JP2016504774A - 超薄型PoPパッケージ - Google Patents
超薄型PoPパッケージ Download PDFInfo
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- JP2016504774A JP2016504774A JP2015555197A JP2015555197A JP2016504774A JP 2016504774 A JP2016504774 A JP 2016504774A JP 2015555197 A JP2015555197 A JP 2015555197A JP 2015555197 A JP2015555197 A JP 2015555197A JP 2016504774 A JP2016504774 A JP 2016504774A
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Abstract
Description
本発明は、半導体のパッケージング及び半導体素子(半導体デバイス、半導体装置)のパッケージング方法に関する。より詳細には、本発明は、PoP(パッケージ・オン・パッケージ)の下部パッケージに関する。
半導体産業では、コストの削減、性能の向上、集積回路の高密度化及びパッケージの高密度化が現在も求められており、それに伴い、パッケージ・オン・パッケージ(PoP)技術が次第に普及している。パッケージを狭小化する取り組みは更に進められ、ダイとパッケージの統合(例えば、プリスタック技術(pre-stacking)又はメモリ技術とシステムオンチップ(systemon a chip、「SoC」)技術の統合)により、パッケージの薄型化が実現されている。このようなプリスタック技術は、薄型で微細なピッチのPoPパッケージのための、非常に重要な要素となった。
Claims (14)
- 半導体素子パッケージであって、
再分配層と、
前記再分配層の上方のカプセル材と、
前記カプセル材の上方の介在層と、
前記カプセル材中に少なくとも部分的に封入されたダイであって、前記ダイが、前記再分配層の上側表面及び前記介在層の下側表面に結合される、ダイと、
前記再分配層の少なくとも一部に前記介在層の少なくとも一部を結合する1つ以上の端子と、
を備え、前記端子が、前記ダイの外周で前記カプセル材中に配置される
ことを特徴とする半導体素子パッケージ。 - 前記ダイが、接着剤層を用いて前記介在層の前記下側表面に結合される
ことを特徴とする請求項1に記載の半導体素子パッケージ。 - 前記介在層の前記ダイとは反対側に配置された1つ以上の追加の端子を介して前記介在層に結合されたメモリパッケージを更に備える
ことを特徴とする請求項1に記載の半導体素子パッケージ。 - 前記追加の端子が、前記ダイの前記外周と前記ダイの上方の両方に配置される
ことを特徴とする請求項3に記載の半導体素子パッケージ。 - 前記介在層が、前記再分配層の少なくとも一部に前記介在層の少なくとも一部を結合する前記1つ以上の端子の位置と、前記介在層の前記ダイとは反対側に配置された前記1つ以上の追加の端子の位置とに対応するルーティングを含む
ことを特徴とする請求項3に記載の半導体素子パッケージ。 - 半導体素子パッケージを形成する方法であって、
介在層を提供することであって、1つ以上の第1の端子が前記介在層の第1の面に結合される、介在層を提供することと、
ダイの外周に配置された前記端子を用いて、前記介在層の前記第1の面に前記ダイを結合することと、
前記ダイ及び前記端子をカプセル材中に少なくとも部分的にカプセル化することと、
前記ダイ及び前記端子に再分配層を結合することと、
を含む
ことを特徴とする半導体素子パッケージを形成する方法。 - 接着剤層を用いて前記ダイを前記介在層に結合することを更に含む
ことを特徴とする請求項6に記載の半導体素子パッケージを形成する方法。 - 前記介在層の前記第1の面とは反対側の第2の面に配置された1つ以上の追加の端子を使用して、前記介在層にメモリパッケージを結合することを更に含む
ことを特徴とする請求項6に記載の半導体素子パッケージを形成する方法。 - 前記再分配層の下側表面に1つ以上の追加の端子を結合することと、マザーボード又はプリント回路板に前記追加の端子を結合することと、を更に含む
ことを特徴とする請求項6に記載の半導体素子パッケージを形成する方法。 - 半導体素子パッケージであって、
介在層と再分配層との間に配置されたモールド材と、
前記モールド材中に少なくとも部分的に封入されたダイであって、前記ダイが、前記再分配層及び前記介在層に結合される、ダイと、
前記再分配層に前記介在層を結合する1つ以上の端子と、
を備え、前記端子が、前記ダイの外周で前記モールド材に配置される
ことを特徴とする半導体素子パッケージ。 - 前記ダイが、接着剤層を用いて前記介在層に結合される
ことを特徴とする請求項10に記載の半導体素子パッケージ。 - 前記介在層の前記ダイとは反対側に配置された1つ以上の追加の端子を更に備え、前記追加の端子が、メモリパッケージに前記パッケージを結合するように構成される
ことを特徴とする請求項10に記載の半導体素子パッケージ。 - 前記再分配層が、前記ダイの前記外周で1つ以上の追加の端子に前記ダイを結合する電気ルーティングを含む
ことを特徴とする請求項10に記載の半導体素子パッケージ。 - 前記介在層が、2層介在層を含む
ことを特徴とする請求項10に記載の半導体素子パッケージ。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US13/753,014 US20140210106A1 (en) | 2013-01-29 | 2013-01-29 | ULTRA THIN PoP PACKAGE |
US13/753,014 | 2013-01-29 | ||
PCT/US2014/012050 WO2014120483A1 (en) | 2013-01-29 | 2014-01-17 | ULTRA THIN PoP PACKAGE |
Publications (1)
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JP2016504774A true JP2016504774A (ja) | 2016-02-12 |
Family
ID=50070699
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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JP2015555197A Pending JP2016504774A (ja) | 2013-01-29 | 2014-01-17 | 超薄型PoPパッケージ |
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US (1) | US20140210106A1 (ja) |
JP (1) | JP2016504774A (ja) |
KR (1) | KR20150109477A (ja) |
CN (1) | CN104969347A (ja) |
TW (1) | TWI585906B (ja) |
WO (1) | WO2014120483A1 (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2018078274A (ja) * | 2016-11-10 | 2018-05-17 | サムソン エレクトロ−メカニックス カンパニーリミテッド. | イメージセンサー装置及びそれを含むイメージセンサーモジュール |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9006030B1 (en) * | 2013-12-09 | 2015-04-14 | Xilinx, Inc. | Warpage management for fan-out mold packaged integrated circuit |
KR102367404B1 (ko) | 2015-08-03 | 2022-02-25 | 삼성전자주식회사 | 반도체 패키지의 제조 방법 |
TWI566356B (zh) | 2015-10-15 | 2017-01-11 | 力成科技股份有限公司 | 封裝結構及其製造方法 |
CN108928802A (zh) * | 2017-05-27 | 2018-12-04 | 北京万应科技有限公司 | 芯片晶圆封装方法、微机电***封装方法及微机电*** |
US10515936B1 (en) | 2018-06-25 | 2019-12-24 | Powertech Technology Inc. | Package structure and manufacturing method thereof |
US10770433B1 (en) | 2019-02-27 | 2020-09-08 | Apple Inc. | High bandwidth die to die interconnect with package area reduction |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20070296065A1 (en) * | 2006-06-27 | 2007-12-27 | Advanced Chip Engineering Technology Inc. | 3D electronic packaging structure having a conductive support substrate |
US20090014858A1 (en) * | 2007-07-09 | 2009-01-15 | Micron Technology, Inc. | Packaged semiconductor assemblies and methods for manufacturing such assemblies |
JP2010205851A (ja) * | 2009-03-02 | 2010-09-16 | Shinko Electric Ind Co Ltd | 半導体装置及びその製造方法、並びに電子装置 |
EP2309535A1 (en) * | 2009-10-09 | 2011-04-13 | Telefonaktiebolaget L M Ericsson (Publ) | Chip package with a chip embedded in a wiring body |
JP2012175099A (ja) * | 2011-02-17 | 2012-09-10 | Samsung Electronics Co Ltd | スルー基板ビアを有するインターポーザを含む半導体パッケージ及びその製造方法 |
Family Cites Families (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3772066B2 (ja) * | 2000-03-09 | 2006-05-10 | 沖電気工業株式会社 | 半導体装置 |
DE102004058395A1 (de) * | 2004-12-03 | 2006-06-08 | Infineon Technologies Ag | Verfahren zum Verdrahten von einem stapelbaren Halbleiterchip und eine Halbleitervorrichtung mit gestapelten Halbleiterchips |
US20070069389A1 (en) * | 2005-09-15 | 2007-03-29 | Alexander Wollanke | Stackable device, device stack and method for fabricating the same |
US7858440B2 (en) * | 2007-09-21 | 2010-12-28 | Infineon Technologies Ag | Stacked semiconductor chips |
TWI360207B (en) * | 2007-10-22 | 2012-03-11 | Advanced Semiconductor Eng | Chip package structure and method of manufacturing |
JP2010147153A (ja) * | 2008-12-17 | 2010-07-01 | Shinko Electric Ind Co Ltd | 半導体装置及びその製造方法 |
US7960827B1 (en) * | 2009-04-09 | 2011-06-14 | Amkor Technology, Inc. | Thermal via heat spreader package and method |
US8383457B2 (en) * | 2010-09-03 | 2013-02-26 | Stats Chippac, Ltd. | Semiconductor device and method of forming interposer frame over semiconductor die to provide vertical interconnect |
US8035235B2 (en) * | 2009-09-15 | 2011-10-11 | Stats Chippac Ltd. | Integrated circuit packaging system with package-on-package and method of manufacture thereof |
US8508954B2 (en) * | 2009-12-17 | 2013-08-13 | Samsung Electronics Co., Ltd. | Systems employing a stacked semiconductor package |
US8951839B2 (en) * | 2010-03-15 | 2015-02-10 | Stats Chippac, Ltd. | Semiconductor device and method of forming conductive vias through interconnect structures and encapsulant of WLCSP |
TWI426587B (zh) * | 2010-08-12 | 2014-02-11 | 矽品精密工業股份有限公司 | 晶片尺寸封裝件及其製法 |
US8941222B2 (en) * | 2010-11-11 | 2015-01-27 | Advanced Semiconductor Engineering Inc. | Wafer level semiconductor package and manufacturing methods thereof |
US8587126B2 (en) * | 2010-12-02 | 2013-11-19 | Tessera, Inc. | Stacked microelectronic assembly with TSVs formed in stages with plural active chips |
US8736065B2 (en) * | 2010-12-22 | 2014-05-27 | Intel Corporation | Multi-chip package having a substrate with a plurality of vertically embedded die and a process of forming the same |
US8466544B2 (en) * | 2011-02-25 | 2013-06-18 | Stats Chippac, Ltd. | Semiconductor device and method of forming interposer and opposing build-up interconnect structure with connecting conductive TMV for electrical interconnect of Fo-WLCSP |
US8597986B2 (en) * | 2011-09-01 | 2013-12-03 | Taiwan Semiconductor Manufacturing Co., Ltd. | System in package and method of fabricating same |
US8552556B1 (en) * | 2011-11-22 | 2013-10-08 | Amkor Technology, Inc. | Wafer level fan out package |
-
2013
- 2013-01-29 US US13/753,014 patent/US20140210106A1/en not_active Abandoned
-
2014
- 2014-01-17 WO PCT/US2014/012050 patent/WO2014120483A1/en active Application Filing
- 2014-01-17 JP JP2015555197A patent/JP2016504774A/ja active Pending
- 2014-01-17 CN CN201480006272.0A patent/CN104969347A/zh active Pending
- 2014-01-17 KR KR1020157023023A patent/KR20150109477A/ko not_active Application Discontinuation
- 2014-01-29 TW TW103103658A patent/TWI585906B/zh active
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20070296065A1 (en) * | 2006-06-27 | 2007-12-27 | Advanced Chip Engineering Technology Inc. | 3D electronic packaging structure having a conductive support substrate |
US20090014858A1 (en) * | 2007-07-09 | 2009-01-15 | Micron Technology, Inc. | Packaged semiconductor assemblies and methods for manufacturing such assemblies |
JP2010205851A (ja) * | 2009-03-02 | 2010-09-16 | Shinko Electric Ind Co Ltd | 半導体装置及びその製造方法、並びに電子装置 |
EP2309535A1 (en) * | 2009-10-09 | 2011-04-13 | Telefonaktiebolaget L M Ericsson (Publ) | Chip package with a chip embedded in a wiring body |
JP2012175099A (ja) * | 2011-02-17 | 2012-09-10 | Samsung Electronics Co Ltd | スルー基板ビアを有するインターポーザを含む半導体パッケージ及びその製造方法 |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2018078274A (ja) * | 2016-11-10 | 2018-05-17 | サムソン エレクトロ−メカニックス カンパニーリミテッド. | イメージセンサー装置及びそれを含むイメージセンサーモジュール |
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CN104969347A (zh) | 2015-10-07 |
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WO2014120483A1 (en) | 2014-08-07 |
US20140210106A1 (en) | 2014-07-31 |
TW201438159A (zh) | 2014-10-01 |
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