JP2017183625A - 半導体装置およびその製造方法 - Google Patents
半導体装置およびその製造方法 Download PDFInfo
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Abstract
Description
そこで、本発明は、耐圧を向上できる半導体装置およびその製造方法を提供することを目的とする。
<第1実施形態>
図1は、本発明の第1実施形態に係る半導体装置1の平面図である。図2は、図1のII-II線に沿う縦断面図である。図3は、図2の一点鎖線IIIで囲まれた部分の拡大断面図である。
アクティブ領域4における半導体層2の表面部には、本発明の第2導電型の不純物拡散領域の一例としてのp型不純物拡散領域6が形成されている。アクティブ領域4は、p型不純物拡散領域6の投影部でもあり、p型不純物拡散領域6は、機能素子の少なくとも一部(機能素子の一部または全部)を構成している。p型不純物拡散領域6は、半導体層2の表面から露出し、その底部が半導体層2内に位置するように形成されており、n−型半導体領域3との間でpn接合部を形成している。
たとえば、p型ウェル領域7の全域を略同様の濃度プロファイルで作り込んだ場合、p型ウェル領域7の外側周縁部9に電界が集中する結果、期待される設計上の耐圧を得ることができないという課題がある。そこで、本実施形態に係る半導体装置1では、p型ウェル領域7の外側周縁部9のp型不純物濃度を、p型ウェル領域7の内側周縁部8のp型不純物濃度よりも低くすることによって、当該外側周縁部9に電界が集中するのを抑制し、半導体装置1の耐圧の向上を図っている。
図2および図3に示されるように、p型ウェル領域7の内方部10は、半導体層2の表面に沿う横方向に略一様な厚さで形成されている。p型ウェル領域7の内方部10の厚さは、当該p型ウェル領域7の表面と底部との間の距離で定義される。本実施形態では、p型ウェル領域7の外側周縁部9の底部は、p型ウェル領域7の内方部10の底部とほぼ等しい深さ位置に形成されている。したがって、p型ウェル領域7の外側周縁部9の底部は、p型ウェル領域7の内方部10の底部とほぼ段差なく繋がっている。これにより、p型ウェル領域7の内方部10の底部とp型ウェル領域7の外側周縁部9の底部との間における不所望な電界集中の発生が抑制されている。
図4のグラフには、第1曲線L1と、第2曲線L2とが示されている。第1曲線L1は、図3のA-A線に沿うp型ウェル領域7の内方部10のp型不純物の濃度プロファイルを示している。一方、第2曲線L2は、図3のB-B線に沿うp型ウェル領域7の外側周縁部9のp型不純物の濃度プロファイルを示している。
本実施形態に係る半導体装置1の耐圧と比較するため、図5に示されるように、参考例に係る半導体装置14を用意した。図5は、参考例に係る半導体装置14のp型ウェル領域7の一部を示す拡大断面図である。図5は、前述の図3に対応する部分の拡大断面図でもある。
以上、本実施形態に係る半導体装置1によれば、p型ウェル領域7の外側周縁部9のp型不純物濃度が、p型ウェル領域7の内側周縁部8(内方部10)のp型不純物濃度よりも選択的に低く設定されている。しかも、p型ウェル領域7は、半導体層2の表面から深さ方向に向かってp型不純物濃度が徐々に低下する濃度プロファイルを有していると共に、内側周縁部8(内方部10)から外側周縁部9に向けて、p型不純物濃度が徐々に低下する濃度プロファイルを有している。したがって、p型不純物濃度の急激な変動が抑制されているから、p型ウェル領域7の外側周縁部9における電界強度を良好に緩和できる。その結果、p型ウェル領域7の外側周縁部9に対する電界集中の発生を良好に抑制できるから、耐圧を効果的に向上できる半導体装置1を提供できる。
図8Aを参照して、半導体装置1を製造するに当たり、機能素子が形成されるアクティブ領域4およびその外側の外周領域5を有し、n−型半導体領域3をその全域に含む半導体層2が準備される(ステップS1)。半導体層2は、たとえばFZ法により製造されたn−型のSi単結晶の半導体ウエハを用いて形成される。次に、たとえばCVD(Chemical Vapor Deposition:化学気相成長)法によって、絶縁材料が半導体層2の表面に堆積されて表面絶縁膜12が形成される(ステップS2)。表面絶縁膜12は、CVD法に代えて熱酸化処理によっても形成できる。この場合、半導体層2の表面に酸化膜からなる表面絶縁膜12が形成される。
これにより、化合物中のp型不純物が半導体層2内に拡散して、半導体層2の表面から深さ方向に向かってp型不純物濃度が徐々に低下する濃度プロファイルを有するp型ウェル領域7が形成される。その後、マスクが除去される。なお、p型不純物を含む化合物が、表面絶縁膜12上に代えて、半導体層2の表面に直接堆積される工程が実行されてもよい。また、前述のp型FLR13は、p型ウェル領域7と別の工程で形成されてもよい。
図9は、本発明の第2実施形態に係る半導体装置21のp型ウェル領域7を示す縦断面図である。図10は、図9の一点鎖線Xで囲まれた部分の拡大断面図である。図9は、前述の図2に対応する部分の縦断面図でもある。図9および図10において、前述の第1実施形態において述べた構成と同様の構成については同一の参照符号を付して説明を省略する。
図11を参照して、本実施形態に係る半導体装置21の製造方法は、保護膜16を形成する工程(ステップS4)の後、熱酸化処理工程(ステップS5)に先立って、p型ウェル領域7の外側周縁部9の一部を選択的に除去する工程(ステップS11)を含む。以下、図12A〜図12Eを参照しつつ、半導体装置21の製造工程について具体的に説明する。
図13は、本発明の第3実施形態に係る半導体装置31を示す平面図である。図14は、図13のXIV-XIV線に沿う縦断面図である。図15は、図13のXV-XV線に沿う縦断面図である。なお、図15は、説明便宜のため、その寸法が図14の寸法よりも拡大されて示されている。図13〜図15において、前述の第1実施形態において述べた構成と同様の構成については同一の参照符号を付して説明を省略する。
前述のLOCOS膜11は、前述の第1実施形態と同様の態様で、p型ウェル領域7を選択的に被覆していると共に、外周領域5における半導体層2の表面を選択的に被覆している。LOCOS膜11は、p型FLR13を選択的に露出させるコンタクト孔39と、n+型チャネルストップ領域37を選択的に露出させる外周除去領域40とを有している。
フィールドプレート41は、各p型FLR13A〜13Dに一つずつ形成されている。各フィールドプレート41は、LOCOS膜11のコンタクト孔39内でp型FLR13A〜13Dに接続されている。最も外側でp型FLR13Dに接続されたフィールドプレート41は、LOCOS膜11上において半導体層2の端面38側に引き出された引き出し部41aを有していてもよい。
図15に示されるように、アクティブ領域4における半導体層2の表面部に形成されたp型不純物拡散領域6は、本実施形態では、IGBTの一部を構成するp型ボディ領域でもある。アクティブ領域4における半導体層2の表面部には、複数のトレンチゲート構造43が形成されている。
以上、本発明の実施形態について説明したが、本発明は、さらに他の形態で実施することもできる。
また、前述の第3実施形態では、機能素子としてIGBTがアクティブ領域4に形成された例について説明した。しかし、p+型半導体領域32の導電型を反転してn+型半導体領域とすることにより、機能素子としてのMISFETが、IGBTに代えてアクティブ領域4に形成された構成とすることもできる。この場合、エミッタメタル36がMISFETのソースメタルに対応し、エミッタ領域47がMISFETのソース領域に対応し、コレクタメタル33がMISFETのドレインメタルに対応する。
その他、特許請求の範囲に記載された事項の範囲で種々の設計変更を施すことが可能である。この明細書および図面から抽出される構成を以下に示す。
項1:機能素子が形成されるアクティブ領域を有する第1導電型の半導体層と、前記半導体層の表面部に前記アクティブ領域に沿って形成され、前記アクティブ領域側に位置する内側周縁部およびその反対側に位置する外側周縁部を有する第2導電型半導体領域とを含み、前記半導体層における前記第2導電型半導体領域の前記外側周縁部が形成された部分が選択的に除去されることにより、前記第2導電型半導体領域の前記外側周縁部の表面と前記第2導電型半導体領域の前記内側周縁部の表面との間に段差部が形成されている、半導体装置。
項3:前記第2導電型半導体領域の前記外側周縁部の底部は、前記第2導電型半導体領域の前記内側周縁部の底部と等しい深さ位置に形成されている、項1または2に記載の半導体装置。
項5:前記第2導電型半導体領域の前記外側周縁部の表面の不純物濃度は、前記内側周縁部の深さ方向に見て、当該内側周縁部の表面から前記外側周縁部の表面までの距離と等しい深さ位置に位置する中間部分の不純物濃度よりも低い、項1〜4のいずれか一項に記載の半導体装置。
項7:前記第2導電型半導体領域は、前記半導体層の表面から深さ方向に向かって不純物濃度が徐々に低下する濃度プロファイルを有している、項1〜6のいずれか一項に記載の半導体装置。
項9:前記絶縁膜は、酸化膜である、項8に記載の半導体装置。
項10:前記第1導電型半導体領域は、n型半導体領域であり、前記第2導電型半導体領域は、p型半導体領域であり、前記第2導電型半導体領域は、p型不純物としてのホウ素を含む、項1〜9のいずれか一項に記載の半導体装置。
Claims (16)
- 機能素子が形成されるアクティブ領域を有する第1導電型の半導体層と、
前記半導体層の表面部に前記アクティブ領域に沿って形成され、前記アクティブ領域側に位置する内側周縁部および前記アクティブ領域とは反対側に位置する外側周縁部を有する第2導電型半導体領域とを含み、
前記第2導電型半導体領域の前記外側周縁部の不純物濃度が、前記第2導電型半導体領域の前記内側周縁部の不純物濃度よりも低くされている、半導体装置。 - 前記第2導電型半導体領域は、前記内側周縁部から前記外側周縁部に向かって不純物濃度が徐々に低下する濃度プロファイルを有している、請求項1に記載の半導体装置。
- 前記第2導電型半導体領域は、前記半導体層の表面から深さ方向に向かって不純物濃度が徐々に低下する濃度プロファイルを有している、請求項1または2に記載の半導体装置。
- 前記第2導電型半導体領域の前記内側周縁部を避けて前記第2導電型半導体領域の前記外側周縁部を被覆するように前記半導体層の表面に形成された酸化膜をさらに含み、
前記酸化膜に被覆された前記第2導電型半導体領域の前記外側周縁部の不純物濃度が、前記酸化膜から露出する前記第2導電型半導体領域の前記内側周縁部の不純物濃度よりも低くされている、請求項1〜3のいずれか一項に記載の半導体装置。 - 前記酸化膜における前記第2導電型半導体領域の前記外側周縁部を被覆する部分は、前記第2導電型半導体領域を形成する第2導電型の不純物と同一の第2導電型の不純物を含む、請求項4に記載の半導体装置。
- 前記半導体層における前記第2導電型半導体領域の前記外側周縁部が形成された部分が選択的に除去されることにより、前記第2導電型半導体領域の前記外側周縁部の表面と前記第2導電型半導体領域の前記内側周縁部の表面との間に段差部が形成されている、請求項1〜5のいずれか一項に記載の半導体装置。
- 前記アクティブ領域における前記半導体層の表面部に形成され、前記機能素子の少なくとも一部を構成する第2導電型の不純物拡散領域をさらに含み、
前記第2導電型半導体領域の前記内側周縁部は、前記不純物拡散領域と接している、請求項1〜6のいずれか一項に記載の半導体装置。 - 前記第2導電型半導体領域は、前記アクティブ領域を取り囲むように形成されている、請求項1〜7のいずれか一項に記載の半導体装置。
- 前記第1導電型半導体領域は、n型半導体領域であり、
前記第2導電型半導体領域は、p型半導体領域であり、
前記第2導電型半導体領域は、p型不純物としてのホウ素を含む、請求項1〜8のいずれか一項に記載の半導体装置。 - 機能素子が形成されるアクティブ領域を有する第1導電型の半導体層を準備する工程と、
前記半導体層の表面部に前記アクティブ領域に沿って第2導電型不純物を選択的に導入することにより、前記アクティブ領域側に位置する内側周縁部および前記アクティブ領域とは反対側に位置する外側周縁部を有する第2導電型半導体領域を形成する工程と、
前記半導体層に熱酸化処理を選択的に施すことにより、前記第2導電型半導体領域の前記内側周縁部を避けて前記第2導電型半導体領域の前記外側周縁部を被覆する酸化膜を形成する工程とを含む、半導体装置の製造方法。 - 前記酸化膜を形成する工程は、前記第2導電型半導体領域の前記外側周縁部から前記第2導電型不純物を吸収させながら前記酸化膜を形成する工程を含む、請求項10に記載の半導体装置の製造方法。
- 前記酸化膜を形成する工程は、前記第2導電型半導体領域の前記外側周縁部の不純物濃度を、前記第2導電型半導体領域の前記内側周縁部の不純物濃度よりも選択的に低くする工程を兼ねている、請求項10または11に記載の半導体装置の製造方法。
- 前記第2導電型半導体領域を形成する工程は、前記第2導電型不純物を前記半導体層の表面部に選択的に注入した後、アニール処理を施すことにより前記半導体層の表面部に前記第2導電型不純物を選択的に導入する工程を含む、請求項10〜12のいずれか一項に記載の半導体装置の製造方法。
- 前記第2導電型半導体領域を形成する工程は、前記第2導電型不純物を含む化合物を前記半導体層の表面上に選択的に堆積させた後、当該化合物に熱を加えることにより前記半導体層の表面部に前記第2導電型不純物を選択的に導入する工程を含む、請求項10〜12のいずれか一項に記載の半導体装置の製造方法。
- 前記酸化膜を形成する工程に先立って、前記半導体層における前記第2導電型半導体領域の前記外側周縁部が形成された部分を選択的に除去することにより、前記第2導電型半導体領域の前記外側周縁部の表面と前記第2導電型半導体領域の前記内側周縁部の表面との間に段差部を形成する工程をさらに含む、請求項10〜14のいずれか一項に記載の半導体装置の製造方法。
- 前記第1導電型半導体領域は、n型半導体領域であり、
前記第2導電型半導体領域は、p型半導体領域であり、
前記第2導電型半導体領域を形成する工程は、p型不純物としてのホウ素を前記半導体層の表面部に導入する工程を含む、請求項10〜15のいずれか一項に記載の半導体装置の製造方法。
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