JP2016507894A - フォトニック構造及び電子構造のための半導体基板及び製造方法 - Google Patents
フォトニック構造及び電子構造のための半導体基板及び製造方法 Download PDFInfo
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- 239000000758 substrate Substances 0.000 title claims abstract description 86
- 239000004065 semiconductor Substances 0.000 title claims description 22
- 238000004519 manufacturing process Methods 0.000 title description 8
- 238000002955 isolation Methods 0.000 claims abstract description 99
- 238000000034 method Methods 0.000 claims abstract description 41
- 238000005530 etching Methods 0.000 claims abstract description 33
- 239000000463 material Substances 0.000 claims abstract description 31
- 238000000206 photolithography Methods 0.000 claims abstract description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 16
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 11
- 229910052710 silicon Inorganic materials 0.000 claims description 11
- 239000010703 silicon Substances 0.000 claims description 11
- 235000012239 silicon dioxide Nutrition 0.000 claims description 8
- 239000000377 silicon dioxide Substances 0.000 claims description 8
- 230000003287 optical effect Effects 0.000 claims description 3
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 2
- 239000011229 interlayer Substances 0.000 claims description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 2
- 239000011810 insulating material Substances 0.000 claims 3
- 238000001020 plasma etching Methods 0.000 claims 1
- 125000006850 spacer group Chemical group 0.000 description 8
- 238000001312 dry etching Methods 0.000 description 4
- 238000005253 cladding Methods 0.000 description 3
- 239000012212 insulator Substances 0.000 description 3
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- 238000000347 anisotropic wet etching Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 239000005380 borophosphosilicate glass Substances 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000010410 layer Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76229—Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
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- G—PHYSICS
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- G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
- G02B6/10—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type
- G02B6/12—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
- G02B6/122—Basic optical elements, e.g. light-guiding paths
- G02B6/1225—Basic optical elements, e.g. light-guiding paths comprising photonic band-gap structures or photonic lattices
-
- G—PHYSICS
- G02—OPTICS
- G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
- G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
- G02B6/10—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type
- G02B6/12—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
- G02B6/13—Integrated optical circuits characterised by the manufacturing method
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- G—PHYSICS
- G02—OPTICS
- G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
- G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
- G02B6/10—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type
- G02B6/12—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
- G02B6/13—Integrated optical circuits characterised by the manufacturing method
- G02B6/136—Integrated optical circuits characterised by the manufacturing method by etching
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
- H01L21/76283—Lateral isolation by refilling of trenches with dielectric material
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- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
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- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
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- G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
- G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
- G02B6/10—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type
- G02B6/12—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
- G02B2006/12083—Constructional arrangements
- G02B2006/121—Channel; buried or the like
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Abstract
Description
Claims (24)
- 異なる深さを有する分離領域の半導体基板への形成方法であって、
エッチングマスク材料を半導体基板上に形成すること、
フォトリソグラフィ工程に単一のレチクルを用いて前記エッチングマスク材料にパターンを形成して、第1トレンチ分離領域及び第2トレンチ分離領域を形成するための第1開口及び第2開口であって、前記第2開口が前記第1開口よりも広い第1開口及び第2開口を画定すること、
前記パターン形成されたエッチングマスク材料を用いて前記半導体基板内の第1トレンチ分離領域及び第2トレンチ分離領域をエッチングすること、
前記第1トレンチ分離領域及び前記第2トレンチ分離領域のそれぞれの内部に分離材料を形成すること、
前記第1トレンチ分離領域内のトレンチ分離材料を残しつつ、前記第2トレンチ分離領域の底部の分離材料を除去して、前記半導体基板を露出させること、
前記第2トレンチ分離領域の深さが前記第1トレンチ分離領域の深さを超えるように、前記第2トレンチ分離領域に前記露出させた半導体基板を追加エッチングすること、
前記深くした第2トレンチ分離領域の内部にトレンチ分離材料を形成すること、
電子デバイスを前記基板上に形成して、第1トレンチ分離領域によって前記電子デバイスを電気的に分離すること、並びに
前記第2トレンチ分離領域内の前記トレンチ分離材料の上にフォトニックデバイスを形成して、前記フォトニックデバイスを前記基板から光学的に分離すること、を含む形成方法。 - 前記第1トレンチ分離領域及び第2トレンチ分離領域をエッチングする際は、前記追加エッチング用のエッチングマスクを形成する分離材料を前記第2トレンチ分離領域の側壁に残しておく、請求項1に記載の方法。
- 前記深くした第2分離領域の内部に前記トレンチ分離材料を形成した後に、前記基板の上面の高さにまで平坦化することをさらに含む、請求項1に記載の方法。
- 前記半導体基板がシリコン基板で構成される、請求項3に記載の方法。
- 前記エッチングマスク材料と前記基板の間にパッド酸化物を形成することをさらに含み、前記単一のレチクルを用いたフォトリソグラフィ工程により、前記エッチングマスク材料及び前記パッド酸化物にパターンを形成する、請求項3に記載の方法。
- 前記パッド酸化物が二酸化ケイ素で構成される、請求項5に記載の方法。
- 前記エッチングマスク材料が窒化ケイ素で構成される、請求項1に記載の方法。
- 前記トレンチ分離材料が二酸化ケイ素で構成される、請求項1に記載の方法。
- 前記第2トレンチ分離領域内部の前記分離材料を異方的にエッチングすることによって前記トレンチ分離材料を除去し、前記半導体基板を露出させることにより、前記トレンチ分離材料の一部を前記第2トレンチ分離領域の側壁に残し、前記露出させた半導体基板の前記追加エッチング用のマスクとして用いる、請求項1に記載の方法。
- 異方性エッチングを用いて前記第2トレンチ分離領域から前記分離材料を除去する、請求項1に記載の方法。
- プラズマエッチングを用いて前記第2トレンチ分離領域から前記分離材料を除去する、請求項1に記載の方法。
- 前記追加エッチングの際は、前記第1トレンチ分離領域の少なくとも2倍の深さの第2トレンチ分離領域を生成する、請求項1に記載の方法。
- 前記第1トレンチ分離領域の深さが約200nm〜約300nmである、請求項12に記載の方法。
- 前記第2トレンチ分離領域の深さが約1.2μm〜約1.5μmである、請求項12に記載の方法。
- 前記第2トレンチ分離領域の幅が前記第1トレンチ分離領域の幅よりも広い、請求項1に記載の方法。
- 前記第2トレンチ分離領域の幅が前記第2トレンチの側壁における分離材料の幅の2倍よりも広い、請求項2に記載の方法。
- 回路構造の形成方法であって、
フォトリソグラフィ工程に単一のレチクルを用いて半導体基板上に設けられたエッチングマスクに、前記基板内の第1トレンチ分離領域及び第2トレンチ分離領域をエッチングするための開口であって、前記第2トレンチ分離領域をエッチングするための前記開口が第1トレンチ分離領域をエッチングするための前記開口よりも広い開口を画定するパターンを形成すること、
前記エッチングマスク内の前記第1開口及び第2開口を用いて前記基板から半導体材料を除去して、前記第1トレンチ分離領域及び第2トレンチ分離領域を設けること、
前記第1トレンチ分離領域及び第2トレンチ分離領域の内部に絶縁材料を形成すること、
前記第2トレンチ分離領域から前記絶縁材料を除去して前記基板を露出させること、
前記第2トレンチ分離領域が前記第1トレンチ分離領域よりも深くなるように、前記露出させた基板を追加エッチングすること、
前記深くした第2トレンチ分離領域に絶縁材料を充填すること、
前記第1トレンチ分離領域及び第2トレンチ分離領域を前記基板の高さにまで平坦化すること、
前記基板上に電子デバイスを形成して、前記第1トレンチ分離領域によって前記電子デバイスを電気的に分離すること、並びに
前記平坦化された第2トレンチ分離領域の上にフォトニックデバイスを形成すること、を含む形成方法。 - 前記第1トレンチ分離領域の幅が約20nm〜約150nmである、請求項19に記載の方法。
- 前記第2トレンチ分離領域の幅が約2μm〜約10μmである、請求項17に記載の方法。
- 前記第2トレンチ分離領域の幅が約2μm〜約4μmである、請求項19に記載の方法。
- 前記第2トレンチ分離領域を前記第1トレンチ分離領域の少なくとも2倍の深さにまでエッチングする、請求項17に記載の方法。
- 前記フォトニックデバイスの両側及び上部に光学的分離領域を作製することをさらに含む、請求項17に記載の方法。
- 前記フォトニックデバイスが導波管、検出器、分岐器、分配器、変調器及び復調器からなる群から選択される、請求項17に記載の方法。
- 前記フォトニックデバイス上部の前記光学的絶縁が層間絶縁構造の一部である、請求項22に記載の方法。
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US13/726,891 | 2012-12-26 | ||
US13/726,891 US8652934B1 (en) | 2012-12-26 | 2012-12-26 | Semiconductor substrate for photonic and electronic structures and method of manufacture |
PCT/US2013/071649 WO2014105319A1 (en) | 2012-12-26 | 2013-11-25 | Semiconductor substrate for photonic and electronic structures and method of manufacture |
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KR102007258B1 (ko) * | 2012-11-21 | 2019-08-05 | 삼성전자주식회사 | 광전 집적회로 기판의 제조방법 |
US8652934B1 (en) * | 2012-12-26 | 2014-02-18 | Micron Technology, Inc. | Semiconductor substrate for photonic and electronic structures and method of manufacture |
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US20140341503A1 (en) | 2014-11-20 |
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US8652934B1 (en) | 2014-02-18 |
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US9305826B2 (en) | 2016-04-05 |
US20150243546A1 (en) | 2015-08-27 |
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