JP2016149524A - パッケージ基板及びその製造方法 - Google Patents
パッケージ基板及びその製造方法 Download PDFInfo
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- 239000000758 substrate Substances 0.000 title claims abstract description 116
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 46
- 239000010410 layer Substances 0.000 claims abstract description 256
- 239000002184 metal Substances 0.000 claims abstract description 124
- 229910052751 metal Inorganic materials 0.000 claims abstract description 124
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 116
- 239000011889 copper foil Substances 0.000 claims abstract description 87
- 238000000034 method Methods 0.000 claims abstract description 32
- 239000012790 adhesive layer Substances 0.000 claims abstract description 21
- 239000004020 conductor Substances 0.000 claims abstract description 21
- 238000007747 plating Methods 0.000 claims abstract description 19
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 40
- 229910052802 copper Inorganic materials 0.000 claims description 29
- 239000010949 copper Substances 0.000 claims description 29
- 239000000463 material Substances 0.000 claims description 22
- 229910052759 nickel Inorganic materials 0.000 claims description 20
- 238000005530 etching Methods 0.000 claims description 7
- 238000010030 laminating Methods 0.000 claims description 3
- 230000004308 accommodation Effects 0.000 description 12
- 229920002120 photoresistant polymer Polymers 0.000 description 7
- 241001424392 Lucia limbaria Species 0.000 description 4
- 238000005520 cutting process Methods 0.000 description 4
- 238000003698 laser cutting Methods 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 230000017525 heat dissipation Effects 0.000 description 3
- 239000011888 foil Substances 0.000 description 1
- 238000007731 hot pressing Methods 0.000 description 1
- 238000000608 laser ablation Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B65—CONVEYING; PACKING; STORING; HANDLING THIN OR FILAMENTARY MATERIAL
- B65D—CONTAINERS FOR STORAGE OR TRANSPORT OF ARTICLES OR MATERIALS, e.g. BAGS, BARRELS, BOTTLES, BOXES, CANS, CARTONS, CRATES, DRUMS, JARS, TANKS, HOPPERS, FORWARDING CONTAINERS; ACCESSORIES, CLOSURES, OR FITTINGS THEREFOR; PACKAGING ELEMENTS; PACKAGES
- B65D65/00—Wrappers or flexible covers; Packaging materials of special type or form
- B65D65/38—Packaging materials of special type or form
- B65D65/40—Applications of laminates for particular packaging purposes
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B32—LAYERED PRODUCTS
- B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
- B32B37/00—Methods or apparatus for laminating, e.g. by curing or by ultrasonic bonding
- B32B37/02—Methods or apparatus for laminating, e.g. by curing or by ultrasonic bonding characterised by a sequence of laminating steps, e.g. by adding new layers at consecutive laminating stations
-
- C—CHEMISTRY; METALLURGY
- C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
- C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
- C25D5/02—Electroplating of selected surface areas
- C25D5/022—Electroplating of selected surface areas using masking means
-
- C—CHEMISTRY; METALLURGY
- C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
- C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
- C25D5/10—Electroplating with more than one layer of the same or of different metals
- C25D5/12—Electroplating with more than one layer of the same or of different metals at least one layer being of nickel or chromium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B32—LAYERED PRODUCTS
- B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
- B32B38/00—Ancillary operations in connection with laminating processes
- B32B38/04—Punching, slitting or perforating
- B32B2038/047—Perforating
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B32—LAYERED PRODUCTS
- B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
- B32B2311/00—Metals, their alloys or their compounds
- B32B2311/12—Copper
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B32—LAYERED PRODUCTS
- B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
- B32B2457/00—Electrical equipment
- B32B2457/08—PCBs, i.e. printed circuit boards
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B32—LAYERED PRODUCTS
- B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
- B32B37/00—Methods or apparatus for laminating, e.g. by curing or by ultrasonic bonding
- B32B37/12—Methods or apparatus for laminating, e.g. by curing or by ultrasonic bonding characterised by using adhesives
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B32—LAYERED PRODUCTS
- B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
- B32B38/00—Ancillary operations in connection with laminating processes
- B32B38/06—Embossing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
- H01L2224/1146—Plating
- H01L2224/11462—Electroplating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15313—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a land array, e.g. LGA
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
- General Chemical & Material Sciences (AREA)
- Parts Printed On Printed Circuit Boards (AREA)
- Structure Of Printed Boards (AREA)
Abstract
Description
20:パッケージ構造
100:第1の基材
110:誘電体層
120:第1の剥離フィルム
130:第2の剥離フィルム
140:銅層
150:ニッケル層
200:第2の基材
200a:上面
200b:下面
210:コア誘電体層
220:第1の銅箔層
230、230a:第2の銅箔層
310:粘着層
320:導電材料層
330:第1のパターン化金属層
340:第2のパターン化金属層
350、360:チップ
A:切断線
B:ブラインドビアホール
C:導電性の貫通ビアホール
L:底面
M:金属バンプ
S:収容溝
U:上面
T:頂面
Claims (10)
- 第1の基材を形成することと、
めっきにより複数の金属バンプを前記第1の基材上に形成し、前記金属バンプが前記第1の基材を部分的に露出することと、
互いに対向する上面と下面、コア誘電体層、第1の銅箔層、第2の銅箔層、複数の収容溝を有する第2の基材を提供し、前記第1の銅箔層と前記第2の銅箔層がそれぞれ前記コア誘電体層の互いに対向する2つの側面上に位置し、前記収容溝が前記下面から延び前記第2の銅箔層と前記コア誘電体層とを貫通し、前記第1の銅箔層を部分的に露出することと、
前記収容溝の内壁上に粘着層を形成することと、
前記第1の基材と前記第2の基材とをラミネートさせ、前記金属バンプを前記収容溝内に収容し、前記金属バンプが前記粘着層を介し前記収容溝内に固定されることと、
前記第1の基材を取り除き、各前記金属バンプの底面が前記第2の基材の前記下面と実質的に同一平面であることと、
前記第2の基材の前記上面から前記金属バンプへと延びる複数のブラインドビアホールを形成することと、
前記第1の銅箔層上及び前記第2の銅箔層上に導電材料層を形成し、前記導電材料層が前記第1の銅箔層、前記第2の銅箔層、前記金属バンプの前記底面を覆い、前記導電材料層が前記ブラインドビアホールを埋め、複数の導電性の貫通ビアホールを定義することと、
前記導電材料層をパターニングし、第1のパターン化金属層と第2のパターン化金属層とを形成し、前記第1のパターン化金属層が前記第1の銅箔層上に位置して前記導電性の貫通ビアホールと接続し、前記第2のパターン化金属層が前記第2の銅箔層上に位置し、前記第1のパターン化金属層と前記第2のパターン化金属層がそれぞれ前記コア誘電体層の2つの前記側面を部分的に露出することと
を含むパッケージ基板の製造方法。 - 前記第1の基材を形成するステップが、
誘電体層、第1の剥離フィルム、第2の剥離フィルム、銅層を提供することと、
前記誘電体層、前記第1の剥離フィルム、前記第2の剥離フィルム、前記銅層をラミネートし、前記第1の剥離フィルムと前記第2の剥離フィルムがそれぞれ前記誘電体層の互いに対向する2つの側面に位置し、前記銅層が前記第1の剥離フィルム上に位置することと、
前記銅層上にニッケル層を形成し、前記ニッケル層が前記銅層を覆う、前記第1の基材を形成することと
を含む、請求項1に記載のパッケージ基板の製造方法。 - 前記金属バンプが前記ニッケル層上に位置し、前記ニッケル層を部分的に露出する、請求項2に記載のパッケージ基板の製造方法。
- 前記金属バンプを形成するステップが、めっき、露光、現像、エッチングにより金属バンプを形成し、前記ニッケル層をめっきシード層として用いることを含む、請求項2に記載のパッケージ基板の製造方法。
- 前記第1の基材を取り除くステップが、
前記第1の剥離フィルムを剥がし処理を介し前記銅層から分離することと、
前記銅層と前記ニッケル層とをエッチング処理を介し取り除き、前記金属バンプの前記底面と前記第2の基材の前記下面を露出することと
を含む、請求項2に記載のパッケージ基板の製造方法。 - 各前記ブラインドビアホールがレーザーブラインドビアホールである、請求項1に記載のパッケージ基板の製造方法。
- 前記導電材料層を形成するステップが、
前記第1の銅箔層と前記第2の銅箔層をめっきシード層として用い、めっきにより前記導電材料層を形成することを含む、請求項1に記載のパッケージ基板の製造方法。 - 互いに対向する上面と下面、コア誘電体層、第1の銅箔層、第2の銅箔層、複数の収容溝を有する基材であって、前記第1の銅箔層と前記第2の銅箔層がそれぞれ前記コア誘電体層の互いに対向する2つの側面に位置し、前記収容溝が前記下面から延び前記第2の銅箔層と前記コア誘電体層とを貫通し、前記第1の銅箔層を部分的に露出することと、
前記収容溝の内壁に設けられる粘着層と、
それぞれ前記収容溝内に設けられる複数の金属バンプであって、前記金属バンプが前記粘着層を介し前記収容溝内に固定され、各前記金属バンプの底面が前記基材の前記下面と実質的に同一平面であることと、
前記第1の銅箔層を貫通し、前記金属バンプへと延びる複数の導電性の貫通ビアホールと、
前記第1の銅箔層を覆い、前記導電性の貫通ビアホールと接続する第1のパターン化金属層と、
前記第2の銅箔層と前記金属バンプの前記底面を覆う第2のパターン化金属層であって、前記第1のパターン化金属層と前記第2のパターン化金属層がそれぞれ前記コア誘電体層の2つの側面を部分的に露出することと
を含む、パッケージ基板。 - 各前記導電性の貫通ビアホールの上面が前記第1のパターン化金属層の上面と実質的に同一平面である、請求項8に記載のパッケージ基板。
- 前記金属バンプが、それに対応する前記導電性の貫通ビアホールと前記第2のパターン化金属層とに接続する、請求項8に記載のパッケージ基板。
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TW104104529A TWI542271B (zh) | 2015-02-11 | 2015-02-11 | 封裝基板及其製作方法 |
TW104104529 | 2015-02-11 |
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TWI584420B (zh) * | 2015-09-16 | 2017-05-21 | 旭德科技股份有限公司 | 封裝載板及其製作方法 |
CN111836451B (zh) * | 2019-04-16 | 2021-12-21 | 北大方正集团有限公司 | 电路板加工方法及电路板 |
CN110856355B (zh) * | 2019-10-08 | 2023-05-26 | 湖南维胜科技电路板有限公司 | 一种具有高散热性能的led电路板制作方法 |
TWI736421B (zh) | 2020-09-17 | 2021-08-11 | 欣興電子股份有限公司 | 電路板及其製造方法 |
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TWI542271B (zh) | 2016-07-11 |
US9458540B2 (en) | 2016-10-04 |
US20160230286A1 (en) | 2016-08-11 |
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