JP2016139719A - 半導体装置 - Google Patents
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 147
- 230000015556 catabolic process Effects 0.000 claims description 19
- 239000012535 impurity Substances 0.000 description 16
- 230000004888 barrier function Effects 0.000 description 10
- 230000000694 effects Effects 0.000 description 5
- 239000002184 metal Substances 0.000 description 5
- 230000003071 parasitic effect Effects 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 239000000370 acceptor Substances 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 239000004020 conductor Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000005484 gravity Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
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Abstract
【解決手段】実施形態に係る半導体装置は、第1領域に設けられた第1導電形の第1半導体層と、第2領域に設けられた第2導電形の第2半導体層と、前記第1半導体層上及び前記第2半導体層上に設けられた第2導電形の第4半導体層と、前記第4半導体層上に設けられた第1導電形の第5半導体層と、前記第5半導体層上の前記第1領域の一部に設けられた第2導電形の第6半導体層と、前記第1領域に設けられた第2電極と、前記第2領域に設けられた第3電極と、を備える。前記第3半導体層と前記第3電極との間の距離、及び前記第2領域における前記第3半導体層と前記第5半導体層との距離のうち、少なくとも一方は、前記3半導体層と前記第2電極との距離よりも短い。
【選択図】図2
Description
以下、図面を参照しつつ、本発明の実施形態について説明する。
先ず、第1の実施形態について説明する。
図1は、本実施形態に係る半導体装置を示す平面図である。
図2は、本実施形態に係る半導体装置を示す断面図である。
図2に示す断面は、図1に示すA−A’線による断面である。
本実施形態に係る半導体装置1においては、IGBT領域R1において、コレクタ電極11、p+形コレクタ層21、n形バッファ層23a、n−−形ベース層24、p形ベース層25、n++形エミッタ層26、エミッタ電極14、トレンチゲート電極12及びゲート絶縁膜31により、pnpn構造を持つIGBTが形成されている。そして、ゲート電極15を介してトレンチゲート電極12の電位を制御することにより、コレクタ電極11からエミッタ電極14に流れる電流の大きさを制御することができる。IGBT領域R1において、非導通時において耐圧を担保する低濃度部分は、n−−形ベース層24におけるn形バッファ層23aとトレンチゲート電極12との間の部分であり、その厚さは、n形バッファ層23aとトレンチゲート電極12との距離L1である。
次に、第2の実施形態について説明する。
図3は、本実施形態に係る半導体装置を示す断面図である。
図3が示す断面は、図1に示すA−A’線による断面に相当する。
本実施形態における上記以外の構成及び作用効果は、前述の第1の実施形態と同様である。
次に、第3の実施形態について説明する。
図4は、本実施形態に係る半導体装置を示す断面図である。
図4が示す断面は、図1に示すA−A’線による断面に相当する。
本実施形態における上記以外の構成及び作用効果は、前述の第1の実施形態と同様である。
次に、第4の実施形態について説明する。
図5は、本実施形態に係る半導体装置を示す断面図である。
図5が示す断面は、図1に示すA−A’線による断面に相当する。
本実施形態における上記以外の構成及び作用効果は、前述の第1の実施形態と同様である。
次に、第5の実施形態について説明する。
図6は、本実施形態に係る半導体装置を示す断面図である。
図6が示す断面は、図1に示すA−A’線による断面に相当する。
本実施形態における上記以外の構成及び作用効果は、前述の第4の実施形態と同様である。
Claims (7)
- 第1電極と、
前記第1電極上の第1領域に設けられ、前記第1電極と電気的に接続された第1導電形の第1半導体層と、
前記第1電極上の第2領域に設けられ、前記第1電極と電気的に接続された第2導電形の第2半導体層と、
前記第1半導体層上及び前記第2半導体層上に設けられ、前記第2半導体層よりも低い第2導電形のキャリア濃度を有する第2導電形の第3半導体層と、
前記第3半導体層上に設けられ、前記第3半導体層よりも低い第2導電形のキャリア濃度を有する第2導電形の第4半導体層と、
前記第4半導体層上に設けられ、第1導電形の第5半導体層と、
前記第1領域において、前記第5半導体層上に設けられた第2導電形の第6半導体層と、
前記第4半導体層、前記第5半導体層及び第6半導体層に第1絶縁膜を介して対面し、前記第1領域に設けられた第2電極と、
前記第4半導体層及び前記第5半導体層に第2絶縁膜を介して対面し、前記第2領域に設けられた第3電極と、
前記第5半導体層、前記第6半導体層及び前記第3電極に接続された第4電極と、
を備え、
前記第3半導体層と前記第3電極との間の距離、及び前記第2領域における前記第3半導体層と前記第5半導体層との距離のうち、少なくとも一方は、前記3半導体層と前記第2電極との距離よりも短い半導体装置。 - 前記第3半導体層における前記第2領域に位置する部分の上面は、前記第3半導体層における前記第1領域に位置する部分の上面よりも上方に位置する請求項1記載の半導体装置。
- 前記第3電極の下端は、前記第2電極の下端よりも下方に位置する請求項1記載の半導体装置。
- 前記第5半導体層における前記第2領域に位置する部分の下面は、前記第3電極の下端よりも下方に位置し、前記第5半導体層における前記第1領域に位置する部分の下面よりも下方に位置している請求項1記載の半導体装置。
- 第1電極と、
前記第1電極上の第1領域に設けられ、前記第1電極と電気的に接続された第1導電形の第1半導体層と、
前記第1電極上の第2領域に設けられ、前記第1電極と電気的に接続された第2導電形の第2半導体層と、
前記第1半導体層上及び前記第2半導体層上に設けられ、前記第2半導体層よりも低い第2導電形のキャリア濃度を有する第2導電形の第3半導体層と、
前記第3半導体層上に設けられ、前記第3半導体層よりも低い第2導電形のキャリア濃度を有する第2導電形の第4半導体層と、
前記第4半導体層上に設けられ、第1導電形の第5半導体層と、
前記第5半導体層上の前記第1領域の一部に設けられ、第2導電形の第6半導体層と、
前記第2領域における前記第4半導体層と前記第5半導体層との間に設けられ、前記第4半導体層よりも高い第2導電形のキャリア濃度を有する第2導電形の第7半導体層と、
前記第4半導体層、前記第5半導体層及び前記第6半導体層に第1絶縁膜を介して対面し、前記第1領域に設けられた第2電極と、
前記第4半導体層、前記第7半導体層及び前記第5半導体層に第2絶縁膜を介して対面し、前記第2領域に設けられた第3電極と、
前記第5半導体層、前記第6半導体層及び前記第3電極に接続された第4電極と、
を備えた半導体装置。 - 前記第1領域における前記第4電極と前記第5電極との間に設けられ、前記第7半導体層よりも低い第2導電形のキャリア濃度を有する第2導電形の第8半導体層をさらに備えた請求項5記載の半導体装置。
- 絶縁ゲートバイポーラトランジスタを有する第1領域と、
ダイオードを有する第2領域と、
を備え、
前記第1領域及び前記第2領域は同じチップ内に形成されており、
前記第2領域の耐圧が前記第1領域の耐圧よりも低い半導体装置。
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
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JP2015014168A JP6392133B2 (ja) | 2015-01-28 | 2015-01-28 | 半導体装置 |
CN201610052225.0A CN105826316A (zh) | 2015-01-28 | 2016-01-26 | 半导体装置 |
US15/006,790 US10297593B2 (en) | 2015-01-28 | 2016-01-26 | Semiconductor device |
TW105102569A TW201628190A (zh) | 2015-01-28 | 2016-01-27 | 半導體裝置 |
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JP2015014168A JP6392133B2 (ja) | 2015-01-28 | 2015-01-28 | 半導体装置 |
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JP2016139719A true JP2016139719A (ja) | 2016-08-04 |
JP6392133B2 JP6392133B2 (ja) | 2018-09-19 |
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Cited By (4)
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US9972675B1 (en) | 2016-11-11 | 2018-05-15 | Mitsubishi Electric Corporation | Power semiconductor device and method therefor |
JP2019016765A (ja) * | 2016-11-17 | 2019-01-31 | 富士電機株式会社 | 半導体装置 |
US11424126B2 (en) | 2020-06-17 | 2022-08-23 | Fuji Electric Co., Ltd. | Semiconductor device and method of manufacturing semiconductor device |
WO2023199932A1 (ja) * | 2022-04-13 | 2023-10-19 | 富士電機株式会社 | 半導体装置および製造方法 |
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US10874787B2 (en) | 2014-12-10 | 2020-12-29 | Medtronic, Inc. | Degassing system for dialysis |
CN106783611A (zh) * | 2017-03-21 | 2017-05-31 | 株洲中车时代电气股份有限公司 | 一种具有栅极内嵌二极管的沟槽栅igbt及其制备方法 |
JP6926012B2 (ja) * | 2018-02-14 | 2021-08-25 | 株式会社東芝 | 半導体装置 |
JP6935351B2 (ja) * | 2018-03-20 | 2021-09-15 | 株式会社東芝 | 半導体装置 |
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JP2021197525A (ja) * | 2020-06-18 | 2021-12-27 | ミツミ電機株式会社 | 半導体装置及びその製造方法 |
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US10297593B2 (en) | 2019-05-21 |
TW201628190A (zh) | 2016-08-01 |
US20160218101A1 (en) | 2016-07-28 |
JP6392133B2 (ja) | 2018-09-19 |
CN105826316A (zh) | 2016-08-03 |
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