JP2016122801A - 半導体装置の製造方法 - Google Patents
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- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical group [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims abstract description 9
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- 150000001805 chlorine compounds Chemical class 0.000 claims description 7
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Abstract
Description
まず、本発明の実施の形態による半導体装置の製造方法がより明確となると思われるため、本発明者によって見出された半導体装置の製造方法における解決しようとする課題について詳細に説明する。
本実施の形態1による半導体装置の製造方法を図1〜図5を用いて説明する。図1は、本実施の形態1による半導体装置の製造方法の流れを説明する工程図である。図2は、本実施の形態1による半導体装置の製造工程を説明する電極パッドの要部断面図である。図3は、本実施の形態1による半導体ウェハ上のフッ素残留量を示すグラフ図である。図4は、本実施の形態1による電極パッドの表面に形成される酸化膜の厚さと熱処理時間との関係を示すグラフ図である。図5は、本実施の形態1による電極パッドの腐食発生率と熱処理時間との関係を示すグラフ図である。
1.ウェハ完成
まず、半導体ウェハの主面(回路形成面、表面とも言う)に集積回路を形成する。例えばシリコン(Si)単結晶からなる半導体ウェハの主面に、電解効果トランジスタ、抵抗および容量などの種々の半導体素子を形成し、これらを、絶縁層と配線層とをそれぞれ複数段積み重ねた多層配線層を介して電気的に接続する。なお、半導体ウェハは、シリコン(Si)に限らず、ガリウムヒ素(GaAs)または炭化珪素(SiC)などの化合物半導体であってもよい。
次に、図2(b)に示すように、電極パッドPADに、例えばタングステン(W)などからなるプローブ針(探針とも言う)を接触させて、半導体ウェハに形成された半導体チップ毎の集積回路の電気的特性を測定し、これをテスターが読み取ることにより半導体チップ毎の良・不良を判定する。
次に、図2(c)に示すように、ウェハテストが終わった後の半導体ウェハに対して熱処理を行うことにより、プローブ痕がある電極パッドPADの表面に、均一な厚さの酸化膜OFを一様に形成する。酸化膜OFは、酸化アルミニウム(Al2O3)膜である。酸化膜OFの厚さが薄い場合は、均一な厚さの酸化膜OFが形成できない可能性がある。一方、酸化膜OFの厚さが厚い場合は、熱処理時間が長くなり、製造TATが増加するという課題が生じ、また、電極パッドPADと、これに接合される導電性部材との接合不良が発生する可能性がある。これらを考慮すると、酸化膜OFの厚さは、2nm〜6nmの範囲が適切であり、また、4nmを中心値とする範囲が最も好適であると考えられる。
その後、後工程へ移送されるまでの間、半導体ウェハはクリーンルーム内に保管される。半導体ウェハを保管する際には、半導体ウェハは、複数枚の半導体ウェハを収納するケースまたは1枚の半導体ウェハを収納するケースなどに梱包される。また、保管が長期間に亘る場合は、半導体ウェハが収納されたケースを梱包袋に入れ、脱気した後に保管される。
図3は、ウェハテスト後に熱処理を行った場合と、熱処理を行わなかった場合における半導体ウェハ上のフッ素残留量を示すグラフ図である。熱処理温度は、250℃であり、熱処理雰囲気は、大気雰囲気である。
本実施の形態2による半導体装置の製造方法を図6および図7を用いて説明する。図6は、本実施の形態2による半導体装置の製造方法の流れを説明する工程図である。図7は、本実施の形態2による半導体装置の製造工程を説明する電極パッドの要部断面図である。
本実施の形態3による半導体装置の製造方法を図8および図9を用いて説明する。図8は、本実施の形態3による半導体装置の製造方法の流れを説明する工程図である。図9は、本実施の形態3による半導体装置の製造工程を説明する電極パッドの要部断面図である。
本実施の形態4による半導体装置の製造方法を図10および図11を用いて説明する。図10は、本実施の形態4による半導体装置の製造方法の流れを説明する工程図である。図11は、本実施の形態4によるウェハテスト後に水洗のみを行った場合と、水洗を行わなかった場合における半導体ウェハ上のフッ素残留量を示すグラフ図である。
ML 配線層
OF 酸化膜
OL1 第1絶縁部材(無機絶縁膜)
OL2 第2絶縁部材(有機絶縁膜)
OP 開口部
PAD 電極パッド(表面電極、パッド電極)
SO 自然酸化膜
Claims (9)
- 以下の工程を含む半導体装置の製造方法:
(a)半導体ウェハの主面上に電極パッドを形成する工程;
(b)前記電極パッドを覆うように、前記半導体ウェハの主面上に絶縁部材を形成する工程;
(c)ハロゲン系ガスを含むエッチングガスを用いたドライエッチング法により前記絶縁部材を加工して、前記電極パッドの表面が露出する開口部を前記絶縁部材に形成する工程;
(d)酸素を含む雰囲気で熱処理を行い、前記電極パッドの露出した表面に酸化膜を形成する工程;
(e)前記(d)工程の後、前記半導体ウェハを保管する工程。 - 請求項1記載の半導体装置の製造方法において、
前記(d)工程における前記熱処理の温度は、200℃から300℃である、半導体装置の製造方法。 - 請求項1記載の半導体装置の製造方法において、
前記(c)工程で、前記開口部に露出した前記電極パッドの表面には、フッ素化合物または塩素化合物が形成される、半導体装置の製造方法。 - 請求項1記載の半導体装置の製造方法において、
前記(c)工程と前記(d)工程との間、または前記(d)工程と前記(e)工程との間に、さらに以下の工程を含む:
(f)前記電極パッドの露出した表面を水洗する工程。 - 請求項1記載の半導体装置の製造方法において、
前記(c)工程と前記(d)工程との間、または前記(d)工程と前記(e)工程との間に、さらに以下の工程を含む:
(g)前記半導体ウェハに形成された半導体チップ毎に、前記電極パッドにプローブ針を接触させて、前記半導体チップ毎の集積回路の電気的特性を測定する工程。 - 請求項1記載の半導体装置の製造方法において、
前記酸化膜の厚さは、2nmから6nmである、半導体装置の製造方法。 - 請求項1記載の半導体装置の製造方法において、
前記酸化膜の厚さは、4nmである、半導体装置の製造方法。 - 請求項1記載の半導体装置の製造方法において、
前記ハロゲン系ガスは、フッ素または塩素である、半導体装置の製造方法。 - 請求項1記載の半導体装置の製造方法において、
前記電極パッドは、アルミニウムを主成分とする導電性材料からなり、前記酸化膜は、酸化アルミニウムからなる、半導体装置の製造方法。
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JP2014263483A JP2016122801A (ja) | 2014-12-25 | 2014-12-25 | 半導体装置の製造方法 |
US14/919,153 US9799572B2 (en) | 2014-12-25 | 2015-10-21 | Manufacturing method of semiconductor device |
US15/720,055 US10153216B2 (en) | 2014-12-25 | 2017-09-29 | Manufacturing method of semiconductor device |
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US20160190022A1 (en) | 2016-06-30 |
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