JP2014033228A - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP2014033228A JP2014033228A JP2013227868A JP2013227868A JP2014033228A JP 2014033228 A JP2014033228 A JP 2014033228A JP 2013227868 A JP2013227868 A JP 2013227868A JP 2013227868 A JP2013227868 A JP 2013227868A JP 2014033228 A JP2014033228 A JP 2014033228A
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Abstract
【解決手段】開口部OP2の径を開口部OP1の径よりも小さくし、かつ、開口部OP2を開口部OP1に内包されるように形成する。これにより、開口部OP1の側面に露出する反射防止膜ARの側面を、開口部OP2を形成している表面保護膜PAS2で覆うことができる。この結果、反射防止膜ARの側面を露出することなく、パッドPDを形成することができる。
【選択図】図8
Description
本実施の形態1における半導体装置を説明する前に、本発明者が見出した新規な課題について図面を参照しながら説明する。
前記実施の形態1では、表面保護膜PAS1に開口部OP1を形成し、開口部OP1の底部に露出する反射防止膜ARを除去した後、表面保護膜PAS2を形成している。そして、この表面保護膜PAS2に開口部OP2を形成することにより、開口部OP2の底部にアルミニウム膜ALが露出したパッドPDを形成している。このとき、パッドPD形成領域に露出しているアルミニウム膜ALの表面は、開口部OP1から露出する反射防止膜ARを除去し、さらに、防蝕処理を施すことにより清浄化されている。
前記実施の形態1では、図8に示すように、開口部OP2を開口部OP1に内包されるように形成し、反射防止膜ARが露出する開口部OP1の側面を表面保護膜OP2で覆うように形成している。このように構成することにより、前記実施の形態1では、電圧印加試験において、開口部OP1の側面に露出する反射防止膜ARと開口部OP2の角部に浸入してくる水分との直接接触を避けることができ、表面保護膜PAS1から表面保護膜PAS2にわたる大きなクラックの発生、および、反射防止膜ARと表面保護膜PAS1からの剥離を抑制することができる顕著な効果が得られるとしている。
前記実施の形態1〜3では、パッドPD近傍の構成について説明したが、本実施の形態4ではガードリング近傍の構成について説明する。まず、ガードリングの構成について説明する。図34は、半導体チップCHPの平面レイアウト構成を示す図である。図34は、前記実施の形態1の図5で示した平面レイアウト図とほぼ同様であるが、半導体チップCHPの周辺領域に沿ってガードリングGRが形成されている。そして、ガードリングGRで囲まれた内側領域にパッドPDが形成されている。このパッドPDは、半導体チップCHPの4辺に沿って形成されている。つまり、半導体チップCHPの4辺に沿って複数のパッドPDが形成されており、このパッドPDの外側を囲むようにガードリングGRが形成されている。このガードリングGRは、半導体チップCHPの内部領域に外部からの不純物や水分が浸入することを防止するために設けられるものであり、防護壁として機能する。すなわち、ガードリングGRで囲まれた半導体チップCHPの内側領域には、パッドPDを含む集積回路が形成されており、この集積回路を形成している領域に不純物(異物)や水分が浸入しないように集積回路を形成している外側領域にガードリングGRが形成されているのである。このように半導体チップCHPにガードリングGRを設けることにより、半導体チップCHPに形成されている集積回路を保護することができ、集積回路の信頼性を向上することができる。
図42は、実施の形態5の半導体装置を示す断面図である。本実施の形態5では、ガードリング形成領域の反射防止膜ARと表面保護膜PAS1を除去せずに残しており、表面保護膜PAS1に開口部OP3を形成していない。そして、表面保護膜PAS2については、ガードリングTGR上に開口部OP4が形成されている構造になっている。
本実施の形態6では、パッドPDの表面領域のうちプローブを接触させるプローブ接触領域に形成されている開口部と、ワイヤを接続するワイヤ接続領域に形成されている開口部の大きさを相違させる例について説明する。
本実施の形態は、反射防止膜AR(窒化チタン膜)の表面に、反射防止絶縁膜ARIが形成されている点が、前記実施の形態1〜6と相違する。以下に、前記実施の形態1との違いを比較して説明する。
AL アルミニウム膜
AR 反射防止膜
ARI 反射防止絶縁膜
CHP 半導体チップ
CK クラック
D ダイサー
GD グラインダ
GR ガードリング
GR1 ガードリング
GR2 ガードリング
GR3 ガードリング
GR4 ガードリング
HDP 表面保護膜
ICA 内部回路領域
IL1 層間絶縁膜
IL2 層間絶縁膜
ILA 層間絶縁膜
ILB 層間絶縁膜
ILC 層間絶縁膜
MR 樹脂
OP1 開口部
OP2 開口部
PAS1 表面保護膜
PAS2 表面保護膜
PD パッド
PDR パッド接続領域
PLG1 プラグ
PLG2 プラグ
PRO プローブ接触領域
SB 半田ボール
TE 端子
TGR ガードリング
TN 窒化チタン膜
TOX 酸化チタン膜
TWL 最上層配線
Vdd 電源配線
Vss 基準電源配線
W ワイヤ
WB 配線基板
WD 溝
WF 半導体ウェハ
WL 配線
X 距離
Claims (6)
- 半導体基板は集積回路形成領域と、前記半導体基板の端部と前記集積回路形成領域との間に設けられ、且つ、前記集積回路形成領域を平面的に囲むように設けられたガードリング形成領域を有し、
前記集積回路形成領域には、
(a1)前記半導体基板の上層に形成された第1パッドと、
(b1)前記第1パッド上に第1開口部が形成された第1表面保護膜と、
(c1)前記第1パッド上に第2開口部が形成され、前記第1パッドおよび前記第1表面保護膜上に形成された第2表面保護膜とが形成され、
前記第1パッドは、
(a11)第1導体膜と、
(a12)前記第1導体膜上に形成された反射防止膜とを有し、
前記第1開口部の内部領域に前記第2開口部が内包され、
前記第1開口部の内部領域では前記反射防止膜が除去されており、
前記ガードリング形成領域には、
(a2)前記半導体基板の上層に形成された第2パッドと、
(b2)前記第2パッド上に形成された前記第1表面保護膜と、
(c2)前記第1表面保護膜上に形成され、第3開口部を有する前記第2表面保護膜とが形成され、
前記第2パッドは、
(a21)前記第1導体膜と、
(a22)前記第1導体膜上に形成された前記反射防止膜とを有することを特徴とする半導体装置。 - 請求項1記載の半導体装置であって、
前記第1導体膜は、アルミニウム膜からなり、
前記反射防止膜は、窒化チタン膜からなることを特徴とする半導体装置。 - 請求項1または2に記載の半導体装置であって、
前記第1表面保護膜は、酸化シリコン膜であり、
前記第2表面保護膜は、窒化シリコン膜であることを特徴とする半導体装置。 - 請求項1〜3のいずれか1項に記載の半導体装置であって、
前記半導体装置は、更に、前記第2開口部内を含む前記第2表面保護膜上に形成された樹脂部材を備え、
前記樹脂部材は、ハロゲンフリー部材から構成されていることを特徴とする半導体装置。 - 請求項4記載の半導体装置であって、
前記ハロゲンフリー部材は、WEEE指令によって定められる部材であることを特徴とする半導体装置。 - 請求項1〜5のいずれか1項に記載の半導体装置であって、
前記ガードリング形成領域と前記半導体基板の端部との間の領域において、前記第2表面保護膜に、前記ガードリング形成領域を平面的に囲むように第4開口部が設けられていることを特徴とする半導体装置。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
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JP2013227868A JP5702844B2 (ja) | 2013-11-01 | 2013-11-01 | 半導体装置 |
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JP2013227868A JP5702844B2 (ja) | 2013-11-01 | 2013-11-01 | 半導体装置 |
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JP2009121850A Division JP5443827B2 (ja) | 2009-05-20 | 2009-05-20 | 半導体装置 |
Publications (2)
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US10181450B2 (en) | 2016-03-31 | 2019-01-15 | Renesas Electronics Corporation | Method of manufacturing semiconductor device |
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JP2006303452A (ja) * | 2005-03-25 | 2006-11-02 | Sanyo Electric Co Ltd | 半導体装置及びその製造方法 |
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JP2006303452A (ja) * | 2005-03-25 | 2006-11-02 | Sanyo Electric Co Ltd | 半導体装置及びその製造方法 |
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