JP2015138801A - 半導体装置の製造方法 - Google Patents
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 208
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 24
- 238000000034 method Methods 0.000 title claims abstract description 20
- 239000000758 substrate Substances 0.000 claims abstract description 157
- 239000013078 crystal Substances 0.000 claims abstract description 85
- 230000007547 defect Effects 0.000 claims abstract description 85
- 239000002245 particle Substances 0.000 claims abstract description 21
- 238000005498 polishing Methods 0.000 claims abstract description 7
- 238000010438 heat treatment Methods 0.000 claims description 8
- 229910052734 helium Inorganic materials 0.000 description 36
- 239000001307 helium Substances 0.000 description 36
- -1 helium ions Chemical class 0.000 description 35
- 238000002347 injection Methods 0.000 description 10
- 239000007924 injection Substances 0.000 description 10
- 238000002513 implantation Methods 0.000 description 7
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 6
- 229910052782 aluminium Inorganic materials 0.000 description 6
- 239000011888 foil Substances 0.000 description 6
- 230000004048 modification Effects 0.000 description 6
- 238000012986 modification Methods 0.000 description 6
- 210000000746 body region Anatomy 0.000 description 4
- 239000000853 adhesive Substances 0.000 description 3
- 230000001070 adhesive effect Effects 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 230000000149 penetrating effect Effects 0.000 description 2
- 238000000137 annealing Methods 0.000 description 1
- 230000002238 attenuated effect Effects 0.000 description 1
- 229910052805 deuterium Inorganic materials 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000005224 laser annealing Methods 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
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- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
- H01L29/66333—Vertical insulated gate bipolar transistors
- H01L29/66348—Vertical insulated gate bipolar transistors with a recessed gate
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
- H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
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Abstract
Description
(半導体装置100の構成)
本実施例の半導体装置の製造方法では、図1に示す半導体装置100を製造する。図1の半導体装置100は、同一の半導体基板10にIGBT(Insulated Gate Bipolar Transistor)領域J1とダイオード領域J2とが混在している逆導通IGBTである。他の例では、半導体装置100は、他の任意の縦型の半導体装置であってもよい。半導体基板10の表面には、絶縁層38及び表面電極60が形成されている。表面電極60は、半導体基板10の表面全面に形成されている。半導体基板10の裏面には、裏面電極90が形成されている。裏面電極90は、半導体基板10の裏面全面に形成されている。
次いで、本実施例の半導体装置100の製造方法を説明する。まず、図3に示すように、Siからなる半導体基板10の表面に、半導体装置100の表面構造を形成する。即ち、半導体基板10の表面に、エミッタ領域20、ボディ領域30、アノード領域50を形成する。また、複数のゲートトレンチ32を形成し、各ゲートトレンチ32の内側に、ゲート絶縁膜34で覆われたトレンチゲート電極36を形成する。各トレンチゲート電極36の上面に絶縁層38を形成する。半導体基板10及び絶縁層38の表面に、表面電極60を形成する。表面電極60は、エミッタ領域20とアノード領域50にオーミック接続される。この半導体装置100の表面構造の各要素は、いずれも周知の方法によって形成される。これにより、ボディ領域30及びアノード領域50よりも深い部分は、半導体装置100のドリフト領域40を構成する。この時点では、表面構造を含む半導体基板10の厚さ(図1のV1方向の厚さ)は、製品である半導体装置100(図1参照)の厚さ(例えば、100μm程度)よりも厚い。この時点の半導体基板10の厚さは、例えば、500μm以上900μm未満である。
20:エミッタ領域
30:ボディ領域
32:ゲートトレンチ
34:ゲート絶縁膜
36:トレンチゲート電極
38:絶縁層
40:ドリフト領域
42:結晶欠陥領域(深さVa)
44:結晶欠陥領域(深さVb)
50:アノード領域
60:表面電極
70:バッファ領域
80:コレクタ領域
85:カソード領域
90:裏面電極
100:半導体装置
110:アルミ箔
120:支持板
122:接着材料
Claims (2)
- 半導体基板の表面側に半導体素子の表面構造を形成する工程と、
前記半導体基板に荷電粒子を打ち込むことによって前記半導体基板内に結晶欠陥を形成する工程と、
前記結晶欠陥を形成する前記工程の後に、前記半導体基板を熱処理する工程と、
熱処理する前記工程の後に、前記半導体基板の表面側に支持板を貼り付ける工程と、
前記支持板が貼り付けられた前記半導体基板の裏面側を研磨して前記半導体基板を薄板化する工程と、
薄板化後の前記半導体基板の裏面側に前記半導体素子の裏面構造を形成する工程、
を備えている、
半導体装置の製造方法。 - 前記結晶欠陥を形成する前記工程は、
前記半導体基板の表面側から第1の深さに結晶欠陥密度の第1のピークが形成されるように前記荷電粒子を打ち込む工程と、
前記半導体基板の表面側から前記第1の深さよりも浅い第2の深さに結晶欠陥密度の第2のピークが形成されるように前記荷電粒子を打ち込む工程、
を備えており、
薄板化する前記工程では、前記半導体基板の前記第1の深さを含む部分を研磨して除去する、
請求項1の製造方法。
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JP2014007985A JP5895950B2 (ja) | 2014-01-20 | 2014-01-20 | 半導体装置の製造方法 |
US14/599,916 US9490127B2 (en) | 2014-01-20 | 2015-01-19 | Method for manufacturing semiconductor device |
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JP2014007985A JP5895950B2 (ja) | 2014-01-20 | 2014-01-20 | 半導体装置の製造方法 |
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JP2015138801A true JP2015138801A (ja) | 2015-07-30 |
JP5895950B2 JP5895950B2 (ja) | 2016-03-30 |
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JP (1) | JP5895950B2 (ja) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9620499B2 (en) | 2014-04-28 | 2017-04-11 | Toyota Jidosha Kabushiki Kaisha | Semiconductor device and method of manufacturing the semiconductor device |
CN108831832A (zh) * | 2018-05-07 | 2018-11-16 | 株洲中车时代电气股份有限公司 | 沟槽台阶栅igbt芯片的制作方法 |
US10381225B2 (en) | 2015-09-16 | 2019-08-13 | Fuji Electric Co., Ltd. | Semiconductor device having IGBT and diode with field stop layer formed of hydrogen donor and helium |
US11043555B2 (en) | 2016-12-16 | 2021-06-22 | Fuji Electric Co., Ltd. | Semiconductor device and manufacturing method of the same |
DE112020003167T5 (de) | 2020-02-12 | 2022-06-30 | Fuji Electric Co., Ltd. | Halbleitervorrichtung und dessen herstellungsverfahren |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP6119593B2 (ja) * | 2013-12-17 | 2017-04-26 | トヨタ自動車株式会社 | 半導体装置 |
JP6277814B2 (ja) * | 2014-03-25 | 2018-02-14 | 株式会社デンソー | 半導体装置 |
JP6787690B2 (ja) * | 2016-05-19 | 2020-11-18 | ローム株式会社 | 高速ダイオード及びその製造方法 |
US11393812B2 (en) * | 2017-12-28 | 2022-07-19 | Fuji Electric Co., Ltd. | Semiconductor device and method of manufacturing semiconductor device |
US10651281B1 (en) * | 2018-12-03 | 2020-05-12 | Globalfoundries Inc. | Substrates with self-aligned buried dielectric and polycrystalline layers |
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JP2008085050A (ja) * | 2006-09-27 | 2008-04-10 | Renesas Technology Corp | 半導体装置の製造方法 |
JP2013197306A (ja) * | 2012-03-19 | 2013-09-30 | Fuji Electric Co Ltd | 半導体装置の製造方法 |
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JPS6459874A (en) * | 1987-08-31 | 1989-03-07 | Toko Inc | Manufacture of variable-capacitance diode |
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US7501332B2 (en) * | 2004-04-05 | 2009-03-10 | Kabushiki Kaisha Toshiba | Doping method and manufacturing method for a semiconductor device |
JP2008172145A (ja) | 2007-01-15 | 2008-07-24 | Toyota Motor Corp | ダイオードの製造方法 |
JP4873002B2 (ja) | 2008-12-12 | 2012-02-08 | 株式会社デンソー | 半導体装置の製造方法 |
US8507352B2 (en) | 2008-12-10 | 2013-08-13 | Denso Corporation | Method of manufacturing semiconductor device including insulated gate bipolar transistor and diode |
JP5929741B2 (ja) | 2012-01-23 | 2016-06-08 | 株式会社デンソー | 半導体装置の製造方法 |
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Patent Citations (2)
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JP2008085050A (ja) * | 2006-09-27 | 2008-04-10 | Renesas Technology Corp | 半導体装置の製造方法 |
JP2013197306A (ja) * | 2012-03-19 | 2013-09-30 | Fuji Electric Co Ltd | 半導体装置の製造方法 |
Cited By (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9620499B2 (en) | 2014-04-28 | 2017-04-11 | Toyota Jidosha Kabushiki Kaisha | Semiconductor device and method of manufacturing the semiconductor device |
US10381225B2 (en) | 2015-09-16 | 2019-08-13 | Fuji Electric Co., Ltd. | Semiconductor device having IGBT and diode with field stop layer formed of hydrogen donor and helium |
US10840099B2 (en) | 2015-09-16 | 2020-11-17 | Fuji Electric Co., Ltd. | Semiconductor device having IGBT and diode with field stop layer formed of hydrogen donor and helium |
US11508581B2 (en) | 2015-09-16 | 2022-11-22 | Fuji Electric Co., Ltd. | Semiconductor device having IGBT and diode with field stop layer formed of hydrogen donor and helium |
US11043555B2 (en) | 2016-12-16 | 2021-06-22 | Fuji Electric Co., Ltd. | Semiconductor device and manufacturing method of the same |
US11552165B2 (en) | 2016-12-16 | 2023-01-10 | Fuji Electric Co., Ltd. | Semiconductor device and manufacturing method of 1HE same |
CN108831832A (zh) * | 2018-05-07 | 2018-11-16 | 株洲中车时代电气股份有限公司 | 沟槽台阶栅igbt芯片的制作方法 |
CN108831832B (zh) * | 2018-05-07 | 2020-08-14 | 株洲中车时代电气股份有限公司 | 沟槽台阶栅igbt芯片的制作方法 |
DE112020003167T5 (de) | 2020-02-12 | 2022-06-30 | Fuji Electric Co., Ltd. | Halbleitervorrichtung und dessen herstellungsverfahren |
Also Published As
Publication number | Publication date |
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US9490127B2 (en) | 2016-11-08 |
US20150206758A1 (en) | 2015-07-23 |
JP5895950B2 (ja) | 2016-03-30 |
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