JP2015026723A - 炭化珪素半導体装置およびその製造方法 - Google Patents
炭化珪素半導体装置およびその製造方法 Download PDFInfo
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- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 title claims abstract description 124
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 3
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Abstract
【解決手段】炭化珪素層101の第2の主面P2には、第2の主面P2から第1の主面P1に向かう方向の深さを有するトレンチTRが設けられており、トレンチTRは、第2の層82と第3の層83とが表出する側壁部SWと、側壁部SWと連なり第1の層81が表出する底部BTとを有する。トレンチTRの深さ方向においてトレンチTRの底部BTの位置は、第2の層82と第1の層81とが接する領域のうち最も第1の主面P1側にある部位82bよりも第2の主面P2側に位置するか、または、深さ方向において部位82bと同じ深さに位置する。
【選択図】図1
Description
まず、本願発明の実施の形態(以下、「本実施の形態」とも記す)の概要を以下の(1)〜(11)に列記して説明する。
以下、本実施の形態に係る炭化珪素半導体装置について、より詳細に説明するが、本発明はこれらに限定されるものではない。
図1に示す実施の形態に係る炭化珪素半導体装置201は、縦型MOSFET(Metal Oxide Semiconductor Field Effect Transistor)として構成されている。炭化珪素半導体装置201は、単結晶基板80と、炭化珪素層101(エピタキシャル層)と、ゲート絶縁膜91と、ゲート電極92と、層間絶縁膜93と、ソース電極94と、ソース配線層95と、ドレイン電極98とを有する。単結晶基板80は、炭化珪素からなり、n型(第1の導電型)を有する。単結晶基板80上には、炭化珪素層101が設けられている。
トレンチTRの側壁部SWは、炭化珪素層101の上面P2に対して傾斜していることが好ましい。すなわち、トレンチTRは開口に向かってテーパ状に拡がっていることが好ましい。具体的には、側壁部SWの面方位は、{0001}面に対して50°以上65°以下傾斜していることが好ましく、(000−1)面に対して50°以上65°以下傾斜していることが好ましい。また、側壁部SWは、特にpボディ層82上の部分において、所定の結晶面(以下、「特殊面」と称する)を有することが好ましい。
次に本実施の形態に係る炭化珪素半導体装置の製造方法について説明する。本実施の形態に係る炭化珪素半導体装置を製造する方法としては、以下に示す第1の製造方法および第2の製造方法が好適である。
図8Aに示すように、まず単結晶基板80上にnドリフト層81が形成される。具体的には、単結晶基板80上におけるエピタキシャル成長によって、nドリフト層81が形成される。このエピタキシャル成長は、たとえば原料ガスとしてシラン(SiH4)とプロパン(C3H8)との混合ガスを用い、キャリアガスとしてたとえば水素ガス(H2)を用いたCVD(Chemical Vapor Deposition)法により行うことができる。この際、不純物として、たとえば窒素(N)やリン(P)を導入することが好ましい。
次に、本実施の形態の炭化珪素半導体装置の別の製造方法について説明する。
次に、図4〜図6を参照して、本実施の形態に係る炭化珪素半導体装置の変形例について説明する。
図4に示す第1の変形例に係る炭化珪素半導体装置401は、nドリフト層81内に埋込領域70を有する点において、図1に示す炭化珪素半導体装置201と異なる。
図5を参照して、第2の変形例に係る炭化珪素半導体装置501を説明する。炭化珪素半導体装置501では、トレンチTRは底面である底部BTと側壁部SWとの境界に角部CNを有しており、角部CNはpボディ層82内に位置している。
図6を参照して、第3の変形例に係る炭化珪素半導体装置601を説明する。炭化珪素半導体装置601では、トレンチTRは底面である底部BTと側壁部SWとの境界に角部CNを有しており、角部CNはnドリフト層81内に位置している。そして、トレンチTRの底面(底部BT)の位置する深さとpボディ層82のうち最も下面P1側にある部位82bの位置する深さとの差異(図6中のT1)と、角部CNとpボディ層82との最短距離(図6のT2)とが、T2<T1となる関係を満たしている。
70 埋込領域
80 単結晶基板
81 nドリフト層(第1の層)
81a 注入領域
82 pボディ層(第2の層)
82b 部位
83 n+層(第3の層)
84 pコンタクト層
91 ゲート絶縁膜
92 ゲート電極
93 層間絶縁膜
94 ソース電極
95 ソース配線層
98 ドレイン電極
101 炭化珪素層
110,111 炭化珪素基板
201,301,401,501,601,701 炭化珪素半導体装置
TR トレンチ
BT 底部
SW 側壁部
CN 角部
CD チャネル方向
P1 下面(第1の主面)
P2 上面(第2の主面)
S1 第1の面
S2 第2の面
SQ,SR 複合面。
Claims (11)
- 第1の主面と、前記第1の主面と反対の第2の主面とを有する炭化珪素層を備え、
前記炭化珪素層は、前記第1の主面を構成し第1の導電型を有する第1の層と、
前記第1の層内に設けられ前記第1の導電型と異なる第2の導電型を有する第2の層と、
前記第1の層から隔てられるように前記第2の層上に設けられ前記第2の主面の一部を構成しかつ前記第1の導電型を有する第3の層と、を含み、
前記炭化珪素層の前記第2の主面には、前記第2の主面から前記第1の主面に向かう方向の深さを有するトレンチが設けられており、
前記トレンチは、前記第2の層と前記第3の層とが表出する側壁部と、前記側壁部と連なり前記第1の層が表出する底部とを有し、さらに、
前記側壁部および前記底部の各々を覆うゲート絶縁膜と、
前記ゲート絶縁膜上に設けられたゲート電極と、を備え、
前記トレンチの深さ方向において前記トレンチの前記底部の位置は、前記第2の層と前記第1の層とが接する領域のうち最も前記第1の主面側にある部位よりも前記第2の主面側に位置するか、または、前記深さ方向において前記部位と同じ深さに位置する、炭化珪素半導体装置。 - 前記側壁部において前記第2の層には、面方位{0−33−8}を有する第1の面を含む表面が設けられている、請求項1に記載の炭化珪素半導体装置。
- 前記トレンチの前記底部は、前記側壁部と交差する方向に伸びる底面を含み、
前記トレンチは、前記底面と前記側壁部との境界部に角部を有し、
前記角部は、前記第2の層内に位置する、請求項1または請求項2に記載の炭化珪素半導体装置。 - 前記トレンチの前記底部は、前記側壁部と交差する方向に伸びる底面を含み、
前記トレンチは、前記底面と前記側壁部との境界部に角部を有し、
前記角部は、前記第1の層内に位置し、
前記底面の位置する深さと前記部位の位置する深さとの差異をT1として表わし、前記角部と前記第2の層との最短距離をT2として表わした場合に、T2<T1となる関係を満たす、請求項1または請求項2に記載の炭化珪素半導体装置。 - 前記底部を覆う前記ゲート絶縁膜の部分は、前記側壁部を覆う前記ゲート絶縁膜の部分よりも厚い、請求項1〜請求項4のいずれか1項に記載の炭化珪素半導体装置。
- 前記第1の層内に、前記第2の導電型を有する埋込領域を含み、
前記埋込領域は、前記第1の層によって前記第2の層から隔てられており、かつ前記トレンチの前記側壁部および前記底部の各々から離れている、請求項1〜請求項5のいずれか1項に記載の炭化珪素半導体装置。 - 前記第1の導電型はn型であり、前記第2の導電型はp型である、請求項1〜請求項6のいずれか1項に記載の炭化珪素半導体装置。
- 第1の導電型を有する第1の層と、前記第1の層内に設けられ前記第1の導電型と異なる第2の導電型を有する第2の層と、前記第1の層から隔てられるように前記第2の層上に設けられ前記第1の導電型を有する第3の層とを含む炭化珪素基板を準備する工程と、
前記第3の層および前記第2の層の一部を除去することにより、前記第3の層を貫通し前記第2の層に到る側壁部と、前記第2の層の露出面を含む底部とを有するトレンチを形成する工程と、
前記第2の層の前記露出面に前記第1の導電型の不純物を注入することにより、前記トレンチの前記底部から前記第1の層にまで伸びる前記第1の導電型を有する注入領域を形成する工程と、を備え、
前記注入領域は、前記第1の層と一体となり、さらに、
前記トレンチの前記側壁部および前記底部を覆うゲート絶縁膜を形成する工程と、
前記ゲート絶縁膜を介して前記トレンチ上にゲート電極を形成する工程と、を備える、炭化珪素半導体装置の製造方法。 - 第1の導電型を有する第1の層と、前記第1の層内に離間して設けられ前記第1の導電型とは異なる第2の導電型を有する2つの第2の層と、前記第1の層および前記第2の層上に設けられ前記第1の導電型を有する第3の層とを含む炭化珪素基板を準備する工程と、
2つの前記第2の層の間の領域上から、前記第3の層を開口することにより、前記第1の層を露出させ、前記第3の層を貫通し前記第2の層に到る側壁部と、前記第1の層の露出面を含む底部とを有するトレンチを形成する工程と、
前記トレンチの前記側壁部および前記底部を覆うゲート絶縁膜を形成する工程と、
前記ゲート絶縁膜を介して前記トレンチ上にゲート電極を形成する工程と、を備える、炭化珪素半導体装置の製造方法。 - 前記炭化珪素基板を準備する工程は、イオン注入により、前記第1の層内に、前記第2の層と前記第3の層とを形成する工程を含む、請求項8または請求項9に記載の炭化珪素半導体装置の製造方法。
- 前記炭化珪素基板を準備する工程は、エピタキシャル成長により、前記第1の層上に前記第2の層と前記第3の層とを形成する工程を含む、請求項8または請求項9に記載の炭化珪素半導体装置の製造方法。
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