JP2013542597A - バイポーラノンパンチスルー電力半導体デバイス - Google Patents
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Abstract
【選択図】 図2
Description
第1の導電型のドリフト層と、
ドリフト層上の第1の主側部の方向で配置され、ドリフト層に直接に接続されている、第2の導電型の第1の層と、
を有する、少なくとも2層の構造を具備し、第1の層は、第1の層の厚さまで配置され、第1の層の厚さは、最大の深さとして測定され、この層は、第1の主側部に正射影され、第1の主側部から最大の深さまで延在している。
1´ ダイオード
10 先行技術のPCT
2 ウェーハ
22 内側領域
23 ウェーハの厚さ
24 終端領域
26 ドリフト層
3 カソード接点
31 カソード側
4 アノード接点
41 アノード側
5 ベース層
51 ベース層の深さ
52 ベース層の厚さ
53 負のベベル
54 第1の終端層
55 第1の終端層の深さ
56 第1の終端層の厚さ
57 第1のマスク
58 第1のエッジ層
59 第1のエッジ層の深さ
50 第1のエッジ層の厚さ
6 アノード層
61 アノード層の深さ
62 アノード層の厚さ
64 第2の終端層
65 第2の終端層の深さ
66 第2の終端層の厚さ
67 第2のマスク
68 第2のエッジ層
69 第2のエッジ層の深さ
60 第2のエッジ層の厚さ
7 カソード層
71 カソード層の深さ
8 カソードの短い領域
81 カソードの短い領域の深さ
9 ガードリング
91 ガードリングの深さ
95 ゲート接点
Claims (15)
- 半導体のウェーハ(2)と、
前記ウェーハの第1の主側部上に形成されている第1の電気接点と、
前記第1の電気接点と反対側の、前記ウェーハの第2の主側部上に形成されている第2の電気接点と、
を具備する、バイポーラノンパンチスルー電力半導体デバイスであって、
前記半導体のウェーハ(2)は、異なる導電型の複数の層を有する少なくとも2層の構造を具備し、
前記少なくとも2層の構造は、
第1の導電型のドリフト層(26)と、
前記ドリフト層(26)の前記第1の主側部の方向で直接に接続され、且つ前記第1の電気接点に接触している、第2の導電型の第1の層と、
を具備し、
前記ウェーハ(2)は、
内側領域(22)であって、前記第1と第2の主側部間で測定される一定のウェーハの厚さ(23)を有している、前記内側領域(22)と、
終端領域(24)であって、前記内側領域(22)を囲んでおり、且つ少なくとも第1の主側部において、ウェーハの厚さ(23)が負のベベルで減少している、前記終端領域(24)と、
を具備し、
前記第1の層は、第1の層の深さまで延在し、
前記第1の層の深さは、前記内側領域(22)内において前記第1の主側部が配置されている平面から測定され、
前記ドリフト層は、ドリフト層の深さまで延在し、
前記内側領域(22)内において、前記ドリフト層の深さは、前記内側領域(22)内において前記第1の主側部が配置されている平面から測定され、
前記第2の導電型の第2の層は、前記第2の終端領域(24)において、第1の主側部上に配置され、
前記第2の層は、第2の層の深さまで配置され、
前記第2の層の深さは、前記内側領域(22)内において前記第1の主側部が配置されている平面から測定され、
前記第2の層の深さは、前記第1の層の深さよりも深く、且つ前記ドリフト層の深さよりも浅く、
前記第2の層の最大ドーピング濃度は、前記第1の層の最大ドーピング濃度よりも低く、
前記第1の層の深さは、せいぜい45μm、特にせいぜい30μmである、
ことを特徴とする、バイポーラノンパンチスルー電力半導体デバイス。 - 前記バイポーラノンパンチスルー電力半導体デバイスは、
前記第1の主側部上における前記第1の導電型のカソード層(7)であって、前記第1の電気接点が前記第1の層と前記カソード層(7)とに接触するように配置されている、前記カソード層(7)と、
前記第2の主側部上における前記第2の導電型の第3の層であって、前記第2の主側部から測定される第3の層の深さまで配置されている、前記第3の層と、
を具備し、
前記第2の導電型の第4の層は、前記終端領域(24)において、前記第2の主側部上に、前記第2の主側部から測定される第4の層の深さまで配置され、
前記第4の層の深さは、前記第3の層の深さよりも大きく、
前記第3の層の深さは、特にせいぜい45μm、特に30μmである、
ことを特徴とする、請求項1に記載のバイポーラノンパンチスルー電力半導体デバイス。 - 前記終端領域(24)において、前記ウェーハの厚さ(23)は、負のベベルで減少し、
前記負のベベルは、特にせいぜい5°である1つの角度を有するか、又は、
特にせいぜい5°である、前記内側領域(22)により近い第1の角度と、特にせいぜい15°である、前記ウェーハのエッジにより近い第2の角度とを有する、
ことを特徴とする、請求項1又は2に記載のバイポーラノンパンチスルー電力半導体デバイス。 - 前記第1の層の深さのうちの少なくとも1つが、前記第2の層の深さの少なくとも4分の1、特に10分の1まであることと、
前記第3の層の深さが、前記第4の層の深さの少なくとも4分の1、特に10分の1まであることと、
を特徴とする、請求項1乃至3の何れか1項に記載のバイポーラノンパンチスルー電力半導体デバイス。 - 前記第1の層の深さと前記第3の層の深さとのうちの少なくとも一方は、少なくとも8μm、特に少なくとも10μmである、
ことを特徴とする、請求項1乃至4の何れか1項に記載のバイポーラノンパンチスルー電力半導体デバイス。 - 前記第1の層は、一定の第1の層の深さを有する連続層として形成され、
前記第1の層は、終端領域(24)の中に横方向に延在し、
前記第2の層は、前記第1の層と前記ドリフト層との間に配置されている、
ことを特徴とする、請求項1乃至5の何れか1項に記載のバイポーラノンパンチスルー電力半導体デバイス。 - 前記第2の層のうちの少なくとも1つが、前記第1の層に接続されていることと、
前記第4の層が、前記第3の層に接続されていることと、
を特徴とする、請求項1乃至6の何れか1項に記載のバイポーラノンパンチスルー電力半導体デバイス。 - 前記第2の層のうちの少なくとも1つが、前記第1の電気接点に接続されていることと、
前記第4の層が、前記第2の電気接点に接続されていることと、
を特徴とする、請求項1乃至7の何れか1項に記載のバイポーラノンパンチスルー電力半導体デバイス。 - 前記第4の層は、前記第3層よりも低い最大ドーピング濃度を有する、
ことを特徴とする、請求項1乃至8の何れか1項に記載のバイポーラノンパンチスルー電力半導体デバイス。 - バイポーラノンパンチスルー電力半導体デバイスは、カソード層の深さ(71)を有する前記第1の導電型のカソード層(7)を、前記第1又は第2の主側部のうちの一方の主側部上に具備し、
前記カソード層(7)と同じ主側部に配置されている、前記第1又は第3の層の深さは、前記カソード層の深さ(71)よりも大きい、
ことを特徴とする、請求項1乃至9の何れか1項に記載のバイポーラノンパンチスルー電力半導体デバイス。 - 前記バイポーラノンパンチスルー電力半導体デバイスは、前記第2の導電型の第3の層を具備し、
前記第2の導電型の前記第3の層は、前記第2の主側部上において、前記第2の主側部から測定される第3の層の深さまで配置され、
前記第2の導電型の複数のガードリング(9)は、前記終端領域(24)において前記第2の主側部上に配置されている、
ことを特徴とする、請求項1又は3乃至10の何れか1項に記載のバイポーラノンパンチスルー電力半導体デバイス。 - バイポーラノンパンチスルー電力半導体デバイスを製造する方法であって、
前記バイポーラノンパンチスルー電力半導体デバイスは、
第1の主側部上の第1の電気接点と、
前記第1の主側部と反対側の第2の主側部上の第2の電気接点と、
異なる導電型の複数の層を有する少なくとも2層の構造と、
を具備しており、
前記方法は、少なくとも以下の製造するステップ、即ち、
第1の導電型のウェーハ(2)を与えるステップと、
前記ウェーハの内側領域(22)をカバーしている第1のマスク(57)を前記第1の主側部上に加え、前記内側領域(22)を囲んでいる終端領域(24)における前記第1の主側部に複数のイオンを加え、前記終端領域(24)における前記複数のイオンを前記ウェーハの中に第2の層の深さまで拡散させることによって、弱くドープされた第2の層を前記第1の主側部上に生成するステップと、
前記第1のマスク(57)を取り除くステップと、
前記第1の主側部に複数のイオンを加え、前記ウェーハ(2)の中であって、第2の層の深さよりも浅い、前記第1の主側部からせいぜい45μm、特に30μmの第1の層の深さの中に、前記複数のイオンを拡散させることによって、前記第2の層よりも高度にドープされた第1の層を生成するステップと、
前記第1と第2の電気接点を、前記ウェーハ(2)上であって、前記内側領域(22)上に加えるステップと、
前記終端領域(24)における前記第1の主側部からウェーハの材料を部分的に取り除くことによって、前記終端領域(24)における前記第1の主側部上に、前記ウェーハの負のベベルを生成するステップと、
を含む、方法。 - 前記内側領域(22)をカバーする第2のマスク(67)を、前記第2の主側部上に加え、前記内側領域(22)を囲んでいる前記終端領域(24)における前記第2の主側部(22)に、複数のイオンを加え、前記終端領域(24)における前記ウェーハ(2)の中に第4の層の深さまで前記複数のイオンを拡散させることによって、第4の層を前記第2の主側部上に生成し、
前記第2のマスク(67)を取り除き、
前記第2の主側部に複数のイオンを加え、前記ウェーハ(2)の中であって、第4の層の深さよりも浅い第3の層の深さの中に、前記複数のイオンを拡散させることによって、第3の層を前記第2の主側部上に生成し、
前記終端領域(24)における前記第2の側部からウェーハの材料を部分的に取り除くことによって、前記終端領域(24)における前記第2の主側部に、前記ウェーハの負のベベルを生成する、
ことを特徴とする、請求項12に記載の方法。 - 前記第2の層のうちの少なくとも1つが、140μm未満の深さを有することか、又は、
前記第4の層が、140μm未満の深さを有すること、
を特徴とする、請求項12又は13に記載の方法。 - 前記第1の終端層のうちの少なくとも1つが、50μmを超える深さを有することか、又は、
前記第2の終端層が、50μmを超える深さを有すること、
を特徴とする、請求項12乃至14の何れか1項に記載の方法。
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