JP2013513156A - RFID tag built-in inlay, card including the same, and manufacturing method of RFID tag built-in inlay - Google Patents

RFID tag built-in inlay, card including the same, and manufacturing method of RFID tag built-in inlay Download PDF

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JP2013513156A
JP2013513156A JP2012541943A JP2012541943A JP2013513156A JP 2013513156 A JP2013513156 A JP 2013513156A JP 2012541943 A JP2012541943 A JP 2012541943A JP 2012541943 A JP2012541943 A JP 2012541943A JP 2013513156 A JP2013513156 A JP 2013513156A
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pattern circuit
pad
rfid tag
film layer
external pad
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JP5527674B2 (en
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リ，ジョンギ
ナ，ギョンロク
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サムウォン エフエー カンパニー，リミテッド
イーモト カンパニー，リミテッド
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/07749—Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/0772—Physical layout of the record carrier
    • G06K19/07722—Physical layout of the record carrier the record carrier being multilayered, e.g. laminated sheets
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/07743—External electrical contacts
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/07749—Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card
    • G06K19/07766—Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card comprising at least a second communication arrangement in addition to a first non-contact communication arrangement
    • G06K19/07769—Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card comprising at least a second communication arrangement in addition to a first non-contact communication arrangement the further communication means being a galvanic interface, e.g. hybrid or mixed smart cards having a contact and a non-contact interface
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/07749—Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card
    • G06K19/07773—Antenna details
    • G06K19/07777—Antenna details the antenna being of the inductive type
    • G06K19/07779—Antenna details the antenna being of the inductive type the inductive antenna being a coil
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/07749—Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card
    • G06K19/07773—Antenna details
    • G06K19/07777—Antenna details the antenna being of the inductive type
    • G06K19/07779—Antenna details the antenna being of the inductive type the inductive antenna being a coil
    • G06K19/07783—Antenna details the antenna being of the inductive type the inductive antenna being a coil the coil being planar

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Credit Cards Or The Like (AREA)
  • Manufacturing Of Printed Wiring (AREA)

Abstract

【課題】ＲＦＩＤタグ内蔵型インレイを製造するためのＲＦＩＤタグ製造方法を提供すること。
【解決手段】本発明は、樹脂で充填された樹脂領域、及び所定のパターンをなす非樹脂領域が形成されたマスターの表面をメッキし、非樹脂領域上に複数のパターン回路部を形成する段階と、複数のパターン回路部が形成されたマスターの上側にコアフィルム層をボンディングする段階と、コアフィルム層を金属マスターから分離しながら前記複数のパターン回路部をコアフィルム層側に転写させる段階と、複数のパターン回路部の間の空間に絶縁部を形成する段階と、絶縁部上で前記複数のパターン回路部同士を電気的に連結するジャンパー線を形成する段階とを含んでなる。これにより、ＲＦＩＤタグ内蔵型インレイを容易に製造することができる。
【選択図】図６An RFID tag manufacturing method for manufacturing an inlay with a built-in RFID tag is provided.
The present invention includes a step of plating a surface of a master on which a resin region filled with a resin and a non-resin region having a predetermined pattern are formed, and forming a plurality of pattern circuit portions on the non-resin region. And bonding the core film layer on the upper side of the master on which the plurality of pattern circuit portions are formed; transferring the plurality of pattern circuit portions to the core film layer side while separating the core film layer from the metal master; Forming an insulating part in a space between the plurality of pattern circuit parts, and forming a jumper wire for electrically connecting the plurality of pattern circuit parts on the insulating part. Thereby, an RFID tag built-in inlay can be easily manufactured.
[Selection] Figure 6

Description

ＲＦＩＤタグ内蔵型インレイ、これを含むカード、及びＲＦＩＤタグ内蔵型インレイの製造方法に係り、より詳しくは、マスターを用いたメッキ過程によって容易に製造することが可能なＲＦＩＤタグ内蔵型インレイ、これを含むカード、及びＲＦＩＤタグ内蔵型インレイの製造方法に関する。   The present invention relates to an RFID tag built-in inlay, a card including the same, and an RFID tag built-in inlay manufacturing method, and more particularly, an RFID tag built-in inlay that can be easily manufactured by a plating process using a master. It is related with the manufacturing method of the card | curd containing and RFID tag built-in type inlay.

最近、無線技術の発達に伴い、後払い制ハイパスカードから交通カード、銀行カードに至るまで様々な分野でＲＦＩＤ（Ｒａｄｉｏ Ｆｒｅｑｕｅｎｃｙ Ｉｄｅｎｔｉｆｉｃａｔｉｏｎ）システム又はコンビネーション型スマートカードシステムが使用されている。コンビネーション型スマートカードシステムとは、ＩＣチップがカードの表面に露出しているタイプのスマートカードを用いるシステムを意味する。   Recently, with the development of wireless technology, RFID (Radio Frequency Identification) systems or combination type smart card systems are used in various fields ranging from postpaid high-pass cards to transportation cards and bank cards. The combination type smart card system means a system using a smart card of a type in which an IC chip is exposed on the surface of the card.

ＲＦＩＤシステムは、基本的に、ＲＦＩＤタグ及びＲＦＩＤリードから構成される。ＲＦＩＤタグにはアンテナ回路パターンが内蔵される。具体的には、１３．５ＭＨｚ回路パターンは、コイルの形に製作され、外部からの電磁波によって電気エネルギーを誘導し、或いはＲＦＩＤ ＩＣチップから送信しようとする信号を外部へ放射する機能を行うことができる。よって、ＲＦＩＤタグ内蔵型インレイの製造において、その回路パターンの製造工程とＩＣチップの回路連結部としてのパッド部の形成は重要な部分を占める。   The RFID system basically includes an RFID tag and an RFID lead. An RFID circuit incorporates an antenna circuit pattern. Specifically, the 13.5 MHz circuit pattern is manufactured in the shape of a coil, and performs a function of inducing electrical energy by an external electromagnetic wave or radiating a signal to be transmitted from the RFID IC chip to the outside. it can. Therefore, in the manufacture of the RFID tag built-in type inlay, the manufacturing process of the circuit pattern and the formation of the pad portion as the circuit connecting portion of the IC chip occupy important parts.

従来では、ＲＦＩＤタグ内蔵型のインレイ回路パターンを製作しようとする場合、コイルを直接基板上で複数回巻いてコアフィルム層に固定させる工程や、コアフィルムと銅箔とがラミネートされた基板上にエッチング回路パターンを製作する工程などを行った。   Conventionally, when an inlay circuit pattern with a built-in RFID tag is to be manufactured, a process of winding a coil directly on a substrate a plurality of times and fixing it to a core film layer, or a substrate on which a core film and a copper foil are laminated A process for producing an etching circuit pattern was performed.

ところが、コイルを直接基板上に集積させる方式は、工程上の難しさがあり、量産にも不適であるという問題点があった。また、エッチングを用いる場合は、回路パターンの間隔を精密に保ちながらインレイに製造し難いため、回路パターン同士が重なるショート（ｓｈｏｒｔ）現象が生じるおそれがあるという問題点があって、ＲＦＩＤタグインレイ又はコンビネーション型カードの生産に適用することが難しいという問題点があった。   However, the method of directly integrating the coil on the substrate has a problem in that it is difficult to process and is not suitable for mass production. In addition, when etching is used, it is difficult to manufacture an inlay while maintaining a precise interval between circuit patterns. Therefore, there is a problem that a short phenomenon may occur in which circuit patterns overlap with each other. There was a problem that it was difficult to apply to the production of combination cards.

特に、従来の技術によれば、回路パターンの接続部、すなわちパッド部の実現が別途の工程で行われて量産性に劣るという問題点が指摘されてきた。よって、より便利な方式で精密な構造のＲＦＩＤタグ内蔵型インレイを製造することが可能な製造方法に関する開発必要性が台頭している。   In particular, according to the conventional technique, it has been pointed out that the circuit pattern connection portion, that is, the pad portion is realized in a separate process and is inferior in mass productivity. Therefore, there is a need for development related to a manufacturing method capable of manufacturing an inlay with a built-in RFID tag having a precise structure in a more convenient manner.

本発明は、上述した問題点を解決するために案出されたもので、その目的は、樹脂領域及び非樹脂領域を含むマスターを用いてメッキ方式でＲＦＩＤタグの回路パターンを製作して、便利にＲＦＩＤタグ内蔵型インレイを製造することが可能なＲＦＩＤタグ内蔵型インレイの製造方法、この方法によって製造されるＲＦＩＤタグ内蔵型インレイ、及びこれを含むカードを提供することにある。   The present invention has been devised to solve the above-mentioned problems, and its purpose is to manufacture a RFID tag circuit pattern by a plating method using a master including a resin region and a non-resin region. An RFID tag built-in type inlay capable of producing an RFID tag built-in type inlay, an RFID tag built-in type inlay produced by this method, and a card including the same.

上記目的を達成するために、本発明の一実施例に係るＲＦＩＤタグ内蔵型インレイの製造方法は、樹脂で充填された樹脂領域、及び所定のパターンをなす非樹脂領域が形成されたマスターの表面をメッキし、前記非樹脂領域上に複数のパターン回路部を形成する段階と、前記複数のパターン回路部が形成されたマスターの上側にコアフィルム層をボンディングする段階と、前記コアフィルム層を分離して前記複数のパターン回路部を前記コアフィルム層側に転写させる段階と、前記複数のパターン回路部の間の空間に絶縁部を形成する段階と、前記絶縁部上で前記複数のパターン回路部同士を電気的に連結するジャンパー線を形成する段階と、を含んでなる。   In order to achieve the above object, a method of manufacturing an RFID tag built-in inlay according to an embodiment of the present invention includes a resin surface filled with resin and a surface of a master on which a non-resin region having a predetermined pattern is formed. Separating the core film layer from the step of forming a plurality of pattern circuit portions on the non-resin region, bonding the core film layer on the master on which the plurality of pattern circuit portions are formed, and separating the core film layer And transferring the plurality of pattern circuit portions to the core film layer side, forming an insulating portion in a space between the plurality of pattern circuit portions, and the plurality of pattern circuit portions on the insulating portion. Forming jumper wires that electrically connect each other.

ここで、前記複数のパターン回路部は、前記コアフィルム層の表面の縁部に沿って巻線された形の第１導電部、及び前記コアフィルム層の表面から前記第１導電部の内側に形成された第２導電部を含んでもよい。   Here, the plurality of pattern circuit parts are wound around the edge of the surface of the core film layer, and the first conductive part is formed from the surface of the core film layer to the inside of the first conductive part. The formed second conductive part may be included.

前記第１導電部の両端にはそれぞれ第１外部パッド及び第１内部パッドが形成され、前記第２導電部の両端にはそれぞれ第２外部パッド及び第２内部パッドが形成されてもよい。   A first external pad and a first internal pad may be formed on both ends of the first conductive part, respectively, and a second external pad and a second internal pad may be formed on both ends of the second conductive part, respectively.

一方、本ＲＦＩＤタグ内蔵型インレイの製造方法は、前記複数のパターン回路部上に、前記第１内部パッド及び第２内部パッドそれぞれの少なくとも一部を露出させるカバーレイ層を形成する段階と、前記カバーレイ層の露出した部分に、前記第１内部パッド及び第２内部パッドそれぞれと電気的に連結されるＲＦＩＤチップを配置する段階と、をさらに含んでもよい。   On the other hand, the RFID tag built-in inlay manufacturing method includes forming a cover lay layer on the plurality of pattern circuit portions to expose at least a part of each of the first internal pad and the second internal pad; The method may further include disposing an RFID chip electrically connected to each of the first inner pad and the second inner pad on the exposed portion of the coverlay layer.

前記絶縁部は、前記第１外部パッドと前記第２外部パッドとの間の空間に形成されてもよい。   The insulating part may be formed in a space between the first external pad and the second external pad.

一方、前記ジャンパー線を形成する段階は、前記第１外部パッド及び前記第２外部パッドそれぞれの少なくとも一部と、前記絶縁部の少なくとも一部を露出させるマスクを形成する段階と、前記露出した部分に導電性物質をプリントして前記第１外部パッドと前記第２外部パッドとを互いに連結するジャンパー線を形成する段階と、前記マスクを除去する段階とを含んでもよい。   Meanwhile, forming the jumper line includes forming a mask that exposes at least a part of each of the first external pad and the second external pad and at least a part of the insulating part, and the exposed part. Forming a jumper line connecting the first external pad and the second external pad to each other by printing a conductive material, and removing the mask.

前記マスターの非樹脂領域を離型処理する段階をさらに含んでもよい。   The method may further include a step of releasing the non-resin region of the master.

上述したような実施例において、前記樹脂はテフロンであってもよい。   In the embodiment as described above, the resin may be Teflon.

前記ＲＦＩＤタグは１３．５６ＭＨｚ用ＲＦＩＤタグであってもよい。   The RFID tag may be a 13.56 MHz RFID tag.

一方、本発明の一実施例に係るＲＦＩＤタグ内蔵型インレイは、コアフィルム層と、前記コアフィルム層の表面の縁部に沿って巻線された形の第１導電部と、前記コアフィルム層の表面から前記第１導電部の内側に形成された第２導電部と、前記第１導電部の一端に形成される第１内部パッドと、前記第１導電部の他端に形成される第１外部パッドと、前記第２導電部の一端に形成される第２内部パッドと、前記第２導電部の他端に形成される第２外部パッドと、前記第１外部パッドと前記第２外部パッドとの間の空間に形成された絶縁部と、前記絶縁部上に形成され、前記第１外部パッドと前記第２外部パッドとを電気的に連結するジャンパー線と、を含んでなる。   Meanwhile, an RFID tag built-in inlay according to an embodiment of the present invention includes a core film layer, a first conductive portion wound along an edge of a surface of the core film layer, and the core film layer. A second conductive part formed inside the first conductive part from the surface of the first conductive pad, a first internal pad formed at one end of the first conductive part, and a second conductive part formed at the other end of the first conductive part. A first external pad; a second internal pad formed at one end of the second conductive portion; a second external pad formed at the other end of the second conductive portion; the first external pad and the second external An insulating part formed in a space between the pad and a jumper line formed on the insulating part and electrically connecting the first external pad and the second external pad.

一方、本発明の一実施例に係るカードは、コアフィルム層と、前記コアフィルム層の表面の縁部に沿って巻線された形の第１導電部と、前記コアフィルム層の表面から前記第１導電部の内側に形成された第２導電部と、前記第１導電部の一端に形成される第１内部パッドと、前記第１導電部の他端に形成される第１外部パッドと、前記第２導電部の一端に形成される第２内部パッド、前記第２導電部の他端に形成される第２外部パッド、前記第１外部パッドと前記第２外部パッドとの間の空間に形成された絶縁部と、前記絶縁部上に形成され、前記第１外部パッドと前記第２外部パッドとを電気的に連結するジャンパー線と、前記第１導電部及び前記第２導電部が形成されている前記コアフィルム層の全面を覆いながら、前記第１内部パッド及び前記第２内部パッドそれぞれの少なくとも一部を露出させるカバーレイ層と、前記露出した部分で前記第１内部パッド及び前記第２内部パッドそれぞれに電気的に連結されるＲＦＩＤチップと、を含んでもよい。   Meanwhile, a card according to an embodiment of the present invention includes a core film layer, a first conductive portion wound along an edge of a surface of the core film layer, and the surface of the core film layer. A second conductive portion formed inside the first conductive portion; a first internal pad formed at one end of the first conductive portion; a first external pad formed at the other end of the first conductive portion; A second internal pad formed at one end of the second conductive part, a second external pad formed at the other end of the second conductive part, and a space between the first external pad and the second external pad An insulating portion formed on the insulating portion; a jumper wire formed on the insulating portion to electrically connect the first external pad and the second external pad; and the first conductive portion and the second conductive portion. The first inner pad while covering the entire surface of the formed core film layer And a cover lay layer that exposes at least a part of each of the second internal pads, and an RFID chip that is electrically connected to each of the first internal pads and the second internal pads at the exposed portions. Good.

好ましくは、前記ジャンパー線によって連結される前記第１導電部及び前記第２導電部は１３．５６ＭＨｚ用ＲＦＩＤタグに使用される回路パターンを構成してもよい。   Preferably, the first conductive part and the second conductive part connected by the jumper wire may constitute a circuit pattern used for a 13.56 MHz RFID tag.

上述したような本発明の様々な実施例によれば、マスターを用いてＲＦＩＤタグ内蔵型インレイ、及びこれを含むカードを便利かつ迅速に製造することができる。特に、マスターの表面には樹脂領域と非樹脂領域が設けられ、非樹脂領域でのみメッキが行われてＲＦＩＤ回路パターンを精密に製作することができる。マスターは繰り返し使用できる。   According to various embodiments of the present invention as described above, an RFID tag built-in inlay and a card including the same can be conveniently and quickly manufactured using a master. In particular, a resin region and a non-resin region are provided on the surface of the master, and plating can be performed only in the non-resin region, so that an RFID circuit pattern can be precisely manufactured. The master can be used repeatedly.

本発明の一実施例に係るＲＦＩＤタグ内蔵型インレイを製造するためのマスター構成の一例を示す平面図である。It is a top view which shows an example of the master structure for manufacturing the RFID tag built-in type inlay based on one Example of this invention. 図１のマスターの断面を示す断面図である。It is sectional drawing which shows the cross section of the master of FIG. 図１のマスターを用いてＲＦＩＤタグ内蔵型インレイを製造する過程を説明するための断面図である。It is sectional drawing for demonstrating the process in which an RFID tag built-in type inlay is manufactured using the master of FIG. 図１のマスターを用いてＲＦＩＤタグ内蔵型インレイを製造する過程を説明するための断面図である。It is sectional drawing for demonstrating the process in which an RFID tag built-in type inlay is manufactured using the master of FIG. 図１のマスターを用いてＲＦＩＤタグ内蔵型インレイを製造する過程を説明するための断面図である。It is sectional drawing for demonstrating the process in which an RFID tag built-in type inlay is manufactured using the master of FIG. 図５の断面図に対応する平面図である。FIG. 6 is a plan view corresponding to the cross-sectional view of FIG. 5. 複数のパターン回路部の間の空間に絶縁部を形成する過程を説明するための平面図である。It is a top view for demonstrating the process in which an insulation part is formed in the space between several pattern circuit parts. 複数のパターン回路部の間を連結するジャンパー線を製造する過程を説明するための平面図である。It is a top view for demonstrating the process of manufacturing the jumper wire which connects between some pattern circuit parts. 複数のパターン回路部の間を連結するジャンパー線を製造する過程を説明するための平面図である。It is a top view for demonstrating the process of manufacturing the jumper wire which connects between some pattern circuit parts. ＲＦＩＤタグ回路パターン上にカバーレイ層及びＲＦＩＤチップを搭載してＲＦＩＤタグ内蔵型インレイを完成する過程を説明するための平面図である。It is a top view for demonstrating the process which mounts a cover-lay layer and an RFID chip on an RFID tag circuit pattern, and completes an RFID tag built-in type inlay. ＲＦＩＤタグ回路パターン上にカバーレイ層及びＲＦＩＤチップを搭載してＲＦＩＤタグ内蔵型インレイを完成する過程を説明するための平面図である。It is a top view for demonstrating the process which mounts a cover-lay layer and an RFID chip on an RFID tag circuit pattern, and completes an RFID tag built-in type inlay.

以下に添付図面を参照しながら、本発明について具体的に説明する。
図１は本発明の一実施例に係るＲＦＩＤタグ製造方法に使用されるマスターの構成を示す模式図である。 Hereinafter, the present invention will be specifically described with reference to the accompanying drawings.
FIG. 1 is a schematic diagram showing the configuration of a master used in an RFID tag manufacturing method according to an embodiment of the present invention.

図１によれば、マスター１００の表面には樹脂領域１１０及び非樹脂領域１２０、１３０が設けられる。樹脂領域１１０とは、マスター１００の表面に設けられた溝（ｇｒｏｏｖｅ）の内部に樹脂が充填された部分を意味する。非樹脂領域１２０、１３０とは、マスター１００の表面上における、樹脂が充填されていない部分を意味する。図１の場合、非樹脂領域１２０、１３０は、第１導電部を形成するために設けられた第１領域１２０と、第２導電部を形成するために設けられた第２領域１３０に区分される。   According to FIG. 1, a resin region 110 and non-resin regions 120 and 130 are provided on the surface of the master 100. The resin region 110 means a portion in which a resin is filled in a groove provided on the surface of the master 100. The non-resin regions 120 and 130 mean portions on the surface of the master 100 that are not filled with resin. In the case of FIG. 1, the non-resin regions 120 and 130 are divided into a first region 120 provided for forming the first conductive part and a second region 130 provided for forming the second conductive part. The

一方、マスター１００は、ＲＦＩＤタグの回路パターンを製作するための一種の型枠、すなわち金型の役目を示す部分である。すなわち、非樹脂領域１２０、１３０上には導電性物質が形成され、パターン回路部をなす。したがって、非樹脂領域１２０、１３０はＲＦＩＤタグに埋め込まれる回路パターンに対応する形状に製作される。   On the other hand, the master 100 is a part of a form for producing a circuit pattern of the RFID tag, that is, a part that functions as a mold. That is, a conductive material is formed on the non-resin regions 120 and 130 to form a pattern circuit portion. Therefore, the non-resin regions 120 and 130 are manufactured in a shape corresponding to the circuit pattern embedded in the RFID tag.

図１のマスター１００は多様な方式で製作できる。一例として、マスター１００はフォトエッチング（Ｐｈｏｔｏｌｉｔｈｏ−Ｅｔｃｈｉｎｇ）方式で製作された金属エッチングマスターであってもよい。マスター１００が金属を含む形で具現される場合、金属マスターと呼ばれてもよい。   The master 100 of FIG. 1 can be manufactured in various ways. As an example, the master 100 may be a metal etching master manufactured by a photo-etching method. When the master 100 is embodied in a form containing metal, it may be called a metal master.

一方、樹脂領域１１０に充填される樹脂としては、耐薬品性に優れる、或いは特定の処理（例えば、熱処理など）後に非粘着性が優秀になる特性を持つ任意の物質が使用できる。具体的には、フッ素系高分子樹脂、特にフルオロエチレン樹脂が使用できる。一例として、ポリテトラフルオロエチレン樹脂を使用してもよい。或いは、シリコン系高分子樹脂を使用してもよい。   On the other hand, as the resin filled in the resin region 110, any substance having excellent chemical resistance or non-adhesive properties after a specific treatment (for example, heat treatment) can be used. Specifically, a fluoropolymer resin, particularly a fluoroethylene resin can be used. As an example, polytetrafluoroethylene resin may be used. Alternatively, a silicon-based polymer resin may be used.

フッ素系高分子樹脂として、特に、米国デュポン社がＰＴＦＥ（Ｐｏｌｙ Ｔｅｔｒａ Ｆｌｕｏｒｏ Ｅｔｈｙｌｅｎｅ）樹脂に対して商標登録したテフロン（Ｔｅｆｌｏｎ）が例示できる。テフロンは、一般プラスチックに比べて耐熱性、耐薬品性、研磨性、耐低温性、電気絶縁性、及び高周波特性に優れるうえ、特異な非粘着性及び低摩擦特性があるため、本パターン構造物の製作に使用するには適する。   An example of the fluorine-based polymer resin is Teflon, which is registered as a trademark by PT DuPont for PTFE (Poly Tetra Fluoro Ethylene) resin. Teflon is superior in heat resistance, chemical resistance, abrasiveness, low temperature resistance, electrical insulation, and high frequency characteristics compared to general plastics, and has unique non-adhesiveness and low friction characteristics. Suitable for use in manufacturing.

図２は図１のマスター１００のＡ−Ｂ線に沿った断面図である。図２によれば、マスター１００は表面上の所定の形状の溝が設けられ、その溝の内部に樹脂が充填されることにより樹脂領域１１０を構成し、樹脂領域１１０を除いた残り部分は非樹脂領域１２０を構成する。樹脂領域１１０の深さ及び面積はマスター１００の製造工程の条件によって様々に変更できる。   FIG. 2 is a cross-sectional view taken along line AB of the master 100 of FIG. According to FIG. 2, the master 100 is provided with a groove having a predetermined shape on the surface, and the resin is filled in the groove to form the resin region 110, and the remaining portion except for the resin region 110 is non- A resin region 120 is formed. The depth and area of the resin region 110 can be variously changed according to the conditions of the manufacturing process of the master 100.

図３〜図５は本発明の一実施例に係るＲＦＩＤタグの製造方法を説明するための断面図である。   3 to 5 are cross-sectional views for explaining a method of manufacturing an RFID tag according to an embodiment of the present invention.

図３に示すように、樹脂領域１１０及び非樹脂領域１２０、１３０が設けられたマスター１００の表面に対してメッキを施し、パターン回路部１４１、１４２を形成する。   As shown in FIG. 3, the surface of the master 100 provided with the resin region 110 and the non-resin regions 120 and 130 is plated to form the pattern circuit portions 141 and 142.

メッキ作業はニッケルや銀、銅などの金属を用いて行われる。具体的には、硫酸銅メッキ液などの銅メッキ液を用いて、銅メッキ浴で略３０℃で５分〜１５分間メッキすることにより、パターン回路部１４１、１４２を形成することができる。この場合、メッキ電源は直流又はパルス電源を用いることができる。パターン回路部１４１、１４２の厚さはメッキ時間又はメッキ電源の制御によって調整することができる。すなわち、直流又はパルス電源の印加時間やパルス幅の変調、電流密度などを制御することにより、パターン回路部１４１、１４２の厚さを適切に調整することができる。   The plating operation is performed using a metal such as nickel, silver, or copper. Specifically, the pattern circuit portions 141 and 142 can be formed by plating using a copper plating solution such as a copper sulfate plating solution in a copper plating bath at approximately 30 ° C. for 5 to 15 minutes. In this case, the plating power source can be a direct current or a pulse power source. The thicknesses of the pattern circuit portions 141 and 142 can be adjusted by controlling the plating time or the plating power source. That is, the thickness of the pattern circuit portions 141 and 142 can be appropriately adjusted by controlling the application time of the direct current or pulse power source, the modulation of the pulse width, the current density, and the like.

複数のパターン回路部１４１、１４２のうち、第１パターン回路部１４１は非樹脂領域の第１領域１２０に対応する部分に形成されたメッキ物質を意味し、第２パターン回路部１４２は非樹脂領域の第２領域１３０に対応する部分に形成されたメッキ物質を意味する。   Among the plurality of pattern circuit portions 141 and 142, the first pattern circuit portion 141 means a plating material formed in a portion corresponding to the first region 120 of the non-resin region, and the second pattern circuit portion 142 is a non-resin region. This means a plating material formed in a portion corresponding to the second region 130.

したがって、第１パターン回路部１４１は、マスター１００の縁部に沿って巻線される形態であり、第２パターン回路部１４２は、第１パターン回路部１４１の内側に形成され、第１パターン回路部１４１から一定の距離離れた形態であってもよい。   Therefore, the first pattern circuit unit 141 is wound along the edge of the master 100, and the second pattern circuit unit 142 is formed inside the first pattern circuit unit 141, and the first pattern circuit unit The form away from the part 141 by the fixed distance may be sufficient.

一方、本発明の他の実施例によれば、メッキに先立ち、非樹脂領域１２０、１３０の表面を離型処理することができる。すなわち、パターン回路部１４１、１４２がメッキにより形成された後、後続の工程でコアフィルム層（図示せず）側に転写されなければならないので、分離が容易でなければならない。このために、非樹脂領域１２０、１３０の表面を予め離型処理しておくことができる。   On the other hand, according to another embodiment of the present invention, the surfaces of the non-resin regions 120 and 130 can be released before plating. That is, after the pattern circuit portions 141 and 142 are formed by plating, the pattern circuit portions 141 and 142 must be transferred to the core film layer (not shown) side in a subsequent process. For this reason, the surfaces of the non-resin regions 120 and 130 can be subjected to a release treatment in advance.

このような状態で図４のようにコアフィルム層２００をマスター１００にボンディングさせる。   In this state, the core film layer 200 is bonded to the master 100 as shown in FIG.

図４に示すように、コアフィルム層２００は結合剤層２１０及び支持層２２０を含む。   As shown in FIG. 4, the core film layer 200 includes a binder layer 210 and a support layer 220.

ボンディング過程を具体的に説明すると、まず、別途設けられた支持層２２０の表面に結合剤を塗り付け、結合剤層２１０を形成する。これにより、形成された結合剤層２１０がマスター１００の表面に向かうように、コアフィルム層２００とマスター１００とを結合させる。   The bonding process will be described in detail. First, a binder is applied to the surface of the support layer 220 provided separately to form the binder layer 210. As a result, the core film layer 200 and the master 100 are bonded so that the formed binder layer 210 faces the surface of the master 100.

結合過程は、減圧性粘着剤などと同じ物性を示す結合剤がコートされたポリエステルフィルム又はポリ塩化ビニルフィルムをパターン回路部１４１、１４２側に結合させる方式で行われ得る。   The bonding process may be performed by a method in which a polyester film or a polyvinyl chloride film coated with a bonding agent having the same physical properties as a pressure-sensitive adhesive is bonded to the pattern circuit portions 141 and 142 side.

具体的には、ポリエステル系ホットメルト液又はホットメルトフィルムが結合剤として使用できる。このような結合剤は、物質層の表面でコート、乾燥、硬化又はラミネートなどの工程を経て結合フィルムの形で具現され、コアフィルム層２００をマスター１００側に結合させることができる。   Specifically, a polyester hot melt liquid or a hot melt film can be used as a binder. Such a binder may be embodied in the form of a bonding film through a process such as coating, drying, curing, or laminating on the surface of the material layer, and the core film layer 200 may be bonded to the master 100 side.

また、コアフィルム層２００の支持層２２０は、ＲＦＩＤタグ又はカードに通常使用するプラスチック材質、すなわちポリエステルフィルム又はポリ塩化ビニルフィルムなどが使用でき、その他に、紙材質、金属、ゴムなどの様々な材質が使用できる。但し、金属のように導電性を有する支持層２２０を使用する場合、パターン回路部１４１、１４２におけるＲＦ受信及び放射作業が正常的に行われるように支持層２２０の表面上に絶縁処理が施されてもよい。   Further, the support layer 220 of the core film layer 200 can be made of a plastic material normally used for an RFID tag or a card, that is, a polyester film or a polyvinyl chloride film. Can be used. However, when a conductive support layer 220 such as a metal is used, an insulating process is performed on the surface of the support layer 220 so that RF reception and radiation work in the pattern circuit portions 141 and 142 is performed normally. May be.

一方、結合工程はラミネート設備によっても行われ得る。ラミネート（ｌａｍｉｎａｔｉｎｇ）とは、内容物をポリエステルなどの薄いフィルム又はガラスなどのシートの間に挟んだ後、貼り合わせる工程を意味する。具体的には、ローラーや熱板、熱板内蔵ローラーなどを用いて熱と圧力を加えて接着させる熱ラミネート（ｈｏｔ ｌａｍｉｎａｔｉｎｇ）工程などが使用できる。   On the other hand, the bonding step can also be performed by a laminating facility. Laminating means a process in which contents are sandwiched between thin films such as polyester or sheets such as glass and then bonded together. Specifically, a hot laminating process in which heat and pressure are applied using a roller, a hot plate, a hot plate built-in roller, or the like can be used.

結合工程は、粘着剤と同じ物性を示す結合剤の場合には常温で行われ得る。   In the case of a binder having the same physical properties as the pressure-sensitive adhesive, the bonding step can be performed at room temperature.

結合剤層２１０及び支持層２２０は、後続の工程でパターン回路部１４１、１４２と共にマスター１００から分離され、パターン回路部１４１、１４２を支持する。   The binder layer 210 and the support layer 220 are separated from the master 100 together with the pattern circuit portions 141 and 142 in a subsequent process, and support the pattern circuit portions 141 and 142.

図４では結合剤層２１０が樹脂領域１１０と一定の距離離れているものと示しているが、結合過程で結合剤層２１０が樹脂領域１１０と接してもよい。   Although FIG. 4 shows that the binder layer 210 is separated from the resin region 110 by a certain distance, the binder layer 210 may be in contact with the resin region 110 in the bonding process.

図４に示すように、コアフィルム層２００がマスター１００にボンディングされた後、所定の時間が経過すると、コアフィルム層２００をマスター１００から分離させる。この過程で、マスター１００の表面に形成されていたパターン回路部１４１、１４２がコアフィルム層２００上に転写される。   As shown in FIG. 4, after the core film layer 200 is bonded to the master 100, the core film layer 200 is separated from the master 100 when a predetermined time elapses. In this process, the pattern circuit portions 141 and 142 formed on the surface of the master 100 are transferred onto the core film layer 200.

図５はパターン回路部１４１、１４２が転写されたコアフィルム層２００の構成を示す模式図である。図５によれば、パターン回路部１４１、１４２は結合剤層２１０内に一定の部分挿入されているが、これは一例に該当し、結合剤層２１０の表面にパターン回路部１４１、１４２が固定されてもよく、支持層２２０の表面にまで達するほどパターン回路部１４１、１４２が挿入されていてもよい。   FIG. 5 is a schematic diagram showing the configuration of the core film layer 200 to which the pattern circuit portions 141 and 142 are transferred. According to FIG. 5, the pattern circuit portions 141 and 142 are partially inserted into the binder layer 210, but this is an example, and the pattern circuit portions 141 and 142 are fixed to the surface of the binder layer 210. The pattern circuit portions 141 and 142 may be inserted so as to reach the surface of the support layer 220.

図６は図５の断面図に対応する平面図である。   FIG. 6 is a plan view corresponding to the cross-sectional view of FIG.

図６によれば、第１パターン回路部１４１はコアフィルム層２００の縁部に沿って複数回巻線された形で形成され、第２パターン回路部１４２は第１パターン回路部１４１の内側の空間に配置される。図６において、第２パターン回路部１４２は一本の線みたいに示されているが、第２パターン回路部１４２もコイルの形に製作されてもよい。すなわち、第１パターン回路部１４２の内側面に沿って少なくとも１回巻線される形で第２パターン回路部１４２を具現することもできる。また、必ずしも２つのパターン回路部が形成されるべき必要はなく、実施例によって３つ以上のパターン回路部が形成されてもよい。   Referring to FIG. 6, the first pattern circuit unit 141 is formed by being wound a plurality of times along the edge of the core film layer 200, and the second pattern circuit unit 142 is formed on the inner side of the first pattern circuit unit 141. Arranged in space. In FIG. 6, the second pattern circuit unit 142 is shown as a single line, but the second pattern circuit unit 142 may also be manufactured in the form of a coil. That is, the second pattern circuit unit 142 may be implemented by being wound at least once along the inner surface of the first pattern circuit unit 142. In addition, two pattern circuit portions are not necessarily formed, and three or more pattern circuit portions may be formed according to the embodiment.

図６の第１パターン回路部１４１の両端のうち、一端には第１内部パッド１４１−ａが形成され、他端には第１外部パッド１４１−ｂが形成される。そして、第２パターン回路部１４２の両端のうち、一端には第２内部パッド１４２−ａが形成され、他端には第２外部パッド１４２−ｂが形成される。すなわち、各パターン回路部は、パターンをなす線部分と、その線の両端に設けられるパッドとからなる。   A first internal pad 141-a is formed at one end of the both ends of the first pattern circuit unit 141 of FIG. 6, and a first external pad 141-b is formed at the other end. Of the two ends of the second pattern circuit unit 142, a second internal pad 142-a is formed at one end, and a second external pad 142-b is formed at the other end. That is, each pattern circuit section is composed of a line portion forming a pattern and pads provided at both ends of the line.

図３〜図６で説明したように、パターン回路部はマスター１００を用いて一括的に製作される。すなわち、パターンをなす線部分とパッド部分が一括的に製作できる。よって、コイルとパッドを別々に製作しなければならないという厄介さが解消される。   As described with reference to FIGS. 3 to 6, the pattern circuit unit is collectively manufactured using the master 100. That is, a line portion and a pad portion forming a pattern can be manufactured collectively. Therefore, the trouble that the coil and the pad must be manufactured separately is eliminated.

図６では、第１及び第２内部パッド１４１−ａ、１４２−ａは互いに並んで配置された状態を示したが、各パッド１４１−ａ、１４２−ａ、１４１−ｂ、１４２−ｂの位置及び形状は多様に変更できる。   In FIG. 6, the first and second internal pads 141-a, 142-a are arranged side by side, but the positions of the pads 141-a, 142-a, 141-b, 142-b are shown. The shape can be changed in various ways.

上述したようにマスター１００を用いてメッキ過程を行い、複数のパターン回路部を一括的に製作することができるので、ＲＦＩＤ回路パターンを容易に製作することができる。特に、マスター１００上で樹脂領域１１０と非樹脂領域１２０、１３０を精密に製作しておき、繰り返し使用することができるので、製造過程で不良パターンが発生する回数を減らすことができるうえ、経済的にＲＦＩＤ回路パターンを製作することができる。   As described above, the plating process is performed using the master 100, and a plurality of pattern circuit portions can be manufactured collectively, so that the RFID circuit pattern can be easily manufactured. In particular, since the resin region 110 and the non-resin regions 120 and 130 can be precisely manufactured on the master 100 and used repeatedly, the number of occurrences of defective patterns in the manufacturing process can be reduced and economical. An RFID circuit pattern can be manufactured.

このような方式で製造された回路パターンは、１３．５６ＭＨｚ用ＲＦＩＤタグに使用される回路パターンであってもよい。これにより製造される最終ＲＦＩＤタグは１３．５６ＭＨｚ用ＲＦＩＤタグになれる。   The circuit pattern manufactured by such a method may be a circuit pattern used for a 13.56 MHz RFID tag. As a result, the final RFID tag manufactured can be an RFID tag for 13.56 MHz.

図６のようにコアフィルム層２００上に複数のパターン回路部１４１、１４２が形成されると、各パターン回路部１４１、１４２の一端に設けられた第１外部パッド１４１−ｂと第２外部パッド１４２−ｂとを電気的に連結させるための工程が行われる。この場合、第１パターン回路部１４１をなす線とショートしないように、第１外部パッドと第２外部パッド１４１−ｂ、１４２−ｂとの間の領域に絶縁部を形成する。   When the plurality of pattern circuit portions 141 and 142 are formed on the core film layer 200 as shown in FIG. 6, the first external pads 141-b and the second external pads provided at one ends of the pattern circuit portions 141 and 142. The process for electrically connecting 142-b is performed. In this case, an insulating part is formed in a region between the first external pad and the second external pads 141-b and 142-b so as not to be short-circuited with the line forming the first pattern circuit part 141.

図７は絶縁部１５０が形成されたコアフィルム層２００の上側構成を示す。   FIG. 7 shows an upper configuration of the core film layer 200 on which the insulating portion 150 is formed.

絶縁部１５０は通常の絶縁物質からなってもよい。絶縁部１５０は、ステッカーの形に製作され、第１外部パッド１４１−ｂと第２外部パッド１４２−ｂとの間に付着する方式で形成できる。   The insulating part 150 may be made of a normal insulating material. The insulating part 150 is manufactured in the form of a sticker and can be formed by adhering between the first external pad 141-b and the second external pad 142-b.

又は、絶縁液を第１外部パッド１４１−ｂと第２外部パッド１４２−ｂとの間の空間に滴下した後、凝固させる方式で形成されてもよい。   Alternatively, the insulating liquid may be formed by dripping into the space between the first external pad 141-b and the second external pad 142-b and then solidifying.

一方、図７では絶縁部１５０が全体コアフィルム層２００の一部分にのみ形成されるものと示しているが、必ずしもこれに限定されるのではない。すなわち、コアフィルム層２００上で各外部パッド及び各内部パッドのみを除いた全面に、絶縁部を形成することができる。具体的には、各外部パッド及び各内部パッドの位置にマスクを被せた後、絶縁液でコートする方式、又は該当部分のみを除いた部分に接着剤を用いて絶縁部をボンディングする方式などを用いて、絶縁部を形成することができる。   On the other hand, FIG. 7 shows that the insulating part 150 is formed only on a part of the entire core film layer 200, but the present invention is not necessarily limited thereto. That is, an insulating part can be formed on the entire surface of the core film layer 200 except for each external pad and each internal pad. Specifically, after covering the position of each external pad and each internal pad with a mask, a method of coating with an insulating liquid, or a method of bonding an insulating portion using an adhesive to a portion excluding only the corresponding portion, etc. By using it, an insulating part can be formed.

図８及び図９は複数のパターン回路部同士１４１、１４２を電気的に連結させるジャンパー線を製造するための工程の一例を示す。   8 and 9 show an example of a process for manufacturing a jumper wire for electrically connecting a plurality of pattern circuit portions 141 and 142 to each other.

すなわち、図８のようにコアフィルム層２００の全面にマスク１６０を被せる。マスク１６０の一領域には露出部１６１が設けられる。図８に示すように、露出部１６１は第１外部パッド１４１−ｂ及び第２外部パッド１４２−ｂそれぞれの少なくとも一部分と、絶縁部１５０の少なくとも一部分を露出させる。図８のようにマスク１６０が被せられた状態で、導電性物質をコートする。導電性物質のコーティングはローラーを用いたプリント、スタンピングなどの工程で行われ得る。このような状態でマスク１６０を除去すると、図９に示すようにジャンパー線１７０が形成される。ジャンパー線１７０は伝導性ペーストからなってもよい。   That is, the mask 160 is put on the entire surface of the core film layer 200 as shown in FIG. An exposed portion 161 is provided in one area of the mask 160. As shown in FIG. 8, the exposed portion 161 exposes at least a portion of each of the first external pad 141-b and the second external pad 142-b and at least a portion of the insulating portion 150. In the state where the mask 160 is covered as shown in FIG. 8, the conductive material is coated. The conductive material may be coated by a process such as printing or stamping using a roller. When the mask 160 is removed in such a state, a jumper line 170 is formed as shown in FIG. The jumper wire 170 may be made of a conductive paste.

図９によれば、ジャンパー線１７０は、絶縁部１５０の上側を介して第１外部パッド１４１−ｂと第２外部パッド１４２−ｂとを電気的に連結する形に製作される。絶縁部１５０によって、第１外部パッド１４１−ｂを除いた第１パターン回路部１４１の他の部分と電気的に連結されることが防止される。   Referring to FIG. 9, the jumper wire 170 is manufactured to electrically connect the first external pad 141-b and the second external pad 142-b through the upper side of the insulating part 150. The insulating part 150 prevents electrical connection with other parts of the first pattern circuit part 141 except for the first external pads 141-b.

このようにジャンパー線１７０が製作されると、図１０に示すように、パターン回路部１４１、１４２の上にカバーレイ層３００を積層する。カバーレイ層２００は、ポリエステルフィルムやポリ塩化ビニルフィルムなどのプラスチック、又は紙材質からなってもよい。カバーレイ層３００はＲＦＩＤタグのインレイの外観に該当する部分であるので、カバーレイ層３００の素材はカードの後続の工程に対して問題を起こさない材質からなってもよい。また、カバーレイ層３００は、接着剤を用いて、パターン回路部１４１、１４２の上側でコアフィルム層２００と結合することができる。接着剤の種類は、上述した結合剤層２１０と同一であってもよく、これとは異なる接着剤を使用してもよい。   When the jumper wire 170 is thus manufactured, the coverlay layer 300 is laminated on the pattern circuit portions 141 and 142 as shown in FIG. The coverlay layer 200 may be made of a plastic such as a polyester film or a polyvinyl chloride film, or a paper material. Since the coverlay layer 300 is a portion corresponding to the appearance of the inlay of the RFID tag, the material of the coverlay layer 300 may be made of a material that does not cause a problem with respect to subsequent processes of the card. Further, the coverlay layer 300 can be bonded to the core film layer 200 on the upper side of the pattern circuit portions 141 and 142 using an adhesive. The type of adhesive may be the same as that of the binder layer 210 described above, or an adhesive different from this may be used.

カバーレイ層３００の一領域には露出部３１０が形成される。露出部３１０は下側の第１内部パッド１４１−ａ及び第２内部パッド１４２−ａそれぞれの少なくとも一部が露出するように、適切なサイズ及び位置に形成される。   An exposed portion 310 is formed in a region of the cover lay layer 300. The exposed portion 310 is formed in an appropriate size and position so that at least a part of each of the lower first inner pad 141-a and second inner pad 142-a is exposed.

次に、図１１に示すように露出部３１０にＲＦＩＤチップを配置する。ＲＦＩＤチップは露出部３１０を介して露出した第１内部パッド１４１−ａ及び第２内部パッド１４２−ａそれぞれと電気的に連結される。これにより、ＲＦＩＤタグ４００の製作が完了する。   Next, as shown in FIG. 11, the RFID chip is disposed on the exposed portion 310. The RFID chip is electrically connected to each of the first internal pads 141-a and the second internal pads 142-a exposed through the exposed portion 310. Thereby, the production of the RFID tag 400 is completed.

一方、ＲＦＩＤチップが配置された後、透明膜をコートするなどの表面処理を施してもよい。   On the other hand, after the RFID chip is disposed, a surface treatment such as coating a transparent film may be performed.

以上、本発明の好適な実施例について図示及び説明したが、本発明は、上述した特定の実施例に限定されるものではなく、請求の範囲で請求する本発明の要旨を逸脱することなく、当該発明の属する技術分野における通常の知識を有する者によって多様な変形実施が可能なのは勿論のことであり、それらの変形実施は本発明の技術的思想又は展望から個別的に理解されてはならない。   Although the preferred embodiments of the present invention have been illustrated and described above, the present invention is not limited to the specific embodiments described above, and does not depart from the gist of the present invention claimed in the claims. It goes without saying that various modifications can be made by those having ordinary knowledge in the technical field to which the invention pertains, and these modifications should not be individually understood from the technical idea or perspective of the present invention.

１００ マスター
１１０ 樹脂領域
１２０、１３０ 非樹脂領域
１４１ 第１パターン回路部
１４２ 第２パターン回路部





































100 Master 110 Resin area 120, 130 Non-resin area 141 First pattern circuit part 142 Second pattern circuit part





































Claims (10)

ＲＦＩＤタグ内蔵型インレイを製造するためのＲＦＩＤタグ内蔵型インレイの製造方法において、
樹脂で充填された樹脂領域、及び所定のパターンをなす非樹脂領域が形成されたマスターの表面をメッキし、前記非樹脂領域上に複数のパターン回路部を形成する段階と、
前記複数のパターン回路部が形成されたマスターの上側にコアフィルム層をボンディングする段階と、
前記コアフィルム層を分離して前記複数のパターン回路部を前記コアフィルム層側に転写させる段階と、
前記複数のパターン回路部の間の空間に絶縁部を形成する段階と、
前記絶縁部上で前記複数のパターン回路部同士を電気的に連結するジャンパー線を形成する段階と、を含んでなることを特徴とする、ＲＦＩＤタグ内蔵型インレイの製造方法。 In the manufacturing method of the RFID tag built-in type inlay for producing the RFID tag built-in type inlay,
Plating a resin area filled with resin and a surface of a master on which a non-resin area having a predetermined pattern is formed, and forming a plurality of pattern circuit portions on the non-resin area; and
Bonding a core film layer on the upper side of the master on which the plurality of pattern circuit portions are formed;
Separating the core film layer and transferring the plurality of pattern circuit portions to the core film layer side; and
Forming an insulating part in a space between the plurality of pattern circuit parts;
Forming a jumper wire for electrically connecting the plurality of pattern circuit portions to each other on the insulating portion. A method for manufacturing an RFID tag built-in inlay, comprising: 前記複数のパターン回路部は、
前記コアフィルム層の表面の縁部に沿って巻線された形の第１パターン回路部、及び前記コアフィルム層の表面から前記第１パターン回路部の内側に形成された第２パターン回路部を含み、
前記第１パターン回路部の両端にはそれぞれ第１外部パッド及び第１内部パッドが形成され、前記第２パターン回路部の両端にはそれぞれ第２外部パッド及び第２内部パッドが形成されたことを特徴とする、請求項１に記載のＲＦＩＤタグ内蔵型インレイの製造方法。 The plurality of pattern circuit units are:
A first pattern circuit portion wound along the edge of the surface of the core film layer, and a second pattern circuit portion formed inside the first pattern circuit portion from the surface of the core film layer. Including
A first external pad and a first internal pad are formed at both ends of the first pattern circuit unit, respectively, and a second external pad and a second internal pad are formed at both ends of the second pattern circuit unit, respectively. The manufacturing method of the RFID tag built-in type inlay according to claim 1, wherein 前記複数のパターン回路部の上側に、前記第１内部パッド及び第２内部パッドそれぞれの少なくとも一部を露出させるカバーレイ層を形成する段階と、
前記カバーレイ層の露出した部分に、前記第１内部パッド及び第２内部パッドそれぞれと電気的に連結されるＲＦＩＤチップを配置する段階と、をさらに含むことを特徴とする、請求項２に記載のＲＦＩＤタグ内蔵型インレイの製造方法。 Forming a coverlay layer exposing at least a part of each of the first internal pads and the second internal pads on the plurality of pattern circuit portions;
The method of claim 2, further comprising disposing an RFID chip electrically connected to each of the first inner pad and the second inner pad on the exposed portion of the coverlay layer. Manufacturing method of RFID tag built-in type inlay. 前記絶縁部は前記第１外部パッドと前記第２外部パッドとの間の空間に形成されることを特徴とする、請求項３に記載のＲＦＩＤタグ内蔵型インレイの製造方法。 4. The method of manufacturing an RFID tag built-in type inlay according to claim 3, wherein the insulating part is formed in a space between the first external pad and the second external pad. 前記ジャンパー線を形成する段階は、
前記第１外部パッド及び前記第２外部パッドそれぞれの少なくとも一部と、前記絶縁部の少なくとも一部を露出させるマスクを形成する段階と、
前記露出した部分に導電性物質をプリントして前記第１外部パッドと前記第２外部パッドとを互いに連結するジャンパー線を形成する段階と、
前記マスクを除去する段階と、を含んでなることを特徴とする、請求項４に記載のＲＦＩＤタグ内蔵型インレイの製造方法。 Forming the jumper wire comprises:
Forming a mask exposing at least a part of each of the first external pad and the second external pad and at least a part of the insulating part;
Forming a jumper line connecting the first external pad and the second external pad by printing a conductive material on the exposed portion;
The method of manufacturing an RFID tag built-in type inlay according to claim 4, comprising the step of removing the mask. 前記マスターの非樹脂領域を離型処理する段階をさらに含むことを特徴とする、請求項１に記載のＲＦＩＤタグ内蔵型インレイの製造方法。 The method for manufacturing an inlay with an RFID tag according to claim 1, further comprising a step of releasing a non-resin region of the master. 前記樹脂がテフロンであることを特徴とする、請求項１〜６のいずれか１項に記載のＲＦＩＤタグ内蔵型インレイの製造方法。 The method for producing an RFID tag built-in type inlay according to claim 1, wherein the resin is Teflon. 前記ＲＦＩＤタグ内蔵型インレイは１３．５６ＭＨｚ用コンビネーション型スマートカードに使用することを特徴とする、請求項１〜６のいずれか１項に記載のＲＦＩＤタグ内蔵型インレイの製造方法。 The RFID tag built-in type inlay according to any one of claims 1 to 6, wherein the RFID tag built-in type inlay is used for a 13.56 MHz combination smart card. コアフィルム層と、
前記コアフィルム層の表面の縁部に沿って巻線された形の第１パターン回路部と、
前記コアフィルム層の表面から前記第１パターン回路部の内側に形成された第２パターン回路部と、
前記第１パターン回路部の一端に形成される第１内部パッドと、
前記第１パターン回路部の他端に形成される第１外部パッドと、
前記第２パターン回路部の一端に形成される第２内部パッドと、
前記第２パターン回路部の他端に形成される第２外部パッドと、
前記第１外部パッドと前記第２外部パッドとの間の空間に形成された絶縁部と、
前記絶縁部上に形成され、前記第１外部パッドと前記第２外部パッドとを電気的に連結するジャンパー線と、を含んでなることを特徴とする、ＲＦＩＤタグ内蔵型インレイ。 A core film layer;
A first pattern circuit portion wound around an edge of the surface of the core film layer;
A second pattern circuit portion formed inside the first pattern circuit portion from the surface of the core film layer;
A first internal pad formed at one end of the first pattern circuit unit;
A first external pad formed at the other end of the first pattern circuit unit;
A second internal pad formed at one end of the second pattern circuit unit;
A second external pad formed at the other end of the second pattern circuit unit;
An insulating part formed in a space between the first external pad and the second external pad;
An inlay with a built-in RFID tag, comprising: a jumper wire formed on the insulating portion and electrically connecting the first external pad and the second external pad. コアフィルム層と、
前記コアフィルム層の表面の縁部に沿って巻線された形の第１パターン回路部と、
前記コアフィルム層の表面から前記第１パターン回路部の内側に形成された第２パターン回路部と、
前記第１パターン回路部の一端に形成される第１内部パッドと、
前記第１パターン回路部の他端に形成される第１外部パッドと、
前記第２パターン回路部の一端に形成される第２内部パッドと、
前記第２パターン回路部の他端に形成される第２外部パッドと、
前記第１外部パッドと前記第２外部パッドとの間の空間に形成された絶縁部と、
前記絶縁部上に形成され、前記第１外部パッドと前記第２外部パッドとを電気的に連結するジャンパー線と、
前記第１外部パッド及び前記第２パターン回路部が形成されている前記コアフィルム層の全面を覆いながら、前記第１内部パッド及び前記第２内部パッドそれぞれの少なくとも一部を露出させるカバーレイ層と、
前記露出した部分で前記第１内部パッド及び前記第２内部パッドそれぞれと電気的に連結されるＲＦＩＤチップと、を含んでなり、
前記ジャンパー線によって連結される前記第１パターン回路部及び前記第２パターン回路部は１３．５６ＭＨｚ用ＲＦＩＤタグに使用される回路パターンを構成することを特徴とする、カード。 A core film layer;
A first pattern circuit portion wound around an edge of the surface of the core film layer;
A second pattern circuit portion formed inside the first pattern circuit portion from the surface of the core film layer;
A first internal pad formed at one end of the first pattern circuit unit;
A first external pad formed at the other end of the first pattern circuit unit;
A second internal pad formed at one end of the second pattern circuit unit;
A second external pad formed at the other end of the second pattern circuit unit;
An insulating part formed in a space between the first external pad and the second external pad;
A jumper wire formed on the insulating portion and electrically connecting the first external pad and the second external pad;
A coverlay layer exposing at least a part of each of the first internal pad and the second internal pad while covering the entire surface of the core film layer on which the first external pad and the second pattern circuit portion are formed; ,
An RFID chip electrically connected to each of the first internal pad and the second internal pad at the exposed portion,
The card, wherein the first pattern circuit part and the second pattern circuit part connected by the jumper wire constitute a circuit pattern used for a 13.56 MHz RFID tag.
JP2012541943A 2009-12-03 2010-12-01 RFID tag built-in inlay, card including the same, and manufacturing method of RFID tag built-in inlay Expired - Fee Related JP5527674B2 (en)

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PCT/KR2010/008562 WO2011068359A2 (en) 2009-12-03 2010-12-01 Inlay having built-in rfid tag, card including same, and method for manufacturing inlay having built-in rfid tag

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