JP2013232687A5 - - Google Patents

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JP2013232687A5
JP2013232687A5 JP2013162185A JP2013162185A JP2013232687A5 JP 2013232687 A5 JP2013232687 A5 JP 2013232687A5 JP 2013162185 A JP2013162185 A JP 2013162185A JP 2013162185 A JP2013162185 A JP 2013162185A JP 2013232687 A5 JP2013232687 A5 JP 2013232687A5
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wiring board
printed wiring
board according
copper
layer
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JP2013162185A
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JP2013232687A (en
JP5946802B2 (en
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例示的な実施形態において、銅酸化物層はグレインを有し、調整の後にはこれらグレインは250ナノメータ以下のサイズを有する。別の実施形態において、銅酸化物層はグレインを有し、調整の後にはこれらグレインは200ナノメータ以下のサイズを有する。いくつかの実施形態において、銅酸化物層はグレインを有し、調整の後にはこれらグレインは実質的に不規則に配向している。 In an exemplary embodiment, the copper oxide layer has a grain, these grains after adjustments have a size equal to or less than 250 nanometers. In another embodiment, the copper oxide layer has grains , and after conditioning these grains have a size of 200 nanometers or less. In some embodiments, the copper oxide layer has a grain, these grains after adjustments are substantially randomly oriented.

表面は、表面を酸化剤に暴露することによって安定化される。例示の実施形態において、酸化剤は亜塩素酸ナトリウム、過酸化水素、過マンガン酸塩、過塩素酸塩、過硫酸塩、オゾン、又はこれら物質の混合物のうちのいずれか1つ以上から選択される。銅表面を安定化させるステップは、室温〜約80℃の範囲の温度で行うことができる。 The copper surface is stabilized by exposing the copper surface to an oxidizing agent. In an exemplary embodiment, the oxidizing agent is selected from one or more of sodium chlorite, hydrogen peroxide, permanganate, perchlorate, persulfate, ozone, or a mixture of these substances. The The step of stabilizing the copper surface can be performed at a temperature ranging from room temperature to about 80 ° C.

例示の実施形態において、銅酸化物層は非常に分散したグレイン構造を有し、調整の後にはグレインは200ナノメータ以下のサイズを有する。別の実施形態において、銅酸化物層はグレインを有し、調整の後にはこれらグレインは100ナノメータ以下のサイズを有する。いくつかの実施形態において、銅酸化物はグレインを有し、調整の後にはこれらグレインは実質的にランダムに配向している。 In the illustrated embodiment, the copper oxide layer has a highly dispersed grain structure, and after conditioning the grains have a size of 200 nanometers or less. In another embodiment, the copper oxide layer has a grain, these grains after adjustments have a size equal to or less than 100 nanometers. In some embodiments, the copper oxide has a grain, these grains after adjustments are oriented in substantially random.

図3Aは、ノジュール状グレイン及び長距離秩序の結晶構造を反映する一方向性グレイン成長を有する、従来の電解銅表面(すなわち、滑らかな銅表面、若しくは言い換えると粗化されていない銅表面)の典型的なモルフォロジーを示す、50,000倍の例示的SEM写真である。比較として、本発明の方法に従って処理された電解銅表面のモルフォロジーが、図3Bに示されている。非常に明確であるように、図3Bに示された、処理された銅表面上の安定化層は、グレインがより細かグレイン成長が一方向性ではな、均一性がより高いモルフォロジーを示している。対照的に、図3Cは既存の黒色酸化物表面を示し、この表面は非常に厚く、壊れやすい繊維状構造を示している。図3Dは、既存のマイクロエッチされた銅表面の例示的SEM写真であり、この表面は非常に不均一なマイクロな畝状モルフォロジーを示している。 FIG. 3A shows a conventional electrolytic copper surface (ie, a smooth copper surface or, in other words, an unroughened copper surface) with unidirectional grain growth reflecting a nodular grain and a long-range ordered crystal structure. 2 is an exemplary SEM photo at 50,000 times showing typical morphology. As a comparison, the morphology of the electrolytic copper surface treated according to the method of the present invention is shown in FIG. 3B. As is very clear, as shown in FIG. 3B, stabilizing layer on the treated copper surface, grain rather finer, grain growth rather than a unidirectional, higher morphological uniformity Show. In contrast, FIG. 3C shows an existing black oxide surface, which is very thick and shows a fragile fibrous structure. FIG. 3D is an exemplary SEM photo of an existing micro-etched copper surface, which shows a very non-uniform micro-cocoon morphology.

Claims (11)

少なくとも1つの銅層と、
少なくとも1つのポリマー材料層と、
前記銅層と前記ポリマー材料層との間の安定化層と、
を備え、
前記安定化層は、約250nm以下のサイズを有する複数のグレインを備え、前記グレインは実質的に不規則に配向しており、前記銅層の表面は、約0.14μmRa以下の粗さを呈する、プリント配線板。
At least one copper layer;
At least one polymer material layer;
A stabilizing layer between the copper layer and the polymeric material layer;
With
The stabilization layer includes a plurality of grains having a size of about 250 nm or less, the grains are substantially irregularly oriented, and the surface of the copper layer exhibits a roughness of about 0.14 μmRa or less. , Printed wiring board.
前記グレインは200nm以下のサイズを有することを特徴とする請求項に記載のプリント配線板。 The printed wiring board according to claim 1 , wherein the grains have a size of 200 nm or less. 前記グレインは100nm以下のサイズを有することを特徴とする請求項に記載のプリント配線板。 The printed wiring board according to claim 1 , wherein the grains have a size of 100 nm or less. 前記安定化層が500nm以下の厚さを有することを特徴とする請求項に記載のプリント配線板。 The printed wiring board according to claim 1 , wherein the stabilization layer has a thickness of 500 nm or less. 前記安定化層が300nm以下の厚さを有することを特徴とする請求項に記載のプリント配線板。 The printed wiring board according to claim 1 , wherein the stabilization layer has a thickness of 300 nm or less. 前記安定化層が約100nm〜200nmの厚さを有することを特徴とする請求項に記載のプリント配線板。 The printed wiring board according to claim 1 , wherein the stabilization layer has a thickness of about 100 nm to 200 nm. 前記グレインが、一方向性グレイン成長と実質的な均一性とを呈することを特徴とする請求項に記載のプリント配線板。 The printed wiring board according to claim 1 , wherein the grains exhibit unidirectional grain growth and substantial uniformity. 前記安定化層が酸化第一銅を備えることを特徴とする請求項に記載のプリント配線板。 The printed wiring board according to claim 1 , wherein the stabilization layer includes cuprous oxide. 前記銅層は、電解銅若しくは電気メッキ銅若しくは電着銅、無電解メッキ銅、及び圧延銅、又はこれらの組み合わせを備えることを特徴とする請求項に記載のプリント配線板。 The printed wiring board according to claim 1 , wherein the copper layer includes electrolytic copper, electroplated copper, electrodeposited copper, electroless plated copper, rolled copper, or a combination thereof. 前記ポリマー材料層は、誘電体樹脂を備えることを特徴とする請求項に記載のプリント配線板。 The printed wiring board according to claim 1 , wherein the polymer material layer includes a dielectric resin. 前記ポリマー材料層は、エポキシ又はフィラー材料を含むエポキシを備え、前記フィラー材料は、ガラス、シリカ及びそれらの混合物を備えることを特徴とする請求項に記載のプリント配線板。 The printed wiring board according to claim 1 , wherein the polymer material layer includes an epoxy or an epoxy including a filler material, and the filler material includes glass, silica, and a mixture thereof.
JP2013162185A 2013-08-05 2013-08-05 Printed wiring board Active JP5946802B2 (en)

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JP2013518360A Division JP5946827B2 (en) 2010-07-06 2010-07-06 Method for manufacturing a printed wiring board

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JP2015031989A Division JP6069736B2 (en) 2015-02-20 2015-02-20 Printed wiring board

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JP2013232687A JP2013232687A (en) 2013-11-14
JP2013232687A5 true JP2013232687A5 (en) 2015-04-16
JP5946802B2 JP5946802B2 (en) 2016-07-06

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US9345149B2 (en) 2010-07-06 2016-05-17 Esionic Corp. Methods of treating copper surfaces for enhancing adhesion to organic substrates for use in printed circuit boards

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JP3400514B2 (en) * 1994-01-14 2003-04-28 松下電工株式会社 Circuit board processing method
WO2009029871A1 (en) * 2007-08-31 2009-03-05 Zettacore, Inc. Methods of treating a surface to promote binding of molecule(s) of interest, coatings and devices formed therefrom

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