JP2013207059A - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP2013207059A JP2013207059A JP2012073760A JP2012073760A JP2013207059A JP 2013207059 A JP2013207059 A JP 2013207059A JP 2012073760 A JP2012073760 A JP 2012073760A JP 2012073760 A JP2012073760 A JP 2012073760A JP 2013207059 A JP2013207059 A JP 2013207059A
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Abstract
【解決手段】磁気シールド部材SIEは、第1シールド部材SIE1及び第2シールド部材SIE2を有している。第1シールド部材SIE1の第1対向領域FP1は、半導体チップSCの第1面に対向している。第2シールド部材SIE2の第2対向領域FP2は、半導体チップSCの第2面に対向している。樹脂層RL1は、一部が第1シールド部材SIE1に接しており、他の部分が第2シールド部材SIE2に接している。そして第1シールド部材SIE1と第2シールド部材SIE2は、樹脂層RL1を介して、又は直接、磁気的に接続している。第1シールド部材SIE1及び第2シールド部材SIE2は、平面視で、磁気記憶素子MRを覆っている。
【選択図】図2
Description
その他の課題と新規な特徴は、本発明書の記述及び添付図面から明らかになるであろう。
図1は、実施形態に係る半導体装置SDの構成を示す平面図である。図2(a)は、図1のA−A´断面図である。図2(b)は、図1のB−B´断面図である。半導体装置SDは、半導体チップSC及び磁気シールド部材SIEを有している。
図12は、変形例1に係る半導体装置SDの構成を示す断面図である。本図は、実施形態における図3に対応している。本変形例に係る半導体装置SDは、以下の点を除いて実施形態に係る半導体装置SDと同様の構成である。
図13は、変形例2に係る半導体装置SDの構成を示す断面図である。本図は、実施形態における図3に対応している。本変形例に係る半導体装置SDは、以下の点を除いて実施形態に係る半導体装置SDと同様の構成である。
図14は、変形例3に係る半導体装置SDの構成を示す断面図である。本図は、実施形態における図3に対応している。本変形例に係る半導体装置SDは、凸部CP1及び凸部CP2の製造方法を除いて、変形例2に係る半導体装置SDと同様の構成である。
図15は、変形例4に係る半導体装置SDの構成を示す断面図である。本図は、実施形態における図3に対応している。本変形例に係る半導体装置SDは、凸部CP1及び凸部CP2の製造方法を除いて、変形例2に係る半導体装置SDと同様の構成である。
図18及び図19は、変形例5に係る半導体装置SDの構成を示す断面図である。図18は実施形態における図2(a)に対応しており、図19は実施形態における図3に対応している。本変形例に係る半導体装置SDは、磁気シールド部材SIEの構成を除いて実施形態に係る半導体装置SDと同様の構成である。
図23は、変形例6に係る半導体装置SDの構成を示す断面図である。本図は、実施形態における図3に対応している。本変形例に係る半導体装置SDは、第1シールド部材SIE1を構成するシール材の構造を除いて、変形例5に係る半導体装置SDと同様の構成である。なお本図において、第1シールド部材SIE1の端部は図20と同様の構造となっているが、図19と同様の構造であっても良い。
図24は、変形例7に係る半導体装置SDの構成を示す断面図である。本変形例に係る半導体装置SDは、実施形態、又は変形例1〜6に係る半導体装置SDと同様の構成である。なお図24は、実施形態と同様の場合を示している。
図25は、変形例8に係る半導体装置SDの構成を示す平面図である。図26は、図25のB−B´断面図である。本変形例に係る半導体装置SDは、第2シールド部材SIE2のうち電極パッドPADの並びと直交する方向の幅(図25における上下方向の長さ)が半導体チップSCの幅よりも小さい点を除いて、実施形態1、又は変形例1〜7のいずれかと同様の構成である。
図27は、変形例9に係る半導体装置SDの構成を示す平面図である。図28(a)は、図27のA−A´断面図であり、図28(b)は図27のB−B´断面図である。本変形例に係る半導体装置SDは、第2シールド部材SIE2の端部のうち第1シールド部材SIE1に繋がっていない側の端部(図27及び図28(a)における左側の端部)が半導体チップSCと配線基板WPの間に位置している点を除いて、変形例8と同様の構成である。なお本図に示す例では、第2シールド部材SIE2の幅は、第1シールド部材SIE1の幅よりも狭くなっている。
図29は、変形例10に係る半導体装置SDの構成を示す断面図である。本図は、実施形態における図2(a)に対応している。本変形例に係る半導体装置SDは、第1シールド部材SIE1のうち互いに対向する2辺に、側面対向領域SPが形成されている点を除いて、実施形態、または変形例1〜8と同様である。
図30は、変形例11に係る半導体装置SDの構成を示す断面図である。本図は、実施形態における図3に対応している。本変形例に係る半導体装置SDは、以下の点を除いて、実施形態、又は変形例1〜10と同様の構成である。
図31は、変形例12に係る半導体装置SDの構成を示す断面図である。図32は、図31の要部を拡大した図である。図31は実施形態における図2(a)に対応しており、図32は、実施形態における図3に対応している。本変形例に係る半導体装置SDは、以下の点を除いて実施形態に係る半導体装置SDと同様の構成である。
図33は、変形例13に係る半導体装置SDの構成を示す断面図である。本図は、実施形態における図3に対応している。本変形例に係る半導体装置SDは、以下の点を除いて実施形態、変形例7、又は変形例8に係る半導体装置SDと同様の構成である。
図35は、変形例14に係る半導体装置SDの構成を示す断面図である。本図は、実施形態における図3に対応している。本変形例に係る半導体装置SDは、以下の点を除いて、変形例11に係る半導体装置SDと同様の構成を有している。
図36は、変形例15に係る半導体装置SDの構成を示す平面図である。図37は、図36のA−A´断面の要部を拡大した図である。図36は実施形態における図1に対応しており、図37は実施形態における図3に対応している。本変形例に係る半導体装置SDは、以下の点を除いて実施形態に係る半導体装置SDと同様の構成である。
図38は、変形例16に係る半導体装置SDの平面図である。図39は、図38に示した半導体装置SDの底面図であり、図40は、図38のA−A´断面図である。本実施形態に係る半導体装置SDは、以下の点を除いて実施形態に係る半導体装置SDと同様の構成である。なお図39においては、接続端子OT2及びハンダボールSBの図示を省略している。
図41は、変形例17に係る半導体装置SDの構成を示す平面図である。図42は、図41のA−A´断面図である。本変形例に係る半導体装置SDは、第1シールド部材SIE1も2つに分割されている点を除いて、変形例16に係る半導体装置SDと同様の構成である。
図43は、変形例18に係る半導体装置SDの構成を示す平面図である。図44は、図43に示した半導体装置SDの底面図であり、図45は、図43のA−A´断面図である。本実施形態に係る半導体装置SDは、以下の点を除いて変形例16に係る半導体装置SDと同様の構成である。
図48は、変形例19に係る半導体装置SDの構成を示す平面図である。図49は、図48のA−A´断面図である。本変形例に係る半導体装置SDは、以下の点を除いて、変形例18に係る半導体装置SDと同様の構成である。
図50は、変形例20に係る半導体装置SDの構成を示す平面図である。図51は、図50のA−A´断面図である。本変形例に係る半導体装置SDは、以下の点を除いて、変形例19に係る半導体装置SDと同様の構成である。
図52(a)及び図52(b)は、変形例21に係る半導体装置SDの構成を示す断面図である。図52(a)は、実施形態における図2(a)に対応しており、図52(b)は実施形態における図2(b)に対応している。図53は、図52(a)の要部を拡大した図であり、実施形態における図3に対応している。本実施形態に係る半導体装置SDは、以下の点を除いて実施形態に係る半導体装置SDと同様の構成である。
図55は、変形例22に係る装置の機能ブロック図である。本変形例に係る装置は、携帯通信端末であり、制御用半導体チップCONを有している。携帯通信端末は、例えば、携帯電話端末、携帯型のパーソナルコンピュータ、又は携帯型のゲーム機器である。制御用半導体チップCONは、回路基板PCBを介して、各種のデバイスに接続している。これらデバイスとしては、例えば、通信デバイス(Connectivities)、RFIC、HPA、RFPMIC、ADC、DAC、パワー制御デバイス(Power management)、SIMカード、表示デバイス(LCD)、撮像素子(Camera)、メモリーカード、キーパッド、USB端子、RAM(半導体装置SD)、及びNVM(半導体装置SD)に接続している。そして情報、例えば撮像素子で撮像された画像や通信記録は、半導体装置SDの磁気記憶素子MRに記憶される。これらの記憶の制御は、制御用半導体チップCONによって行われている。
図56は、変形例23に係る装置の機能ブロック図である。本変形例に係る装置は車両であり、制御用半導体チップCONを有している。制御用半導体チップCONは、回路基板PCBを介して、車両内の各種電気装置に接続している。これら電気装置としては、例えば音声認識装置、スピーカ、HDD、DVD、チューナーモジュール(Tuner Module)、GPSシステム、交通情報通信装置(例えばVICS(登録商標)システム)、CAN(controller area network)、車載マルチメディアネットワーク、コンピュータネットワーク、ブルートゥースシステム、メモリーカードシステム、USB端子、モニタ、撮像素子(Camera)、MRAM(半導体装置SD)、ナビゲーションシステム、及び電源ICに接続している。そして情報、例えばナビゲーションシステムで使用される情報や撮像素子で撮像された画像は、半導体装置SDの磁気記憶素子MRに記憶される。
BW ボンディングワイヤ
CON 制御用半導体チップ
CR1 コア層
CP1 凸部
CP2 凸部
DB1 ダイシングブレード
DB2 ダイシングブレード
DP ダイパッド
EH1 凹部
EP 端面
FP1 第1対向領域
FP2 第2対向領域
HO 凹部
IC 電源
IL リード
INC1 配線
INC2 配線
MF1 軟磁性膜
MO 封止樹脂
MR 磁気記憶素子
MR1 読出線
MR2 磁気固定層
MR3 ビット線
MR3a ビット線
MR3b ビット線
MR4 磁気フリー層
MR6 トンネルバリア層
OT1 接続端子
OT2 接続端子
PAD 電極パッド
PCB 回路基板
PR1 レジストパターン
PR2 レジストパターン
RL1 樹脂層
RL2 樹脂層
RL3 樹脂層
RL4 樹脂層
RL5 樹脂層
PS 凸部
PST 導体ポスト
SB ハンダボール
SC 半導体チップ
SD 半導体装置
SIE 磁気シールド部材
SIE1 第1シールド部材
SIE2 第2シールド部材
SIE3 第3シールド部材
SL1 保護絶縁膜
SL2 保護絶縁膜
SM 軟磁性層
SP 側面対向領域
VA1 ビア
WP 配線基板
Claims (15)
- 磁気記憶型素子を有する半導体チップと、
前記半導体チップのうち前記磁気記憶型素子が設けられている領域を覆う磁気シールド部材と、
を備え、
前記磁気シールド部材は、
前記半導体チップの第1面に対向する第1の対向領域を有する第1シールド部材と、
前記半導体チップの前記第1面とは逆側の面である第2面に対向する第2の対向領域を有する第2シールド部材と、
一部が前記第1シールド部材に接していて他の部分が前記第2シールド部材に接している樹脂層と、
を備える半導体装置。 - 請求項1に記載の半導体装置において、
前記第1シールド部材は、前記半導体チップの側面に対向する側面対向領域を有しており、
前記樹脂層は、前記側面対向領域に接している半導体装置。 - 請求項2に記載の半導体装置において、
前記樹脂層は、前記側面対向領域の端部に接しており、
前記側面対向領域の前記端部は、前記第2シールド部材の前記第2の対向領域に対して傾斜している傾斜面を有している半導体装置。 - 請求項2に記載の半導体装置において、
前記樹脂層は、前記側面対向領域の端部に接しており、
前記側面対向領域の前記端部は、前記第1シールド部材の厚み方向において前記半導体チップに近い側に凸部を有している半導体装置。 - 請求項2に記載の半導体装置において、
前記樹脂層は、前記側面対向領域の端に接しており、
前記側面対向領域の前記端は、前記半導体チップの前記第2面よりも前記第1面側に位置している半導体装置。 - 請求項2に記載の半導体装置において、
前記第1シールド部材は、樹脂層と軟磁性体層を繰り返し積層させた積層材である半導体装置。 - 請求項2に記載の半導体装置において、
前記半導体チップを封止する封止樹脂を備え、
前記樹脂層は、前記封止樹脂であり、
前記第2シールド部材の端部の少なくとも一部は、前記封止樹脂の外面のうち前記半導体チップの前記側面に対向する面から露出しており、
前記第1シールド部材は、前記封止樹脂の前記外面のうち前記半導体チップの前記第1面に対向する面、及び前記側面に対向する面に沿って設けられている半導体装置。 - 請求項1に記載の半導体装置において、
前記樹脂層内に位置しており、前記半導体チップの側面に対向している第3シールド部材を備える半導体装置。 - 請求項8に記載の半導体装置において、
前記第1の対向領域に平行な面で見た場合の前記第3シールド部材の幅は、前記第1シールド部材の厚さよりも大きい半導体装置。 - 請求項8に記載の半導体装置において、
前記第1の対向領域に平行な面で見た場合、前記第3シールド部材の幅は、前記第3シールド部材の厚さよりも大きい半導体装置。 - 請求項8に記載の半導体装置において、
前記第3シールド部材は、前記第1シールド部材及び前記第2シールド部材よりも飽和磁束密度が高い材料により形成されている半導体装置。 - 請求項1に記載の半導体装置において、
前記樹脂層は、軟磁性材料を有するフィラーを有している半導体装置。 - 請求項1に記載の半導体装置において、
前記半導体チップを封止する封止樹脂を備え、
前記封止樹脂及び前記樹脂層は、フィラーを含有しており、
前記樹脂層の前記フィラーの平均粒子径は、前記封止樹脂の前記フィラーの平均粒子径よりも小さい半導体装置。 - 請求項1に記載の半導体装置において、
前記半導体チップの能動面に設けられた複数の電極パッドを備え、
前記第1シールド部材及び前記第2シールド部材のうち前記能動面に対向する部材は、平面視で前記複数の電極パッドと重なっていない半導体装置。 - 請求項14に記載の半導体装置において、
一端が前記複数の電極パッドに接続する複数のボンディングワイヤと、
前記複数のボンディングワイヤの他端に接続する外部接続端子と、
を備える半導体装置。
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US11011474B2 (en) | 2019-01-11 | 2021-05-18 | Kabushiki Kaisha Toshiba | Electromagnetic wave attenuator and electronic device |
US11049818B2 (en) | 2019-01-28 | 2021-06-29 | Kabushiki Kaisha Toshiba | Electromagnetic wave attenuator and electronic device |
WO2020241068A1 (ja) * | 2019-05-30 | 2020-12-03 | ソニーセミコンダクタソリューションズ株式会社 | 半導体パッケージ、および、半導体パッケージの製造方法 |
WO2024018798A1 (ja) * | 2022-07-22 | 2024-01-25 | ローム株式会社 | 半導体装置 |
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US9172028B2 (en) | 2015-10-27 |
JP5829562B2 (ja) | 2015-12-09 |
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