JP2012256822A - 記憶装置及び半導体装置 - Google Patents
記憶装置及び半導体装置 Download PDFInfo
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- JP2012256822A JP2012256822A JP2011195554A JP2011195554A JP2012256822A JP 2012256822 A JP2012256822 A JP 2012256822A JP 2011195554 A JP2011195554 A JP 2011195554A JP 2011195554 A JP2011195554 A JP 2011195554A JP 2012256822 A JP2012256822 A JP 2012256822A
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- transistor
- oxide semiconductor
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- oxide
- insulating film
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- GZCRRIHWUXGPOV-UHFFFAOYSA-N terbium atom Chemical compound [Tb] GZCRRIHWUXGPOV-UHFFFAOYSA-N 0.000 description 1
- FRNOGLGSGLTDKL-UHFFFAOYSA-N thulium atom Chemical compound [Tm] FRNOGLGSGLTDKL-UHFFFAOYSA-N 0.000 description 1
- 229910001930 tungsten oxide Inorganic materials 0.000 description 1
- 238000001771 vacuum deposition Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
- NAWDYIZEMPQZHO-UHFFFAOYSA-N ytterbium Chemical compound [Yb] NAWDYIZEMPQZHO-UHFFFAOYSA-N 0.000 description 1
- OYQCBJZGELKKPM-UHFFFAOYSA-N zinc indium(3+) oxygen(2-) Chemical compound [O-2].[Zn+2].[O-2].[In+3] OYQCBJZGELKKPM-UHFFFAOYSA-N 0.000 description 1
- 229910052726 zirconium Inorganic materials 0.000 description 1
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- G11C5/10—Arrangements for interconnecting storage elements electrically, e.g. by wiring for interconnecting capacitors
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
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- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/408—Address circuits
- G11C11/4085—Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge
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- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4094—Bit-line management or control circuits
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- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
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- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4097—Bit-line organisation, e.g. bit-line layout, folded bit lines
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- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/18—Bit line organisation; Bit line lay-out
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Abstract
【解決手段】複数のビット線を幾つかのグループに分割し、複数のワード線も幾つかのグループに分割する。そして、一のグループに属するビット線に接続されたメモリセルには、一のグループに属するワード線が接続されるようにする。さらに、複数のビット線は、複数のビット線駆動回路102a,102b,102cによってグループごとにその駆動が制御されるようにする。加えて、複数のビット線駆動回路102a,102b,102cと、ワード線駆動回路101とを含めた駆動回路上に、セルアレイ103a,103b,103cを形成する。駆動回路とセルアレイ103a,103b,103cが重なるように三次元化することで、ビット線駆動回路が複数設けられていても、記憶装置の占有面積を小さくすることができる。
【選択図】図1
Description
まず、本発明の一態様の記憶装置について図1〜図5を参照して説明する。
図1は、本発明の一態様の記憶装置の構造例を示す概念図である。図1に示す記憶装置は、半導体基板100を用いて設けられたワード線駆動回路101と、第1ビット線駆動回路102aと、第2ビット線駆動回路102bと、第3ビット線駆動回路102cと、第1ビット線駆動回路102a上に重畳して設けられる第1セルアレイ103aと、第2ビット線駆動回路102b上に重畳して設けられる第2セルアレイ103bと、第3ビット線駆動回路102c上に重畳して設けられる第3セルアレイ103cと、を有する。なお、図1においては、ワード線駆動回路101及び第1ビット線駆動回路102a乃至第3ビット線駆動回路102cと、第1セルアレイ103a乃至第3セルアレイ103cとを離間して図示しているが、当該記憶装置において両者は重なって設けられている。
図2は、セルアレイ(第1セルアレイ103a〜第3セルアレイ103c)の構成例を示す回路図である。図2に示す第1セルアレイ103aは、複数の第1ワード線104aと、複数の第1ビット線105aと、マトリクス状に配設された複数の第1メモリセル106aと、を有する。なお、複数の第1メモリセル106aのそれぞれは、ゲート電極が複数の第1ワード線104aのいずれか一に電気的に接続され、ソース電極及びドレイン電極の一方が複数の第1ビット線105aのいずれか一に電気的に接続されるトランジスタ107aと、一方の電極が当該トランジスタ107aのソース電極及びドレイン電極の他方に電気的に接続され、他方の電極が容量線に電気的に接続された容量素子108aと、を有する。また、複数の第1ワード線104aのそれぞれは、ワード線駆動回路101によって電位が制御される。すなわち、ワード線駆動回路101は、第1メモリセル106aが有するトランジスタのスイッチングを制御する回路である。また、複数の第1ビット線105aのそれぞれは、第1ビット線駆動回路102aによって電位の制御及び電位の判別が行われる。具体的には、特定の第1メモリセル106aに対してデータの書き込みを行う際には、当該特定の第1メモリセル106aに電気的に接続された第1ビット線105aの電位が第1ビット線駆動回路102aによって当該データに対応した電位となるように制御され、当該特定の第1メモリセル106aからデータの読み出しを行う際には、当該特定の第1メモリセル106aに電気的に接続された第1ビット線105aの電位の判別することで当該データの読み出しが行われる。すなわち、第1ビット線駆動回路102aは、第1メモリセル106aへのデータの書き込み及び当該データの読み出しを行う回路である。
図3は、駆動回路(ワード線駆動回路101及び第1ビット線駆動回路102a乃至第3ビット線駆動回路102c等)の構成例を示すブロック図である。なお、図3中においては、機能ごとに分類された回路を互いに独立したブロックとして示すが、実際の回路は機能ごとに完全に切り分けることが難しく、一つの回路が複数の機能に係わることもあり得る。
次いで、読み出し回路の具体的な構成例について説明する。
図5は、記憶装置の構造の一例を示す断面図である。図5に示す記憶装置は、上部にメモリセル670が複数設けられたセルアレイ201を有し、下部に駆動回路210を有する。上部のセルアレイ201は、酸化物半導体を用いたトランジスタ662を有し、下部の駆動回路210は、多結晶または単結晶のシリコンまたはゲルマニウムなどの半導体を用いたトランジスタ660を有する。
本明細書で開示される記憶装置は、ビット線の数を増やすことで、メモリセルの数が増大しても、一のビット線に接続されるメモリセルの数を小さく抑えることができる。よって、ビット線の有する寄生容量と寄生抵抗を小さくすることができるため、容量素子の面積縮小化により各デジタル値どうしの電荷量の差が小さくなっても、上記ビット線を介して読み出されるデータの正確性を高め、エラー発生率を低く抑えることができる。
図6及び図7に、図5に示したトランジスタ662とは異なるトランジスタの構成例を示す。
次に、図5に示したトランジスタ662の作製方法の一例について、図8を参照して説明する。
以下では、上述した記憶装置の利用例について図9、10を参照して説明する。
酸化物半導体に限らず、実際に測定される絶縁ゲート型トランジスタの電界効果移動度は、さまざまな理由によって本来の移動度よりも低くなる。移動度を低下させる要因としては半導体内部の欠陥や半導体と絶縁膜との界面の欠陥があるが、Levinsonモデルを用いると、半導体内部に欠陥がないと仮定した場合の電界効果移動度を理論的に導き出せる。そこで、本実施の形態では、半導体内部に欠陥がない理想的な酸化物半導体の電界効果移動度を理論的に導き出すとともに、このような酸化物半導体を用いて微細なトランジスタを作製した場合の特性の計算結果を示す。
In、Sn、Znを主成分とする酸化物半導体をチャネル形成領域とするトランジスタは、該酸化物半導体を形成する際に基板を加熱して成膜すること、或いは酸化物半導体膜を形成した後に熱処理を行うことで良好な特性を得ることができる。なお、主成分とは組成比で5atomic%以上含まれる元素をいう。そこで、本実施の形態では、酸化物半導体膜の成膜後に基板を意図的に加熱することで、トランジスタの電界効果移動度を向上させた場合について、図20乃至図26を用いて説明する。
101 ワード線駆動回路
102a 第1ビット線駆動回路
102b 第2ビット線駆動回路
102c 第3ビット線駆動回路
103a 第1セルアレイ
103b 第2セルアレイ
103c 第3セルアレイ
104a 第1ワード線
104b 第2ワード線
104c 第3ワード線
105a 第1ビット線
105b 第2ビット線
105c 第3ビット線
106a 第1メモリセル
106b 第2メモリセル
106c 第3メモリセル
107a トランジスタ
107b トランジスタ
107c トランジスタ
108a 容量素子
108b 容量素子
108c 容量素子
110 制御回路
120 駆動回路
201 セルアレイ
210 駆動回路
260 トランジスタ
262 オペアンプ
312 トランジスタ
314 容量素子
322 トランジスタ
324 容量素子
332 トランジスタ
334 容量素子
342 トランジスタ
344 容量素子
352 トランジスタ
354 容量素子
362 トランジスタ
364 容量素子
401 CPU
402 メインメモリ
403 クロックコントローラ
404 キャッシュコントローラ
405 シリアルインターフェース
406 I/Oポート
407 端子
408 インターフェース
409 キャッシュメモリ
550 RFタグ
551 アンテナ回路
552 集積回路
553 電源回路
554 復調回路
555 変調回路
556 レギュレータ
557 演算回路
558 記憶装置
559 昇圧回路
600 基板
606 素子分離絶縁層
608 ゲート絶縁膜
610 ゲート電極
616 チャネル形成領域
620 不純物領域
624 金属化合物領域
626 電極
628 絶縁膜
630a ソース電極またはドレイン電極
630b ソース電極またはドレイン電極
636a 電極
636b 電極
636c 電極
640 絶縁膜
642a ソース電極またはドレイン電極
642b ソース電極またはドレイン電極
642c 電極
643a 酸化物導電膜
643b 酸化物導電膜
644 酸化物半導体膜
646 ゲート絶縁膜
648a ゲート電極
648b 導電膜
650 絶縁膜
652 絶縁膜
654a 電極
654b 電極
656 配線
659 導電膜
660 トランジスタ
662 トランジスタ
664 容量素子
670 メモリセル
810 書き込み回路
811 読み出し回路
812 デコーダ
813 レベルシフタ
814 セレクタ
815 デコーダ
816 レベルシフタ
817 バッファ
1101 基板
1102 下地絶縁層
1104 保護絶縁膜
1106a 高抵抗領域
1106b 低抵抗領域
1106 酸化物半導体膜
1108 ゲート絶縁膜
1110 ゲート電極
1112 側壁絶縁膜
1114 一対の電極
1116 層間絶縁膜
1118 配線
1600 基板
1602 下地絶縁層
1606 酸化物半導体膜
1608 ゲート絶縁膜
1610 ゲート電極
1614 一対の電極
1616 層間絶縁膜
1618 配線
1620 保護膜
7031 筐体
7032 筐体
7033 表示部
7034 表示部
7035 マイクロホン
7036 スピーカー
7037 操作キー
7038 スタイラス
7041 筐体
7042 表示部
7043 音声入力部
7044 音声出力部
7045 操作キー
7046 受光部
7051 筐体
7052 表示部
7053 操作キー
8101 下地絶縁層
8102 埋め込み絶縁層
8103a 半導体領域
8103b 半導体領域
8103c 半導体領域
8104 ゲート絶縁膜
8105 ゲート
8106a 側壁絶縁物
8106b 側壁絶縁物
8107 絶縁物
8108a ソース
8108b ドレイン
Claims (5)
- 複数の第1ビット線を駆動する第1ビット線駆動回路と、
複数の第2ビット線を駆動する第2ビット線駆動回路と、
複数の第1ワード線及び複数の第2ワード線を駆動するワード線駆動回路と、
複数の第1メモリセルを有する第1セルアレイ及び複数の第2メモリセルを有する第2セルアレイと、を有し、
前記第1メモリセルは、ゲート電極が前記複数の第1ワード線のいずれか一に電気的に接続され、ソース電極及びドレイン電極の一方が前記複数の第1ビット線のいずれか一に電気的に接続された第1トランジスタと、一方の電極が前記第1トランジスタのソース電極及びドレイン電極の他方に電気的に接続された第1容量素子と、を有し、
前記第2メモリセルは、ゲート電極が前記複数の第2ワード線のいずれか一に電気的に接続され、ソース電極及びドレイン電極の一方が前記複数の第2ビット線のいずれか一に電気的に接続された第2トランジスタと、一方の電極が前記第2トランジスタのソース電極及びドレイン電極の他方に電気的に接続された第2容量素子と、を有し、
前記第1セルアレイは、前記第1ビット線駆動回路上に重畳して設けられ、
前記第2セルアレイは、前記第2ビット線駆動回路上に重畳して設けられることを特徴とする記憶装置。 - 請求項1において、
前記第1トランジスタ及び前記第2トランジスタが酸化物半導体を活性層に用いたトランジスタであることを特徴とする記憶装置。 - 請求項1又は請求項2において、
前記第1ビット線駆動回路及び前記第2ビット線駆動回路並びに前記ワード線駆動回路が多結晶又は単結晶のシリコン又はゲルマニウムを活性層に用いたトランジスタを有することを特徴とする記憶装置。 - 請求項1乃至請求項3のいずれか一項において、
前記第1セルアレイ及び前記第2セルアレイが、複数のセルアレイ層を有することを特徴とする記憶装置。 - 請求項1乃至請求項4のいずれか一項に記載の記憶装置を有する半導体装置。
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