JP2012231182A - 微細配線パッケージ - Google Patents
微細配線パッケージ Download PDFInfo
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- JP2012231182A JP2012231182A JP2012179383A JP2012179383A JP2012231182A JP 2012231182 A JP2012231182 A JP 2012231182A JP 2012179383 A JP2012179383 A JP 2012179383A JP 2012179383 A JP2012179383 A JP 2012179383A JP 2012231182 A JP2012231182 A JP 2012231182A
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- 239000011347 resin Substances 0.000 claims abstract description 108
- 229920005989 resin Polymers 0.000 claims abstract description 108
- 238000007789 sealing Methods 0.000 claims abstract description 49
- 239000004020 conductor Substances 0.000 claims abstract description 20
- 230000003014 reinforcing effect Effects 0.000 claims description 18
- 230000002787 reinforcement Effects 0.000 abstract description 3
- 238000009413 insulation Methods 0.000 abstract 2
- 239000010410 layer Substances 0.000 description 97
- 239000012790 adhesive layer Substances 0.000 description 23
- 238000004519 manufacturing process Methods 0.000 description 18
- 239000002184 metal Substances 0.000 description 11
- 238000000034 method Methods 0.000 description 10
- 239000000853 adhesive Substances 0.000 description 9
- 230000001070 adhesive effect Effects 0.000 description 9
- 230000017525 heat dissipation Effects 0.000 description 8
- 239000000463 material Substances 0.000 description 5
- 229910000679 solder Inorganic materials 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 4
- 238000007796 conventional method Methods 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- 238000004377 microelectronic Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 1
- 238000012937 correction Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000009281 ultraviolet germicidal irradiation Methods 0.000 description 1
- 230000003313 weakening effect Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/19—Manufacturing methods of high density interconnect preforms
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/19—Manufacturing methods of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/241—Disposition
- H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/24137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/241—Disposition
- H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/24153—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate
- H01L2224/24195—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being a discrete passive component
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73267—Layer and HDI connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
- H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
- H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
【解決手段】一方の面に搭載した、各々複数の端子を有する高さの異なる複数の電子部品(12、14、16)と、電子部品の端子の表面を所定の平面上に揃えるように、これらの電子部品を、電極端子形成面が露出し且つ電子部品の側面の一部を覆うように、封止する封止樹脂(22)と、電子部品及び封止樹脂の表面上に形成した、電子部品の端子に電気的に接続する導体層(44)と、電子部品の電極端子形成面及び封止樹脂上に形成された配線層を覆う絶縁樹脂層(24)と、封止樹脂と絶縁樹脂層との間に形成した補強板(46)とを含む。
【選択図】図6
Description
図3(a)〜図3(d)、図4(a)〜図4(e)及び図5(a)及び(b)は、本発明の微細配線パッケージの製造方法の実施形態を示す。
12、14、16 電子部品
12a、14a、16a 端子
20 第1の接着剤層
22 封止樹脂
24 絶縁樹脂層
26 ビア
28 配線層
30 ソルダレジスト
32 外部端子
40 第2の支持体
42 第2の接着剤層
44 導体補強層
46 補強板
48 キャビティ構造を持つ補強板
50 導電性樹脂
Claims (7)
- 一方の面に搭載した、各々複数の端子を有する高さの異なる複数の電子部品と、
該電子部品の端子の表面を所定の平面上に揃えるように、前記複数の電子部品を、電極端子形成面が露出するように、且つ該電子部品の側面の一部を覆うように、封止する封止樹脂と、
前記封止樹脂の表面上に形成した導体層と、
前記電子部品の電極端子形成面及び封止樹脂上に形成された前記導体層を覆うように設けた絶縁樹脂層と、
前記絶縁樹脂層上に形成した、前記電子部品の端子に電気的に接続される配線層と、を積層して成ることを特徴とする微細配線パッケージ。 - 前記配線層の一部はビアを介して前記導体層に接続されていることを特徴とする請求項1に記載の微細配線パッケージ。
- 前記封止樹脂の表面の高さは、前記電子部品の電極端子形成面と同じ又はやや低い程度であることを特徴とする請求項1又は2に記載の微細配線パッケージ。
- 前記導体層は、前記電子部品の電極端子の表面と略同一面であることを特徴とする請求項1〜3のいずれか1項に記載の微細配線パッケージ。
- 一方の面に搭載した、各々複数の端子を有する高さの異なる複数の電子部品(12、14、16)と、
該電子部品の端子の表面を所定の平面上に揃えるように、前記複数の電子部品を、電極端子形成面が露出するように、且つ該電子部品の側面の一部を覆うように、封止する封止樹脂(22)と、
前記封止樹脂上に、前記複数の電子部品の電極端子形成面を露出し、且つ該電子部品の側面の一部を覆うように設けた補強板としての導電性樹脂(50)と、
前記電子部品の電極端子形成面及び前記封止樹脂上に形成された前記導電性樹脂を覆うように設けた絶縁樹脂層(24)と、
前記電子部品及び前記封止樹脂の表面上に形成した、前記電子部品の端子に電気的に接続する配線層(28)と、を含むことを特徴とする微細配線パッケージ。 - 前記配線層(28)の一部はビアを介して前記導電性樹脂(50)に接続されていることを特徴とする請求項5に記載の微細配線パッケージ。
- 前記導電性樹脂(50)は、前記電子部品の電極端子(12a、14a、16a)の表面と略同一面であることを特徴とする請求項5又は6に記載の微細配線パッケージ。
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JP2012179383A JP5484532B2 (ja) | 2012-08-13 | 2012-08-13 | 微細配線パッケージ |
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JP2012179383A JP5484532B2 (ja) | 2012-08-13 | 2012-08-13 | 微細配線パッケージ |
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JP2008328488A Division JP5147678B2 (ja) | 2008-12-24 | 2008-12-24 | 微細配線パッケージの製造方法 |
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JP2012231182A true JP2012231182A (ja) | 2012-11-22 |
JP5484532B2 JP5484532B2 (ja) | 2014-05-07 |
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2016056068A1 (ja) * | 2014-10-07 | 2016-04-14 | 株式会社メイコー | 部品内蔵基板の製造方法及びこの製造方法を用いて製造した部品内蔵基板 |
WO2018030262A1 (ja) * | 2016-08-09 | 2018-02-15 | 株式会社村田製作所 | モジュール部品の製造方法 |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH077134A (ja) * | 1993-02-08 | 1995-01-10 | General Electric Co <Ge> | 集積回路モジュール |
JPH08162604A (ja) * | 1994-12-01 | 1996-06-21 | Toyota Motor Corp | マルチチップモジュールの製造方法 |
JPH09321408A (ja) * | 1996-05-31 | 1997-12-12 | Nec Corp | 電子回路基板の高密度実装構造 |
JPH11214849A (ja) * | 1998-01-29 | 1999-08-06 | Yamaichi Electronics Co Ltd | 多層配線基板およびその製造方法 |
JP2002280744A (ja) * | 2001-03-21 | 2002-09-27 | Matsushita Electric Ind Co Ltd | 積層型電子部品実装済部品の製造方法、電子部品実装済完成品の製造方法、及び電子部品実装済完成品 |
JP2004014629A (ja) * | 2002-06-04 | 2004-01-15 | Sony Corp | 半導体装置及びその製造方法 |
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- 2012-08-13 JP JP2012179383A patent/JP5484532B2/ja active Active
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH077134A (ja) * | 1993-02-08 | 1995-01-10 | General Electric Co <Ge> | 集積回路モジュール |
JPH08162604A (ja) * | 1994-12-01 | 1996-06-21 | Toyota Motor Corp | マルチチップモジュールの製造方法 |
JPH09321408A (ja) * | 1996-05-31 | 1997-12-12 | Nec Corp | 電子回路基板の高密度実装構造 |
JPH11214849A (ja) * | 1998-01-29 | 1999-08-06 | Yamaichi Electronics Co Ltd | 多層配線基板およびその製造方法 |
JP2002280744A (ja) * | 2001-03-21 | 2002-09-27 | Matsushita Electric Ind Co Ltd | 積層型電子部品実装済部品の製造方法、電子部品実装済完成品の製造方法、及び電子部品実装済完成品 |
JP2004014629A (ja) * | 2002-06-04 | 2004-01-15 | Sony Corp | 半導体装置及びその製造方法 |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2016056068A1 (ja) * | 2014-10-07 | 2016-04-14 | 株式会社メイコー | 部品内蔵基板の製造方法及びこの製造方法を用いて製造した部品内蔵基板 |
WO2018030262A1 (ja) * | 2016-08-09 | 2018-02-15 | 株式会社村田製作所 | モジュール部品の製造方法 |
US10818518B2 (en) | 2016-08-09 | 2020-10-27 | Murata Manufacturing Co., Ltd. | Method for manufacturing module component |
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