JP2012169524A - 半導体装置及びその試験方法 - Google Patents
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Abstract
【解決手段】半導体装置は、ゲート電極5を有する半導体チップ1と、半導体チップ1の表面に設けられ、当該表面にかかる応力を検出する応力検出用素子7とを備える。そして、半導体装置は、応力検出用素子7で検出された応力に基づいて、ゲート電極5に印加される制御信号を制御する。また、平面視において半導体チップ1の中央部にかかる応力を検出する応力検出用素子7が、第1応力検出用素子7−1として設けられ、平面視において半導体チップ1の外周部にかかる応力を検出する応力検出用素子7が、第2応力検出用素子7−2として設けられることが好ましい。
【選択図】図1
Description
まず、本発明の実施の形態1に係る半導体装置について説明する前に、これと関連する半導体装置(以下、「関連半導体装置」と呼ぶ)について説明する。この関連半導体装置は、低損失で、かつ大電流を制御する代表的なIGBT(Insulated Gate Bipolar Transistor)を含む半導体チップを備えているものとする。このIGBTは、半導体チップとなるウェハの表面側にゲート電極及びエミッタ電極を有し、裏面側にコレクタ電極を有する。
図5は、本発明の実施の形態2に係る半導体装置が備える半導体チップの構成を示す上面図である。なお、本実施の形態に係る半導体装置において、実施の形態1に係る半導体装置の構成要素と類似するものについては同じ符号を付すものとし、以下、実施の形態1と大きく異なる部分を中心に説明する。
実施の形態1では、応力検出用素子7は、半導体チップ1の通電動作中において、半導体チップ1にかかる応力を検出することにより、半導体チップ1の電気的特性のばらつき等を抑制することを目的とした。
図7は、ピエゾ抵抗素子が有する抵抗の種類と、その抵抗係数との関係を示す図である。この図において、抵抗係数が大きければ大きいほど、感度が高いことを意味する。
図12は、本発明の実施の形態5に係る半導体装置が備える半導体チップの構成を示す上面図である。なお、本実施の形態に係る半導体装置において、実施の形態1に係る半導体装置の構成要素と類似するものについては同じ符号を付すものとし、以下、実施の形態1と大きく異なる部分を中心に説明する。
図13は、本発明の実施の形態6に係る半導体装置の一部の構成を示す断面図である。図に示されるように、当該半導体装置は、半導体チップ1の裏面とはんだ61を介して接合された金属製(ここでは銅製)のベース板62と、ベース板62との間に半導体チップ1を内包する樹脂モールド63とを備えている。なお、ここでは、便宜上、半導体チップ1と接続されるワイヤーボンドは省略している。
本発明の実施の形態7では、半導体装置の試験方法に関するものである。ここでは、まず、実施の形態2に係る半導体チップ1に類似する、本実施の形態に係る半導体チップ1が形成されたウェハを準備する。
Claims (12)
- 制御電極を有する半導体チップと、
前記半導体チップの表面に設けられ、当該表面にかかる応力を検出する応力検出用素子と
を備え、
前記応力検出用素子で検出された応力に基づいて、前記制御電極に印加される制御信号を制御する、半導体装置。 - 請求項1に記載の半導体装置であって、
平面視において前記半導体チップの中央部にかかる応力を検出する前記応力検出用素子が、第1応力検出用素子として設けられ、平面視において前記半導体チップの外周部にかかる応力を検出する前記応力検出用素子が、第2応力検出用素子として設けられ、
前記第1応力検出用素子で検出された応力と、前記第2応力検出用素子で検出された応力との差分が所定の閾値を超えた場合に、前記制御信号を制御する、半導体装置。 - 請求項2に記載の半導体装置であって、
前記半導体チップは平面視矩形状を有し、
前記第2応力検出用素子は前記半導体チップのコーナ部に設けられている、半導体装置。 - 請求項1乃至請求項3のいずれかに記載の半導体装置であって、
前記応力検出用素子は、前記半導体チップの通電が行われる前後のそれぞれにおいて前記応力を検出し、
前記通電の前後のそれぞれにおいて前記応力検出用素子で検出された応力同士の差分が所定の閾値を超えた場合に、前記制御信号を制御する、半導体装置。 - 請求項1乃至請求項4のいずれかに記載の半導体装置であって、
前記応力検出用素子は、前記半導体チップの表面にかかる応力に応じて抵抗が変化するピエゾ抵抗素子を含む、半導体装置。 - 請求項5に記載の半導体装置であって、
前記ピエゾ抵抗素子は、N型不純物が注入された拡散層を有する、半導体装置。 - 請求項5に記載の半導体装置であって、
前記ピエゾ抵抗素子は、P型不純物が注入されたポリシリコン層を有する、半導体装置。 - 請求項1に記載の半導体装置であって、
前記半導体チップは、
平面視において、前記半導体チップの中央部を分担する中央部制御電極と、当該中央部半導体チップの外周部を分担する外周部制御電極とを含み、
前記中央部制御電極に対応する前記応力検出用素子が、第1応力検出用素子として設けられ、
前記外周部制御電極に対応する前記応力検出用素子が、第2応力検出用素子として設けられる、半導体装置。 - 請求項1乃至請求項8のいずれかに記載の半導体装置であって、
前記半導体チップの裏面とはんだを介して接合された金属製のベース板と、
前記ベース板との間に前記半導体チップを内包する樹脂モールドと
をさらに備える、半導体装置。 - 請求項1乃至請求項9のいずれかに記載の半導体装置であって、
前記半導体チップは、IGBTまたはパワーMOSFETを含む、半導体装置。 - 請求項1乃至請求項9のいずれかに記載の半導体装置であって、
前記半導体チップは、ダイオードを含む、半導体装置。 - (a)請求項2に記載の半導体チップが形成されたウェハを準備する工程を備え、
前記第2応力検出用素子は前記ウェハのダイシングラインの表面に形成され、
(b)前記工程(a)後、半導体チップを試験する工程と、
(c)前記工程(b)後、前記ウェハを前記ダイシングラインにおいてダイシングする工程と
をさらに備える、半導体装置の試験方法。
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
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JP2011030756A JP5649478B2 (ja) | 2011-02-16 | 2011-02-16 | 半導体装置及びその試験方法 |
US13/272,512 US8884383B2 (en) | 2011-02-16 | 2011-10-13 | Semiconductor device and method of testing the same |
CN201110359048.8A CN102646721B (zh) | 2011-02-16 | 2011-11-14 | 半导体装置及其试验方法 |
DE102011087149.7A DE102011087149B4 (de) | 2011-02-16 | 2011-11-25 | Halbleitervorrichtung und Verfahren, um sie zu testen |
KR1020120010589A KR101465042B1 (ko) | 2011-02-16 | 2012-02-02 | 반도체장치 및 그 시험방법 |
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JP2014183248A (ja) * | 2013-03-21 | 2014-09-29 | Toshiba Corp | 半導体装置および歪監視装置 |
WO2014156273A1 (ja) * | 2013-03-27 | 2014-10-02 | 株式会社日立製作所 | 力学量測定装置およびその製造方法 |
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CN113491059A (zh) * | 2019-03-01 | 2021-10-08 | 三菱电机株式会社 | 半导体装置及半导体装置的诊断方法 |
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US8884383B2 (en) | 2014-11-11 |
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DE102011087149B4 (de) | 2016-02-04 |
JP5649478B2 (ja) | 2015-01-07 |
CN102646721B (zh) | 2015-12-09 |
US20120205756A1 (en) | 2012-08-16 |
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DE102011087149A1 (de) | 2012-08-16 |
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