JP2012147006A - 能動領域ボンディングの両立性のある高電流構造体 - Google Patents
能動領域ボンディングの両立性のある高電流構造体 Download PDFInfo
- Publication number
- JP2012147006A JP2012147006A JP2012058964A JP2012058964A JP2012147006A JP 2012147006 A JP2012147006 A JP 2012147006A JP 2012058964 A JP2012058964 A JP 2012058964A JP 2012058964 A JP2012058964 A JP 2012058964A JP 2012147006 A JP2012147006 A JP 2012147006A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- forming
- interconnect layer
- metal layer
- layers
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
- H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/5329—Insulating materials
- H01L23/53295—Stacked insulating layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
- H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
- H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
- H01L2224/02165—Reinforcing structures
- H01L2224/02166—Collar structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05075—Plural internal layers
- H01L2224/0508—Plural internal layers being stacked
- H01L2224/05082—Two-layer arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05099—Material
- H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
- H01L2224/05166—Titanium [Ti] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/05624—Aluminium [Al] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05647—Copper [Cu] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/85399—Material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01014—Silicon [Si]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01022—Titanium [Ti]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01047—Silver [Ag]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/0105—Tin [Sn]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01074—Tungsten [W]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
- H01L2924/01327—Intermediate phases, i.e. intermetallics compounds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/049—Nitrides composed of metals from groups of the periodic table
- H01L2924/0494—4th Group
- H01L2924/04941—TiN
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/049—Nitrides composed of metals from groups of the periodic table
- H01L2924/0504—14th Group
- H01L2924/05042—Si3N4
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Geometry (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Wire Bonding (AREA)
Abstract
【解決手段】一実施例において、集積回路は基板と、最上部導電層と、1つ以上の中間導電層と、絶縁材料から成る各層と、各デバイスとを具備する。最上部導電層は少なくとも1個のボンディング・パッド及び比較的硬質の材料から成る副層を有する。1つ以上の中間導電層は最上部導電層及び基板の間に形成する。絶縁材料から成る各層は各導電層を分離する。更に、絶縁材料から成る各層のうちの1つの層は比較的硬質で、最上部導電層及びこの最上部導電層に最も近接した中間導電層の間に位置する。各デバイスは集積回路に形成する。また、最上部導電層に最も近接した少なくとも中間導電層は、ボンディング・パッド下方の各選択デバイスの機能的相互接続部に対して適合する。
【選択図】図1
Description
102、302 N型MOS
104、304 N-DMOS
106,306 NPNデバイス
108、312 第1の金属層M1
110、318 第2の金属層M2
112、328 第3の金属層M3
114、334 ボール・ボンディング・ワイヤ
116、118、310、316 ビア
120、126、320 副層
122 分離用酸化物層
124、322 ギャップ
130、330 ボンディング・パッド
132、332 パッシベーション層
301 基板
308 第1の絶縁層
314 第2の絶縁層
324 第3の絶縁層
326 硬質層
Claims (4)
- 基板に少なくとも1つの能動デバイスを形成する工程、
最上部相互接続層と前記基板との間に1つ以上の中間相互接続層を形成する工程、
前記1つ以上の中間相互接続層と前記最上部相互接続層とを分離する1つ以上の絶縁材料層を形成する工程であって、前記最上部相互接続層と前記最上部相互接続層に最も近接した前記中間相互接続層との間に位置した前記絶縁材料層のうちの1つは、クラック発生に対する耐力を有する厚さを有して形成される前記工程、
前記最上部相互接続層上にパッシベーション層を形成する工程、及び
前記パッシベーション層をパターニングして前記最上部相互接続層の表面の一部を露出する工程であって、前記最上部相互接続層の前記露出した表面はボンディング・パッドを形成し、前記少なくとも1つの能動デバイスは前記ボンディング・パッドの直下に位置される前記工程を含むことを特徴とする半導体構造の形成方法。 - 前記最上部相互接続層を形成する工程は、
前記最上部相互接続層の副層を形成する工程を含み、この副層の材料は前記最上部相互接続層の残部に比べて相対的に硬く、前記相対的に硬い材料の副層は、前記最上部相互接続層と前記最上部相互接続層に最も近接した前記中間相互接続層との間に位置した前記絶縁材料層に応力を分配するように構成されることを特徴とする請求項1に記載の半導体構造の形成方法。 - 前記最上部相互接続層に最も近接した前記中間相互接続層の一部から導体を形成する工程であって、前記導体の少なくとも一部は前記ボンディング・パッドの直下に形成される前記工程、及び
前記導体にギャップをパターニングする工程を更に含むことを特徴とする請求項2に記載の半導体構造の形成方法。 - 前記導体を通る電流の流れの方向に延びるように前記ギャップをパターニングする工程を更に含むことを特徴とする請求項3に記載の半導体構造の形成方法。
Applications Claiming Priority (6)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US49688103P | 2003-08-21 | 2003-08-21 | |
US60/496,881 | 2003-08-21 | ||
US50753903P | 2003-09-30 | 2003-09-30 | |
US60/507,539 | 2003-09-30 | ||
US10/698,184 US7005369B2 (en) | 2003-08-21 | 2003-10-31 | Active area bonding compatible high current structures |
US10/698,184 | 2003-10-31 |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2006523849A Division JP5270836B2 (ja) | 2003-08-21 | 2004-07-20 | 能動領域ボンディングの両立性のある高電流構造体 |
Publications (1)
Publication Number | Publication Date |
---|---|
JP2012147006A true JP2012147006A (ja) | 2012-08-02 |
Family
ID=34198983
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2006523849A Expired - Fee Related JP5270836B2 (ja) | 2003-08-21 | 2004-07-20 | 能動領域ボンディングの両立性のある高電流構造体 |
JP2012058964A Pending JP2012147006A (ja) | 2003-08-21 | 2012-03-15 | 能動領域ボンディングの両立性のある高電流構造体 |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2006523849A Expired - Fee Related JP5270836B2 (ja) | 2003-08-21 | 2004-07-20 | 能動領域ボンディングの両立性のある高電流構造体 |
Country Status (7)
Country | Link |
---|---|
US (4) | US7005369B2 (ja) |
EP (2) | EP1661179B1 (ja) |
JP (2) | JP5270836B2 (ja) |
KR (1) | KR100973399B1 (ja) |
CN (4) | CN105261607A (ja) |
TW (1) | TWI293186B (ja) |
WO (1) | WO2005024943A1 (ja) |
Families Citing this family (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8274160B2 (en) | 2003-08-21 | 2012-09-25 | Intersil Americas Inc. | Active area bonding compatible high current structures |
JP2007005539A (ja) * | 2005-06-23 | 2007-01-11 | Seiko Epson Corp | 半導体装置 |
JP4605378B2 (ja) | 2005-07-13 | 2011-01-05 | セイコーエプソン株式会社 | 半導体装置 |
JP2007042817A (ja) * | 2005-08-02 | 2007-02-15 | Sanyo Electric Co Ltd | 絶縁ゲート型半導体装置およびその製造方法 |
US7701070B1 (en) | 2006-12-04 | 2010-04-20 | Xilinx, Inc. | Integrated circuit and method of implementing a contact pad in an integrated circuit |
US7888257B2 (en) * | 2007-10-10 | 2011-02-15 | Agere Systems Inc. | Integrated circuit package including wire bonds |
EP2195837A1 (en) * | 2007-10-31 | 2010-06-16 | Agere Systems Inc. | Bond pad support structure for semiconductor device |
CN101996993A (zh) * | 2009-08-13 | 2011-03-30 | 中芯国际集成电路制造(上海)有限公司 | 利用单一金属化的焊盘下的器件 |
US20110156260A1 (en) * | 2009-12-28 | 2011-06-30 | Yu-Hua Huang | Pad structure and integrated circuit chip with such pad structure |
JP6074984B2 (ja) * | 2012-09-28 | 2017-02-08 | ローム株式会社 | 半導体装置 |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05102327A (ja) * | 1991-10-08 | 1993-04-23 | Nec Corp | 樹脂封止型半導体装置 |
JPH1064945A (ja) * | 1996-08-20 | 1998-03-06 | Seiko Epson Corp | 半導体装置およびその製造方法 |
JP2001308100A (ja) * | 2000-03-17 | 2001-11-02 | Internatl Business Mach Corp <Ibm> | 半導体チップおよびその形成方法 |
JP2002164437A (ja) * | 2000-07-27 | 2002-06-07 | Texas Instruments Inc | ボンディングおよび電流配分を分散したパワー集積回路および方法 |
JP2002198374A (ja) * | 2000-10-16 | 2002-07-12 | Sharp Corp | 半導体装置およびその製造方法 |
JP2004014609A (ja) * | 2002-06-04 | 2004-01-15 | Sharp Corp | 半導体装置及びその製造方法 |
Family Cites Families (30)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4695868A (en) * | 1985-12-13 | 1987-09-22 | Rca Corporation | Patterned metallization for integrated circuits |
US5133054A (en) * | 1987-10-20 | 1992-07-21 | Sharp Kabushiki Kaisha | Data transmission apparatus for autonomously and selectively transmitting data to a plurality of transfer path |
US4893151A (en) * | 1987-11-26 | 1990-01-09 | Kabushiki Kaisha Toshiba | Image developing apparatus |
JP2988075B2 (ja) * | 1991-10-19 | 1999-12-06 | 日本電気株式会社 | 半導体装置 |
JPH06100589A (ja) * | 1992-09-22 | 1994-04-12 | Mochida Pharmaceut Co Ltd | 新規な蛋白性生理活性物質およびそのdna |
US5385868A (en) * | 1994-07-05 | 1995-01-31 | Taiwan Semiconductor Manufacturing Company, Ltd. | Upward plug process for metal via holes |
US6300688B1 (en) * | 1994-12-07 | 2001-10-09 | Quicklogic Corporation | Bond pad having vias usable with antifuse process technology |
JP3660799B2 (ja) * | 1997-09-08 | 2005-06-15 | 株式会社ルネサステクノロジ | 半導体集積回路装置の製造方法 |
US5986343A (en) * | 1998-05-04 | 1999-11-16 | Lucent Technologies Inc. | Bond pad design for integrated circuits |
US6552438B2 (en) * | 1998-06-24 | 2003-04-22 | Samsung Electronics Co. | Integrated circuit bonding pads including conductive layers with arrays of unaligned spaced apart insulating islands therein and methods of forming same |
US6232662B1 (en) * | 1998-07-14 | 2001-05-15 | Texas Instruments Incorporated | System and method for bonding over active integrated circuits |
US6261944B1 (en) * | 1998-11-24 | 2001-07-17 | Vantis Corporation | Method for forming a semiconductor device having high reliability passivation overlying a multi-level interconnect |
TW445616B (en) * | 1998-12-04 | 2001-07-11 | Koninkl Philips Electronics Nv | An integrated circuit device |
US6965165B2 (en) * | 1998-12-21 | 2005-11-15 | Mou-Shiung Lin | Top layers of metal for high performance IC's |
US8021976B2 (en) * | 2002-10-15 | 2011-09-20 | Megica Corporation | Method of wire bonding over active area of a semiconductor circuit |
US6534870B1 (en) * | 1999-06-15 | 2003-03-18 | Kabushiki Kaisha Toshiba | Apparatus and method for manufacturing a semiconductor device |
US6133054A (en) * | 1999-08-02 | 2000-10-17 | Motorola, Inc. | Method and apparatus for testing an integrated circuit |
US6198170B1 (en) * | 1999-12-16 | 2001-03-06 | Conexant Systems, Inc. | Bonding pad and support structure and method for their fabrication |
US6795675B2 (en) * | 2001-02-26 | 2004-09-21 | Canon Kabushiki Kaisha | Developing-carrying member, and developing apparatus and image forming apparatus including the member |
FR2824954A1 (fr) * | 2001-05-18 | 2002-11-22 | St Microelectronics Sa | Plot de connexion d'un circuit integre |
EP1266980B1 (en) * | 2001-06-11 | 2005-11-02 | Mitsubishi Materials Corporation | Surface-coated carbide alloy tool |
JP2003068751A (ja) | 2001-08-27 | 2003-03-07 | Nec Yamagata Ltd | 半導体装置及びその製造方法 |
JP2003068740A (ja) * | 2001-08-30 | 2003-03-07 | Hitachi Ltd | 半導体集積回路装置およびその製造方法 |
JP2003142485A (ja) * | 2001-11-01 | 2003-05-16 | Mitsubishi Electric Corp | 半導体装置及びその製造方法 |
US6921979B2 (en) * | 2002-03-13 | 2005-07-26 | Freescale Semiconductor, Inc. | Semiconductor device having a bond pad and method therefor |
US7288845B2 (en) * | 2002-10-15 | 2007-10-30 | Marvell Semiconductor, Inc. | Fabrication of wire bond pads over underlying active devices, passive devices and/or dielectric layers in integrated circuits |
US6963138B2 (en) * | 2003-02-03 | 2005-11-08 | Lsi Logic Corporation | Dielectric stack |
JP4357862B2 (ja) * | 2003-04-09 | 2009-11-04 | シャープ株式会社 | 半導体装置 |
US6927156B2 (en) * | 2003-06-18 | 2005-08-09 | Intel Corporation | Apparatus and method extending flip-chip pad structures for wirebonding on low-k dielectric silicon |
US7459790B2 (en) * | 2003-10-15 | 2008-12-02 | Megica Corporation | Post passivation interconnection schemes on top of the IC chips |
-
2003
- 2003-10-31 US US10/698,184 patent/US7005369B2/en not_active Expired - Lifetime
-
2004
- 2004-07-15 TW TW093121110A patent/TWI293186B/zh not_active IP Right Cessation
- 2004-07-20 EP EP04778684.3A patent/EP1661179B1/en not_active Expired - Fee Related
- 2004-07-20 KR KR1020067003594A patent/KR100973399B1/ko not_active IP Right Cessation
- 2004-07-20 JP JP2006523849A patent/JP5270836B2/ja not_active Expired - Fee Related
- 2004-07-20 WO PCT/US2004/023307 patent/WO2005024943A1/en active Application Filing
- 2004-07-20 EP EP10178443.7A patent/EP2264757B1/en not_active Expired - Fee Related
- 2004-08-20 CN CN201510633289.5A patent/CN105261607A/zh active Pending
- 2004-08-20 CN CN2010105863288A patent/CN102097366A/zh active Pending
- 2004-08-20 CN CNA2004100959467A patent/CN1645606A/zh active Pending
- 2004-08-20 CN CN201410260705.7A patent/CN104112706A/zh active Pending
-
2005
- 2005-12-19 US US11/305,987 patent/US7224074B2/en not_active Expired - Fee Related
-
2007
- 2007-04-19 US US11/737,392 patent/US7795130B2/en not_active Expired - Fee Related
- 2007-04-19 US US11/737,395 patent/US20070187837A1/en not_active Abandoned
-
2012
- 2012-03-15 JP JP2012058964A patent/JP2012147006A/ja active Pending
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05102327A (ja) * | 1991-10-08 | 1993-04-23 | Nec Corp | 樹脂封止型半導体装置 |
JPH1064945A (ja) * | 1996-08-20 | 1998-03-06 | Seiko Epson Corp | 半導体装置およびその製造方法 |
JP2001308100A (ja) * | 2000-03-17 | 2001-11-02 | Internatl Business Mach Corp <Ibm> | 半導体チップおよびその形成方法 |
JP2002164437A (ja) * | 2000-07-27 | 2002-06-07 | Texas Instruments Inc | ボンディングおよび電流配分を分散したパワー集積回路および方法 |
JP2002198374A (ja) * | 2000-10-16 | 2002-07-12 | Sharp Corp | 半導体装置およびその製造方法 |
JP2004014609A (ja) * | 2002-06-04 | 2004-01-15 | Sharp Corp | 半導体装置及びその製造方法 |
Also Published As
Publication number | Publication date |
---|---|
TW200511403A (en) | 2005-03-16 |
CN104112706A (zh) | 2014-10-22 |
US20070184645A1 (en) | 2007-08-09 |
JP2007503113A (ja) | 2007-02-15 |
US7224074B2 (en) | 2007-05-29 |
EP2264757A2 (en) | 2010-12-22 |
US20060099823A1 (en) | 2006-05-11 |
EP1661179B1 (en) | 2017-09-06 |
EP2264757A3 (en) | 2011-06-29 |
US7795130B2 (en) | 2010-09-14 |
CN1645606A (zh) | 2005-07-27 |
EP2264757B1 (en) | 2017-03-29 |
KR20060087516A (ko) | 2006-08-02 |
US20050042853A1 (en) | 2005-02-24 |
CN102097366A (zh) | 2011-06-15 |
JP5270836B2 (ja) | 2013-08-21 |
CN105261607A (zh) | 2016-01-20 |
KR100973399B1 (ko) | 2010-07-30 |
TWI293186B (en) | 2008-02-01 |
EP1661179A1 (en) | 2006-05-31 |
WO2005024943A1 (en) | 2005-03-17 |
US7005369B2 (en) | 2006-02-28 |
US20070187837A1 (en) | 2007-08-16 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP2012147006A (ja) | 能動領域ボンディングの両立性のある高電流構造体 | |
US6803302B2 (en) | Method for forming a semiconductor device having a mechanically robust pad interface | |
US8212357B2 (en) | Combination via and pad structure for improved solder bump electromigration characteristics | |
EP0913863A2 (en) | Method of manufacturing semiconductor device with copper wiring film | |
JP2005520342A (ja) | ワイヤボンドパッドを有する半導体装置とその製作方法 | |
EP1399966B1 (en) | Power pads for application of high current per bond pad in silicon technology | |
KR20000057792A (ko) | 반도체 집적 회로의 제조 방법 | |
JP5627835B2 (ja) | 半導体装置および半導体装置の製造方法 | |
US20200035620A1 (en) | Advanced crack stop structure | |
US8946912B2 (en) | Active area bonding compatible high current structures | |
US20020068385A1 (en) | Method for forming anchored bond pads in semiconductor devices and devices formed | |
EP1119046A2 (en) | Wire bonding technique and architecture suitable for copper metallization in semiconductor structures | |
JP2010147051A (ja) | 半導体集積回路装置および半導体集積回路装置の製造方法 | |
JP2013239756A (ja) | 半導体装置 | |
JP2004063995A (ja) | 半導体装置及び半導体装置の製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20120403 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20131031 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20131105 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20140129 |
|
A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 20140617 |