JP2012049480A - 半導体装置およびその検査方法、並びに電気機器 - Google Patents
半導体装置およびその検査方法、並びに電気機器 Download PDFInfo
- Publication number
- JP2012049480A JP2012049480A JP2010192898A JP2010192898A JP2012049480A JP 2012049480 A JP2012049480 A JP 2012049480A JP 2010192898 A JP2010192898 A JP 2010192898A JP 2010192898 A JP2010192898 A JP 2010192898A JP 2012049480 A JP2012049480 A JP 2012049480A
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- substrate
- semiconductor device
- electrodes
- insulating substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 157
- 238000007689 inspection Methods 0.000 title claims abstract description 9
- 238000000034 method Methods 0.000 title claims description 13
- 239000000758 substrate Substances 0.000 claims abstract description 303
- 239000000919 ceramic Substances 0.000 claims abstract description 62
- 239000011347 resin Substances 0.000 claims description 29
- 229920005989 resin Polymers 0.000 claims description 29
- 238000007789 sealing Methods 0.000 claims description 27
- 238000009413 insulation Methods 0.000 abstract 2
- 239000004020 conductor Substances 0.000 description 37
- 238000012986 modification Methods 0.000 description 26
- 230000004048 modification Effects 0.000 description 26
- 238000000926 separation method Methods 0.000 description 22
- 238000010586 diagram Methods 0.000 description 14
- 230000006866 deterioration Effects 0.000 description 11
- 239000000047 product Substances 0.000 description 9
- 239000011521 glass Substances 0.000 description 6
- 230000002950 deficient Effects 0.000 description 5
- 238000012790 confirmation Methods 0.000 description 4
- 238000005520 cutting process Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 230000000149 penetrating effect Effects 0.000 description 4
- 230000035515 penetration Effects 0.000 description 4
- 238000007747 plating Methods 0.000 description 4
- 238000005286 illumination Methods 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000004973 liquid crystal related substance Substances 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 230000032683 aging Effects 0.000 description 1
- 230000008602 contraction Effects 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 239000012467 final product Substances 0.000 description 1
- 238000010304 firing Methods 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 239000000523 sample Substances 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 238000011179 visual inspection Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01047—Silver [Ag]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01074—Tungsten [W]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12041—LED
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
- H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Led Device Packages (AREA)
Abstract
【解決手段】セラミック基板101上に発光素子Edを実装してなる半導体発光装置100において、セラミック基板101の表面に形成した表面側カソード電極103および表面側アノード電極104と、セラミック基板101の裏面に形成した裏面カソード電極および裏面アノード電極とを有し、裏面カソード電極を、2つの側面電極105の各々毎に分離された平面パターンを持つ構造とし、裏面アノード電極を、2つの側面電極106の各々毎に分離された平面パターンを持つ構造とした。
【選択図】図1
Description
図1および図2は本発明の実施形態1に係る半導体装置を説明する図であり、図1(a)は、全体構成を示す斜視図、図1(b)は一部断面図、図1(c)は図1(b)に対応する平面図である。また、図2(a)は、この実施形態1の半導体装置の裏面電極の平面パターンを示している。
(実施形態2)
図2(b)〜図2(d)は、本発明の実施形態2およびその変形例による半導体発光装置を説明する図であり、図2(b)は、本実施形態2による半導体発光装置を説明する図である。
(実施形態2の変形例1)
図2(c)は、本実施形態2の変形例1による半導体発光装置20を説明する図である。
(実施形態2の変形例2)
図2(d)は、本実施形態2の変形例2を説明する図である。
(実施形態3)
図4は本発明の実施形態3による半導体発光装置を説明する図であり、図4(a)は、平面図、図4(b)は底面図、図4(c)は側面図である。
(実施形態3の変形例1)
図5は本発明の実施形態3の変形例1による半導体発光装置を説明する図であり、図5(a)は平面図、図5(b)は底面図、図5(c)は側面図である。
(実施形態3の変形例2)
図6は本発明の実施形態3の変形例2による半導体発光装置を説明する図であり、図6(a)は平面図、図6(b)は底面図、図6(c)は側面図である。
15a、15b、25a、25b、35a、35b 裏面個別カソード電極
15c、16c、35c、36c 切り込み部
16a、16b、26a、26b、36a、36b 裏面個別アノード電極
101、111、121、131 セラミック基板
101a、121a、131a 封止樹脂
103、113、135、230、330 表面カソード電極
104、114、136、240、340 表面アノード電極
105、106 側面電極
105a、105b 裏面個別カソード電極
106a、106b 裏面個別アノード電極
108 メッキ層
115、116、123、124、133 スルーホール貫通導体
115a、115b 裏面個別カソード電極
116a、116b 裏面個別アノード電極
123a、133a 表面カソード電極本体部
123b、133b 表面カソード電極分離部
124a、134a 表面アノード電極本体部
124b、134b 表面アノード電極分離部
125、150 裏面カソード電極
126、160 裏面アノード電極
127 リフレクタ部材
B ベース基板
Rc チップ領域
SLh 横方向のスクライブ溝
SLv 縦方向のスクライブ溝
TH スルーホール
W ボンディングワイヤ
Claims (14)
- 絶縁性基板上に半導体素子を実装してなる半導体装置であって、
該絶縁性基板の表面側に形成され、該半導体素子の素子電極と接続される基板表面電極と、
該絶縁性基板の裏面側に形成され、該基板表面電極と電気的に接続される基板裏面電極と、
該絶縁性基板の厚み方向に沿ってその表面および裏面の一方側から他方側に延び、該基板表面電極と該基板裏面電極とを電気的に接続する複数の接続電極とを備え、
該基板表面電極あるいは該基板裏面電極は、
該複数の接続電極の各々毎に分離された平面パターンを持つよう形成されている、半導体装置。 - 請求項1に記載の半導体装置において、
前記基板表面電極は、前記複数の接続電極の全てと電気的に接続される、連続した単一の平面パターンを持つよう形成されており、
前記基板裏面電極は、該複数の接続電極の各々毎に分離された平面パターンを持つよう形成されている、半導体装置。 - 請求項1に記載の半導体装置において、
前記基板表面電極は、前記複数の接続電極の各々毎に分離された平面パターンを持つよう形成されており、
前記基板裏面電極は、前記複数の接続電極の全てと電気的に接続される、連続した単一の平面パターンを持つよう形成されている、半導体装置。 - 請求項2に記載の半導体装置において、
前記絶縁性基板上に配置された前記半導体素子を封止する封止樹脂を備え、
前記絶縁性基板の側面には、その表面および裏面の一方側から他方側に延びる切欠部が形成され、
前記複数の接続電極は、該切欠部の表面に形成され、前記基板表面電極と前記基板裏面電極とを電気的に接続する複数の側面電極である、半導体装置。 - 請求項4に記載の半導体装置において、
前記側面電極と前記基板表面電極との接続部は、前記封止樹脂が、該側面電極の形成されている切欠部に侵入するのを阻止されるよう形成した絶縁膜により覆われている、半導体装置。 - 請求項2に記載の半導体装置において、
前記絶縁性基板に形成され、その表面および裏面の一方側から他方側に延びるスルーホールを有し、
前記接続電極は、該スルーホールの内面に形成され、前記基板表面電極と前記基板裏面電極とを接続する複数の貫通電極である、半導体装置。 - 請求項5に記載の半導体装置において、
前記基板表面電極は、
前記絶縁性基板の表面側に形成され、前記半導体素子の第1の素子電極と接続される第1の基板表面電極と、
該絶縁性基板の表面側に形成され、該半導体素子の第2の素子電極と接続される第2の基板表面電極とを含み、
前記基板裏面電極は、
該絶縁性基板の裏面側に形成され、該第1の基板表面電極と電気的に接続される第1の基板裏面電極と、
該絶縁性基板の裏面側に形成され、該第2の基板表面電極と電気的に接続される第2の基板裏面電極とを含み、
前記側面電極は、
該絶縁性基板の厚み方向に沿ってその表面および裏面の一方側から他方側に延び、該第1の基板表面電極と該第1の基板裏面電極とを電気的に接続する複数の第1の側面電極と、
該絶縁性基板の厚み方向に沿ってその表面および裏面の一方側から他方側に延び、該第2の基板表面電極と該第2の基板裏面電極とを電気的に接続する複数の第2の側面電極とを含み、
該第1の基板裏面電極は、
該複数の第1の側面電極の各々毎に分離された平面パターンを持つよう形成されており、
該第2の基板裏面電極は、
該複数の第2の側面電極の各々毎に分離された平面パターンを持つよう形成されている、半導体装置。 - 請求項7に記載の半導体装置において、
前記半導体素子は、前記第1の素子電極としてカソード電極を有し、かつ前記第2の素子電極としてアノード電極を有する発光ダイオードであり、
前記第1の素子電極であるカソード電極と前記第1の基板表面電極とが接続され、
前記第2の素子電極であるアノード電極と前記第2の基板表面電極とが接続されている、半導体装置。 - 請求項8に記載の半導体装置において、
前記カソード電極と接続される第1の基板表面電極は、2つの前記第1の側面電極を介して前記第1の基板裏面電極と接続されており、
前記アノード電極と接続される第2の基板表面電極は、2つの前記第2の側面電極を介して前記第2の基板裏面電極と接続されている、半導体装置。 - 請求項1に記載の半導体装置において、
前記基板表面電極および前記基板裏面電極は、
前記絶縁性基板上に設定されている、該絶縁性基板のスクライブを行うためのスクライブラインと重ならないよう配置されている半導体装置。 - 請求項3に記載の半導体装置において、
前記絶縁性基板上に前記半導体素子を覆うよう形成され、該半導体素子を封止する封止体を有し、
前記基板表面電極は、該封止体の内部からその外部に達するよう形成されている、半導体装置。 - 請求項1に記載の半導体装置において、
前記絶縁性基板はセラミック基板である、半導体装置。 - 請求項1に記載の半導体装置を検査する検査方法であって、
前記基板表面電極が、前記複数の接続電極の各々毎に分離された平面パターンを持つとき、該基板表面電極の、分離された2つの平面パターンに対応する部分の間に電圧を印加し、前記基板裏面電極が、前記複数の接続電極の各々毎に分離された平面パターンを持つとき、該基板裏面電極の、分離された2つの平面パターンに対応する部分の間に電圧を印加するステップと、
該電圧を印加するステップにより発生する電流値に基づいて、該複数の接続電極と該基板表面電極および該基板裏面電極との導通状態を確認するステップと
を含む、半導体装置の検査方法。 - 半導体装置を備えた電気機器であって、
該半導体装置は、請求項1ないし請求項12のいずれかに記載の半導体装置である電気機器。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2010192898A JP5649878B2 (ja) | 2010-08-30 | 2010-08-30 | 半導体装置およびその検査方法、並びに電気機器 |
US13/221,007 US8749263B2 (en) | 2010-08-30 | 2011-08-30 | Semiconductor apparatus, inspection method thereof and electric device |
CN201110254113.0A CN102386320B (zh) | 2010-08-30 | 2011-08-30 | 半导体装置及其检测方法和电子设备 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2010192898A JP5649878B2 (ja) | 2010-08-30 | 2010-08-30 | 半導体装置およびその検査方法、並びに電気機器 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2012049480A true JP2012049480A (ja) | 2012-03-08 |
JP5649878B2 JP5649878B2 (ja) | 2015-01-07 |
Family
ID=45696310
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2010192898A Expired - Fee Related JP5649878B2 (ja) | 2010-08-30 | 2010-08-30 | 半導体装置およびその検査方法、並びに電気機器 |
Country Status (3)
Country | Link |
---|---|
US (1) | US8749263B2 (ja) |
JP (1) | JP5649878B2 (ja) |
CN (1) | CN102386320B (ja) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2016152905A1 (ja) * | 2015-03-26 | 2016-09-29 | 京セラ株式会社 | 配線基板、電子装置および電子モジュール |
EP3278920A1 (en) | 2014-04-02 | 2018-02-07 | Senju Metal Industry Co., Ltd. | Solder alloy for led |
US10347809B2 (en) | 2016-09-21 | 2019-07-09 | Toyoda Gosei Co., Ltd. | Light-emitting device |
JP2020087978A (ja) * | 2018-11-15 | 2020-06-04 | 日亜化学工業株式会社 | 発光装置の製造方法、発光装置及び光源装置 |
JP2020194900A (ja) * | 2019-05-29 | 2020-12-03 | 新日本無線株式会社 | 電子回路装置 |
Families Citing this family (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20150004118A (ko) * | 2013-07-02 | 2015-01-12 | 삼성디스플레이 주식회사 | 표시 장치용 기판, 상기 표시 장치용 기판의 제조 방법, 및 상기 표시 장치용 기판을 포함하는 표시 장치 |
TWD164809S (zh) * | 2014-01-28 | 2014-12-11 | 璨圓光電股份有限公司 | 發光二極體晶片之部分 |
TWD173888S (zh) * | 2014-01-28 | 2016-02-21 | 璨圓光電股份有限公司 | 發光二極體晶片之部分 |
TWD173883S (zh) * | 2014-01-28 | 2016-02-21 | 璨圓光電股份有限公司 | 發光二極體晶片之部分 |
TWD173887S (zh) * | 2014-01-28 | 2016-02-21 | 璨圓光電股份有限公司 | 發光二極體晶片之部分 |
USD745472S1 (en) * | 2014-01-28 | 2015-12-15 | Formosa Epitaxy Incorporation | Light emitting diode chip |
TWD163754S (zh) * | 2014-01-28 | 2014-10-21 | 璨圓光電股份有限公司 | 發光二極體晶片之部分 |
USD757663S1 (en) * | 2014-01-28 | 2016-05-31 | Formosa Epitaxy Incorporation | Light emitting diode chip |
USD745474S1 (en) * | 2014-01-28 | 2015-12-15 | Formosa Epitaxy Incorporation | Light emitting diode chip |
CN105280626A (zh) * | 2014-06-25 | 2016-01-27 | 常州欧密格光电科技有限公司 | 超小超薄高光效侧射型高亮白光led元件 |
CN116995170A (zh) * | 2023-05-24 | 2023-11-03 | 佛山科学技术学院 | 一种电极封装结构和发光模组 |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH1074800A (ja) * | 1996-08-29 | 1998-03-17 | Nec Corp | 半導体装置の実装構造、実装用基板および実装状 態の検査方法 |
JP2000091645A (ja) * | 1998-09-10 | 2000-03-31 | Sharp Corp | 半導体発光装置及びその製造方法 |
JP2001298244A (ja) * | 2000-04-17 | 2001-10-26 | Mitsubishi Electric Corp | 半導体装置実装用プリント基板 |
JP2003121492A (ja) * | 2001-10-15 | 2003-04-23 | Matsushita Electric Ind Co Ltd | 球面バンプとの接触構造 |
JP2006196702A (ja) * | 2005-01-13 | 2006-07-27 | Epson Toyocom Corp | 表面実装型電子デバイス |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001177159A (ja) * | 1999-12-16 | 2001-06-29 | Matsushita Electronics Industry Corp | 半導体装置 |
JP4360788B2 (ja) * | 2002-08-29 | 2009-11-11 | シチズン電子株式会社 | 液晶表示板用のバックライト及びそれに用いる発光ダイオードの製造方法 |
US8288936B2 (en) * | 2007-06-05 | 2012-10-16 | Sharp Kabushiki Kaisha | Light emitting apparatus, method for manufacturing the light emitting apparatus, electronic device and cell phone device |
CN101325193B (zh) * | 2007-06-13 | 2010-06-09 | 先进开发光电股份有限公司 | 发光二极管封装体 |
-
2010
- 2010-08-30 JP JP2010192898A patent/JP5649878B2/ja not_active Expired - Fee Related
-
2011
- 2011-08-30 US US13/221,007 patent/US8749263B2/en active Active
- 2011-08-30 CN CN201110254113.0A patent/CN102386320B/zh not_active Expired - Fee Related
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH1074800A (ja) * | 1996-08-29 | 1998-03-17 | Nec Corp | 半導体装置の実装構造、実装用基板および実装状 態の検査方法 |
JP2000091645A (ja) * | 1998-09-10 | 2000-03-31 | Sharp Corp | 半導体発光装置及びその製造方法 |
JP2001298244A (ja) * | 2000-04-17 | 2001-10-26 | Mitsubishi Electric Corp | 半導体装置実装用プリント基板 |
JP2003121492A (ja) * | 2001-10-15 | 2003-04-23 | Matsushita Electric Ind Co Ltd | 球面バンプとの接触構造 |
JP2006196702A (ja) * | 2005-01-13 | 2006-07-27 | Epson Toyocom Corp | 表面実装型電子デバイス |
Cited By (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP3278920A1 (en) | 2014-04-02 | 2018-02-07 | Senju Metal Industry Co., Ltd. | Solder alloy for led |
US10265807B2 (en) | 2014-04-02 | 2019-04-23 | Senju Metal Industry Co., Ltd. | Solder alloy and module |
US10272527B2 (en) | 2014-04-02 | 2019-04-30 | Senju Metal Industry Co., Ltd. | Solder alloy, and LED module |
WO2016152905A1 (ja) * | 2015-03-26 | 2016-09-29 | 京セラ株式会社 | 配線基板、電子装置および電子モジュール |
US10347809B2 (en) | 2016-09-21 | 2019-07-09 | Toyoda Gosei Co., Ltd. | Light-emitting device |
JP2020087978A (ja) * | 2018-11-15 | 2020-06-04 | 日亜化学工業株式会社 | 発光装置の製造方法、発光装置及び光源装置 |
JP7186358B2 (ja) | 2018-11-15 | 2022-12-09 | 日亜化学工業株式会社 | 発光装置の製造方法、発光装置及び光源装置 |
JP2020194900A (ja) * | 2019-05-29 | 2020-12-03 | 新日本無線株式会社 | 電子回路装置 |
JP7332094B2 (ja) | 2019-05-29 | 2023-08-23 | 日清紡マイクロデバイス株式会社 | 電子回路装置 |
Also Published As
Publication number | Publication date |
---|---|
JP5649878B2 (ja) | 2015-01-07 |
CN102386320B (zh) | 2014-07-23 |
US8749263B2 (en) | 2014-06-10 |
CN102386320A (zh) | 2012-03-21 |
US20120049882A1 (en) | 2012-03-01 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP5649878B2 (ja) | 半導体装置およびその検査方法、並びに電気機器 | |
EP3582261B1 (en) | Method for preparing a surface-mounted rgb-led packaging module | |
US7675755B2 (en) | LED module | |
US20150049447A1 (en) | Base Substrate Which Prevents Burrs Generated During the Cutting Process and Method for Manufacturing the Same | |
CN105895792A (zh) | 发光组件 | |
JP2009130195A (ja) | 半導体発光装置 | |
JP2009141169A (ja) | 半導体装置 | |
JP6226068B2 (ja) | 半導体装置 | |
US20050280018A1 (en) | Light-emitting diode | |
JP2009054860A (ja) | チップ型半導体装置 | |
CN101840976A (zh) | 发光元件 | |
US9655238B2 (en) | Wiring board, method for manufacturing wiring board, and electronic device | |
JP5227693B2 (ja) | 半導体発光装置 | |
RU2721101C2 (ru) | Островковый держатель для светоизлучающего устройства | |
JP2013045842A (ja) | 発光装置 | |
JP5779406B2 (ja) | 照明装置 | |
CN102468406B (zh) | 发光二极管封装结构及其制造方法 | |
JP2020161697A (ja) | 半導体発光装置 | |
KR20120116945A (ko) | 발광 장치 | |
CN111162063A (zh) | 一种led器件、显示屏及其封装工艺 | |
KR20080101250A (ko) | 발광다이오드 패키지 및 이를 이용한 투명 전광판 | |
JP6094415B2 (ja) | 配線基板および基板モジュール | |
US20240172364A1 (en) | Circuit board, display apparatus, and method for manufacturing circuit board | |
JP4453004B2 (ja) | 発光素子搭載用の配線基板 | |
JP6711568B2 (ja) | 半導体装置 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20130401 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20130926 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20140107 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20140217 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20141022 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20141112 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 5649878 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
RD04 | Notification of resignation of power of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: R3D04 |
|
LAPS | Cancellation because of no payment of annual fees |