JP2012049338A - Semiconductor chip with heater wiring - Google Patents

Semiconductor chip with heater wiring Download PDF

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Publication number
JP2012049338A
JP2012049338A JP2010190249A JP2010190249A JP2012049338A JP 2012049338 A JP2012049338 A JP 2012049338A JP 2010190249 A JP2010190249 A JP 2010190249A JP 2010190249 A JP2010190249 A JP 2010190249A JP 2012049338 A JP2012049338 A JP 2012049338A
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JP
Japan
Prior art keywords
semiconductor chip
heater wiring
heater
film
wiring
Prior art date
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Pending
Application number
JP2010190249A
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Japanese (ja)
Inventor
Takehiko Hasebe
健彦 長谷部
Yukiko Kato
薫子 加藤
Yoshihide Yamaguchi
欣秀 山口
Masato Nakamura
真人 中村
Takashi Kashimura
隆司 樫村
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Hitachi Ltd
Original Assignee
Hitachi Ltd
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Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP2010190249A priority Critical patent/JP2012049338A/en
Priority to PCT/JP2011/003460 priority patent/WO2012026057A1/en
Publication of JP2012049338A publication Critical patent/JP2012049338A/en
Pending legal-status Critical Current

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    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Wire Bonding (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a highly-reliable mounting technique of a semiconductor chip.SOLUTION: A semiconductor chip 4 comprises a substrate 100, a device layer 80 formed on one surface of the substrate, heater wiring 302 that generates heat by radiation of electromagnetic waves, and an electrode 103 that is electrically connected to the device layer. When the semiconductor chip 4 is mounted on a mounting substrate, a fastening material is melt by making a metal wiring film 302 generate heat as a heater, thereby causing the semiconductor chip to be connected to the mounting substrate.

Description

本発明は、半導体チップの実装方法とこれを実現するための実装構造に関する。   The present invention relates to a semiconductor chip mounting method and a mounting structure for realizing the method.

大規模集積回路（ＬＳＩ）やメモリをはじめとする電子部品では、信号処理の高速化や、実装密度の向上が強く要求されている。そのため、半導体チップやプリント基板の配線や端子は微細化が著しく進んでいる。特に、システム化の容易さから、半導体チップを複数組み合わせた半導体パッケージの開発が活発となり、薄く研磨した半導体チップを積層した３次元実装技術が注目されている。このような３次元実装構造では、半導体チップと基板の双方の配線密度が向上し、半導体チップと基板を電気的に接続する端子についても、微細化や多ピン化が急激に進んでいる。上記のような高密度の半導体チップでは、その実装に用いられる材料が非常に多く、また、複雑なプロセスを経て製造される。   In electronic parts such as large-scale integrated circuits (LSIs) and memories, there is a strong demand for faster signal processing and improved packaging density. For this reason, the miniaturization of the wiring and terminals of the semiconductor chip and the printed circuit board has progressed remarkably. In particular, the development of a semiconductor package in which a plurality of semiconductor chips are combined has become active due to the ease of systemization, and a three-dimensional mounting technique in which thinly polished semiconductor chips are stacked has attracted attention. In such a three-dimensional mounting structure, the wiring density of both the semiconductor chip and the substrate is improved, and the miniaturization and the increase in the number of pins of the terminals that electrically connect the semiconductor chip and the substrate are rapidly progressing. The above-described high-density semiconductor chip has a very large amount of materials used for mounting and is manufactured through a complicated process.

両者を接続するための部材として、はんだや金のバンプ、導電性フィラを混錬した異方導電性樹脂などが一般的である。これらを接続するには、部材を位置あわせしつつ積層し、加熱する方法が多く用いられている。例えばはんだの場合、はんだの融点を超える温度までリフロー炉などで加熱・冷却している。   As a member for connecting the two, a solder, a gold bump, an anisotropic conductive resin kneaded with a conductive filler, and the like are generally used. In order to connect them, a method of laminating and heating the members while aligning them is often used. For example, in the case of solder, it is heated and cooled in a reflow furnace to a temperature exceeding the melting point of the solder.

一般的に、複数の半導体チップを積層した後に一括加熱により実装する方法（特許文献１）、あるいは、半導体チップを積層の度に加熱を繰り返して実装する方法（特許文献２）が用いられている。後者の場合、後の工程では先の工程における処理の信頼性を損なわないよう、先の工程よりも低温で処理を行ういわゆる温度階層プロセスが採用される。   In general, a method in which a plurality of semiconductor chips are stacked and then mounted by batch heating (Patent Document 1), or a method in which heating is repeatedly performed every time a semiconductor chip is stacked (Patent Document 2) is used. . In the latter case, a so-called temperature hierarchical process in which processing is performed at a lower temperature than the previous step is employed in the subsequent step so as not to impair the reliability of the processing in the previous step.

また、実装パッケージはシリコン、配線に用いられる金属、基板の絶縁層やアンダーフィルに用いられるエポキシやポリイミドなど有機系材料など、さまざまな材料で構成されている。   The mounting package is made of various materials such as silicon, metals used for wiring, and organic materials such as epoxy and polyimide used for insulating layers and underfills of substrates.

特開２００２−１７０９１９号公報JP 2002-170919 A 特願２００７−６７７５４号公報Japanese Patent Application No. 2007-67754

しかしながら、特許文献１、２の方法によって、リフロー炉で加熱する場合において、リフロー炉の高温雰囲気中に半導体パッケージを投入すると、パッケージの外周から内部に向かって熱が伝播するため、パッケージ内部を十分に加熱するには外周の温度は実装上必要な温度よりも高温となってしまう。すなわち、パッケージを均一に加熱することは極めて困難となる。   However, when heating in a reflow furnace by the methods of Patent Documents 1 and 2, if a semiconductor package is placed in a high-temperature atmosphere of the reflow furnace, heat propagates from the outer periphery of the package toward the inside. In order to heat it, the temperature of the outer periphery becomes higher than the temperature necessary for mounting. That is, it becomes extremely difficult to uniformly heat the package.

チップ多層化が進みパッケージ構造が複雑化すると温度階層の多段化が必要となるが、パッケージ加熱の不均一性が拡大する傾向は益々顕著となる。そのため、熱による高信頼実装は極めて困難となる。当然、特定のチップの選択的に加熱することはできない。   As the number of chips increases and the package structure becomes more complicated, it is necessary to increase the number of stages in the temperature hierarchy, but the tendency to increase the non-uniformity of package heating becomes more prominent. Therefore, highly reliable mounting by heat becomes extremely difficult. Of course, specific chips cannot be selectively heated.

また、実使用環境にさらされた半導体パッケージは、繰り返される電源のオン／オフにより温度が上下動する。実装パッケージの構成部材は、それぞれ異なる熱膨張特性を有するため、温度の上下により構成部材には応力が生じる。半導体チップと実装基板の接続部材であるはんだやアンダーフィルは応力が特に集中しやすく、部材の割れや剥離が生じやすい。   In addition, the temperature of a semiconductor package exposed to an actual use environment fluctuates up and down due to repeated ON / OFF of a power supply. Since the constituent members of the mounting package have different thermal expansion characteristics, stress is generated in the constituent members due to an increase or decrease in temperature. Solder and underfill, which are connecting members between a semiconductor chip and a mounting board, are particularly susceptible to stress concentration, and the members are likely to crack or peel off.

本発明は、上記課題を解決すべくなされたものであり、半導体チップの高信頼実装技術を提供することを目的とする。   The present invention has been made to solve the above-described problems, and an object thereof is to provide a highly reliable mounting technique for a semiconductor chip.

例えば、本発明にかかる半導体チップは、基板と、前記基板の一方の面に形成されたデバイス層と、電磁波の輻射により発熱するヒータ配線と、前記デバイス層と電気的に接続される電極とを備えることを特徴とする。   For example, a semiconductor chip according to the present invention includes a substrate, a device layer formed on one surface of the substrate, a heater wiring that generates heat by radiation of electromagnetic waves, and an electrode electrically connected to the device layer. It is characterized by providing.

本発明によれば、半導体チップの実装信頼性を高められる技術が提供される。   ADVANTAGE OF THE INVENTION According to this invention, the technique which can improve the mounting reliability of a semiconductor chip is provided.

本発明の実施例１にかかる半導体チップ１の構造を示す断面図である。It is sectional drawing which shows the structure of the semiconductor chip 1 concerning Example 1 of this invention. 金属配線膜１０１の配線パターンの一例を表す上面図である。3 is a top view illustrating an example of a wiring pattern of a metal wiring film 101. FIG. 金属配線膜１０２の配線パターンの一例を表す上面図である。3 is a top view illustrating an example of a wiring pattern of a metal wiring film 102. FIG. 電極１０３の一例を表す上面図である。3 is a top view illustrating an example of an electrode 103. FIG. 半導体チップ１の製造過程を示す遷移図である。6 is a transition diagram illustrating a manufacturing process of the semiconductor chip 1. FIG. 本発明の実施例２にかかる半導体チップ２の断面図である。It is sectional drawing of the semiconductor chip 2 concerning Example 2 of this invention. 本発明の実施例３にかかる半導体チップ３の断面図である。It is sectional drawing of the semiconductor chip 3 concerning Example 3 of this invention. 本発明の実施例４にかかる半導体チップ４の断面図である。It is sectional drawing of the semiconductor chip 4 concerning Example 4 of this invention. 半導体チップ１と実装基板１１１が、はんだボールを挟んで位置あわせされた断面図である。FIG. 5 is a cross-sectional view in which the semiconductor chip 1 and the mounting substrate 111 are aligned with a solder ball interposed therebetween. 外部アンテナ８０１と搬送波制御装置の模式図である。It is a schematic diagram of an external antenna 801 and a carrier wave control device. 半導体チップ積層体５の断面図である。2 is a cross-sectional view of a semiconductor chip stacked body 5. FIG. ３次元積層チップの接続部の一例を示した説明図である。It is explanatory drawing which showed an example of the connection part of a three-dimensional multilayer chip.

以下、本発明の各実施例について図面を参照しながら説明する。尚、すべての図面において、同様な構成要素には同様の符号を付し、適宜説明を省略する。   Embodiments of the present invention will be described below with reference to the drawings. In all the drawings, the same reference numerals are given to the same components, and the description will be omitted as appropriate.

図１は、本発明の実施例に係る半導体チップ１の断面図である。   FIG. 1 is a cross-sectional view of a semiconductor chip 1 according to an embodiment of the present invention.

半導体チップ１は、シリコン基板１００の一方の面に、メモリ設計に基づき半導体前工程によりトランジスタが単層あるいは多層に形成されたデバイス層８０と、測温抵抗体としての金属配線膜１０１と、絶縁層としてのポリイミド膜１０４ａと、ヒータとしての金属配線膜１０２と、絶縁層としてのポリイミド膜１０４ｂと、金属配線膜１０１及びデバイス層８０を実装基板に電気的に接続するための電極１０３と、保護層としてのポリイミド膜１０４ｃと、が順次積層されてなる。   The semiconductor chip 1 includes a device layer 80 in which transistors are formed in a single layer or multiple layers by a semiconductor pre-process based on a memory design, a metal wiring film 101 as a resistance temperature detector, A polyimide film 104a as a layer, a metal wiring film 102 as a heater, a polyimide film 104b as an insulating layer, an electrode 103 for electrically connecting the metal wiring film 101 and the device layer 80 to a mounting substrate, and protection A polyimide film 104c as a layer is sequentially laminated.

図２に、金属配線膜１０１の配線パターンの一例を示す。図２に示すように、金属配線膜１０１は、方形に蛇行する独立したＰｔ配線が、３×３のマトリクス状に分画された領域にそれぞれ形成されている。ここでは、各Ｐｔ配線はそれぞれ配線の両端に２つずつ、計４つの端子１０１１を有しており、端子１０１１は電極１０３に接続される。このように、各配線の電気抵抗はいわゆる４端子法により測定できる。なお、白金の抵抗温度係数（３．９×１０−３／Ｋ）であり、温度によって抵抗値が変化するため、Ｐｔ配線の各領域における温度を測定することが可能である。 FIG. 2 shows an example of the wiring pattern of the metal wiring film 101. As shown in FIG. 2, the metal wiring film 101 is formed in an area where independent Pt wirings meandering in a square shape are fractionated in a 3 × 3 matrix. Here, each Pt wiring has a total of four terminals 1011, two at each end of the wiring, and the terminal 1011 is connected to the electrode 103. Thus, the electrical resistance of each wiring can be measured by a so-called four-terminal method. Note that platinum has a temperature coefficient of resistance (3.9 × 10 −3 / K), and the resistance value varies depending on the temperature. Therefore, the temperature in each region of the Pt wiring can be measured.

後述の通り、半導体チップ１を他の実装基板に実装する際には、ヒータとしての金属配線膜１０２を発熱させることにより、固着材料を溶かして半導体チップを実装基板と接続させる。測温抵抗体としての金属配線膜１０１を設けて、温度を計測しながらヒータとしての金属配線膜１０２を発熱させることにより、より精確に金属配線膜１０２の温度を制御することができるようになる。即ち、固着材料が溶ける温度であって、デバイス層８０が熱によりダメージを受けない温度に制御できるようになる。   As will be described later, when the semiconductor chip 1 is mounted on another mounting substrate, the metal wiring film 102 serving as a heater is heated to melt the fixing material and connect the semiconductor chip to the mounting substrate. By providing the metal wiring film 101 as a resistance temperature detector and generating heat in the metal wiring film 102 as a heater while measuring the temperature, the temperature of the metal wiring film 102 can be controlled more accurately. . In other words, the temperature at which the fixing material is melted and the temperature at which the device layer 80 is not damaged by heat can be controlled.

なお、ここでは各領域で独立したＰｔ配線を設けた構成としているが、金属配線膜１０１が一つの連続した配線からなる構成としてもよいし、連続した配線を途中から分岐させ、端子を設けてもよい。   Here, the configuration is such that an independent Pt wiring is provided in each region, but the metal wiring film 101 may be configured by one continuous wiring, or the continuous wiring may be branched from the middle to provide a terminal. Also good.

また、金属配線膜１０１に使用する金属材料としては、温度と電気抵抗の線形成に優れていることから特に白金を利用することが望ましいが、これに限らず、例えばニッケル、銅などを利用してもよい。   Further, as the metal material used for the metal wiring film 101, it is desirable to use platinum in particular because it is excellent in forming a line of temperature and electric resistance, but not limited to this, for example, using nickel, copper, or the like. May be.

金属配線膜１０２は、ヒータとして利用可能な金属の配線パターンが形成されたものである。金属配線膜１０２は電磁波の輻射により発熱する。図３に、金属配線膜１０２の配線パターンの一例を示す。図３に示すように、金属配線膜１０２は、コイル形状（渦巻状）のＮｉ配線パターンである。なお、本実施例では金属配線膜の形状を四角形が徐々に大きくなる渦巻状としたが、円が徐々に大きくなるような渦巻状であってもよい。   The metal wiring film 102 is formed with a metal wiring pattern that can be used as a heater. The metal wiring film 102 generates heat due to radiation of electromagnetic waves. FIG. 3 shows an example of the wiring pattern of the metal wiring film 102. As shown in FIG. 3, the metal wiring film 102 is a coil-shaped (spiral) Ni wiring pattern. In the present embodiment, the metal wiring film has a spiral shape in which the quadrangle gradually increases, but may have a spiral shape in which the circle gradually increases.

金属配線膜１０２は、面積、巻き数、配線長を変えることにより、自己インダクタンスを固有の値に設定することができ、厚さ、配線間隔、配線長を変えることにより、キャパシタンスを固有の値に設定することができる。自己インダクタンス、キャパシタンスを固有の値に設定することにより、金属配線膜１０２の共振周波数を固有の値に設定することができ、金属配線膜１０２の共振周波数と同程度の電磁波を輻射することにより、金属配線膜１０２発熱させることができる。   The metal wiring film 102 can set the self-inductance to a unique value by changing the area, the number of turns, and the wiring length, and can change the capacitance to a unique value by changing the thickness, the wiring interval, and the wiring length. Can be set. By setting the self-inductance and capacitance to unique values, the resonance frequency of the metal wiring film 102 can be set to a unique value, and by radiating electromagnetic waves having the same level as the resonance frequency of the metal wiring film 102, The metal wiring film 102 can generate heat.

また、金属配線膜１０２に使用する金属材料は上記に限らず、高い電気抵抗、パターニング性、高温耐久性を有する金属、例えば、ニッケルクロム系合金、ニッケルクロムアルミニウム系合金、銅、銅マンガン、銅ニッケル、鉄クロム系合金、タングステンなどを利用してもよい。   The metal material used for the metal wiring film 102 is not limited to the above, but a metal having high electrical resistance, patternability, and high temperature durability, such as nickel chromium alloy, nickel chromium aluminum alloy, copper, copper manganese, copper Nickel, iron-chromium alloy, tungsten, or the like may be used.

図４に、電極１０３の一例を示す。電極１０３は、金属配線膜１０１及び金属配線膜１０２と電気的に接続される、外部接続用の電極である。ここでは、外部接続用電極１０３１が金属配線膜１０１の端子１０１１と、外部接続用電極１０３２が金属配線膜１０２の有する端子１０２１と接続される。   FIG. 4 shows an example of the electrode 103. The electrode 103 is an external connection electrode that is electrically connected to the metal wiring film 101 and the metal wiring film 102. Here, the external connection electrode 1031 is connected to the terminal 1011 of the metal wiring film 101 and the external connection electrode 1032 is connected to the terminal 1021 of the metal wiring film 102.

電極１０３上には、ポリイミド膜１０４ｃが保護層として形成されており、ポリイミド膜１０４ｃには、後述する基板１１１や他の半導体チップと電極１０３（金属配線膜１０１）を接続するための開口２１、及び基板１１１と電極１０３（金属配線膜１０２）を接続するための開口２２が設けられている。   A polyimide film 104c is formed as a protective layer on the electrode 103. The polyimide film 104c has an opening 21 for connecting the electrode 111 (metal wiring film 101) to a substrate 111 or another semiconductor chip described later, In addition, an opening 22 for connecting the substrate 111 and the electrode 103 (metal wiring film 102) is provided.

さらに、絶縁層として、金属配線膜１０１と金属配線膜１０２の間にポリイミド膜１０４ａが、金属配線膜１０２と電極１０３の間にポリイミド膜１０４ｂが設けられている。ポリイミド膜１０４ａ及び１０４ｂには、共にデバイス層の端子と電極１０３とを接続するための開口１１、金属配線膜１０１と電極１０３とを接続するための開口１２が形成されている。   Further, as an insulating layer, a polyimide film 104 a is provided between the metal wiring film 101 and the metal wiring film 102, and a polyimide film 104 b is provided between the metal wiring film 102 and the electrode 103. The polyimide films 104 a and 104 b are both formed with an opening 11 for connecting the terminal of the device layer and the electrode 103 and an opening 12 for connecting the metal wiring film 101 and the electrode 103.

（半導体チップの製造方法）
次に、半導体チップ１の製造方法について、図５（ａ）〜図５（ｃ）を用いて説明する。図５（ａ）〜図５（ｃ）は、本発明の第１の実施形態にかかる半導体チップ１の製造方法の過程を示す遷移図である。 (Semiconductor chip manufacturing method)
Next, a method for manufacturing the semiconductor chip 1 will be described with reference to FIGS. 5 (a) to 5 (c). FIG. 5A to FIG. 5C are transition diagrams showing a process of the method for manufacturing the semiconductor chip 1 according to the first embodiment of the present invention.

（ａ）まず、シリコン基板１００の一方の面に、トランジスタや配線からなるデバイス層を形成し、図示しないシリコン酸化膜を成長させる。シリコン酸化膜は、９００℃程度のスチーム雰囲気下でシリコンと酸素を反応させるような、一般的な方法で形成すればよい。そして、シリコン酸化膜上に、プラチナ配線パターンを有する金属配線膜１０１をリフトオフ法により形成する。具体的には、まずシリコン酸化膜上にパターニングされたレジストを形成し、ＰｔＯ膜１０１ａ、Ｐｔ膜１０１ｂ、ＴｉＯ膜１０１ｃを順次蒸着する。そして、レジストを除去して図２に示す配線パターンを完成させる。   (A) First, a device layer made of a transistor and wiring is formed on one surface of the silicon substrate 100, and a silicon oxide film (not shown) is grown. The silicon oxide film may be formed by a general method in which silicon and oxygen are reacted in a steam atmosphere at about 900 ° C. Then, a metal wiring film 101 having a platinum wiring pattern is formed on the silicon oxide film by a lift-off method. Specifically, first, a patterned resist is formed on the silicon oxide film, and a PtO film 101a, a Pt film 101b, and a TiO film 101c are sequentially deposited. Then, the resist is removed to complete the wiring pattern shown in FIG.

なお、ＰｔＯ膜１０１ａはシリコン酸化膜と、ＴｉＯ膜１０１ｃはポリイミド膜１０４ａとの密着性を向上させるために、それぞれＰｔ膜１０１ｂに対して１／１００程度の膜圧で設けた。   The PtO film 101a and the TiO film 101c were provided with a film pressure of about 1/100 of the Pt film 101b, respectively, in order to improve the adhesion between the silicon oxide film and the TiO film 101c.

（ｂ）次に、絶縁層として、金属配線膜１０１の両端を覆い、端子１０１１部分を開口させた膜厚約５μｍのポリイミド膜１０４ａを形成する。そして、ポリイミド膜１０４ａ上に、ニッケル配線パターンを有する金属配線膜１０２を形成する。例えば、Ｃｒ膜及びＣｕ膜の積層膜をシード膜として、レジストのフォトリソグラフィ及びＮｉ電気めっきを併用するセミアディティブ法を用いることにより、図３に記載の配線パターンを有する金属配線膜１０２を形成することができる。さらに、金属配線膜１０２の両端を覆い、端子１０１１及び端子１０２１部分を開口させたポリイミド膜１０４ｂを形成する。   (B) Next, a polyimide film 104a having a film thickness of about 5 μm is formed as an insulating layer, covering both ends of the metal wiring film 101 and opening the terminal 1011 portion. Then, a metal wiring film 102 having a nickel wiring pattern is formed on the polyimide film 104a. For example, the metal wiring film 102 having the wiring pattern shown in FIG. 3 is formed by using a semi-additive method in which a laminated film of a Cr film and a Cu film is used as a seed film and resist photolithography and Ni electroplating are used in combination. be able to. Further, a polyimide film 104b is formed which covers both ends of the metal wiring film 102 and opens the terminal 1011 and the terminal 1021 portion.

（ｃ）そして最後に、ポリイミド膜１０４ｂ上に、セミアディティブ法により図４に記載の外部接続用の電極１０３を形成し、後述する実装基板等と電極１０３を接続するための開口を有する保護層としてのポリイミド膜１０４ｃを形成することで、図１に記載の半導体チップ１を得ることができる。   (C) Finally, the electrode 103 for external connection shown in FIG. 4 is formed on the polyimide film 104b by a semi-additive method, and a protective layer having an opening for connecting the mounting substrate and the electrode 103 to be described later to the electrode 103. 1 is formed, the semiconductor chip 1 shown in FIG. 1 can be obtained.

なお、本発明は、上記第１の実施形態にかかる半導体チップに制限されるものではなく、本発明の技術的思想の範囲内で様々な変形が可能である。   The present invention is not limited to the semiconductor chip according to the first embodiment, and various modifications can be made within the scope of the technical idea of the present invention.

例えば、測温抵抗体、及びヒータは、どのような位置関係で配置されていてもよい。   For example, the resistance temperature detector and the heater may be arranged in any positional relationship.

また、測温抵抗体、ヒータ、及び電極は、シリコン基板の同一面内（同一層）に形成してもよい。   The resistance temperature detector, the heater, and the electrode may be formed in the same plane (same layer) of the silicon substrate.

さらに、配線の温度と電気抵抗の関係を明らかにしておくことで、ヒータと測温抵抗体を一つの配線で兼ねることもできる。すなわち、配線に接続した電源から電力を供給すると同時に電気抵抗を測定すれば、別途配線を設けずとも発熱する配線自身の温度を測定することが可能となる。これにより、本発明の半導体チップの構造を大幅に簡素化することができる。   Furthermore, by clarifying the relationship between the temperature of the wiring and the electrical resistance, the heater and the resistance temperature detector can be combined with one wiring. That is, if electric power is supplied from a power source connected to the wiring and the electrical resistance is measured at the same time, the temperature of the wiring itself that generates heat can be measured without providing a separate wiring. Thereby, the structure of the semiconductor chip of the present invention can be greatly simplified.

なお、ヒータとしての金属配線膜１０２のみを備え、ヒータ配線に供給する電力とチップ温度の関係を明確化しておくことで、ある程度正確なチップ温度制御が可能となるため、より簡素な構成とすることができる。   In addition, since only the metal wiring film 102 as a heater is provided and the relationship between the power supplied to the heater wiring and the chip temperature is clarified, the chip temperature can be controlled with a certain degree of accuracy. be able to.

図６に、本発明の実施例２にかかる半導体チップ２の断面図を示す。半導体チップ２は、測温抵抗体としての金属配線膜３０１とヒータとしての金属配線膜３０２とが、同じ面内の酸化膜上に形成され、金属配線膜３０１及び金属配線膜３０２の両端を覆うように、金属配線膜３０１と電極１０３とを接続するための開口３１及び金属配線膜３０２と電極１０３とを接続するための開口３２を有するポリイミド膜３０４が設けられている。   FIG. 6 is a sectional view of a semiconductor chip 2 according to the second embodiment of the present invention. In the semiconductor chip 2, a metal wiring film 301 as a resistance temperature detector and a metal wiring film 302 as a heater are formed on the same oxide film and cover both ends of the metal wiring film 301 and the metal wiring film 302. Thus, a polyimide film 304 having an opening 31 for connecting the metal wiring film 301 and the electrode 103 and an opening 32 for connecting the metal wiring film 302 and the electrode 103 is provided.

このような構成によれば、絶縁層としての２つのポリイミド膜（ポリイミド膜１０４ａ及びポリイミド膜１０４ｂ）を１つのポリイミド膜３０４で実現できるため、半導体チップ１に比べて層数を減少させ、より低コストに、簡便な方法で半導体チップを製造することが可能である。   According to such a configuration, since two polyimide films (polyimide film 104a and polyimide film 104b) as insulating layers can be realized by one polyimide film 304, the number of layers is reduced compared to the semiconductor chip 1, and the lower It is possible to manufacture a semiconductor chip by a simple method at a low cost.

図７に、本発明の実施例３にかかる半導体チップ３の断面図を示す。半導体チップ３は、測温抵抗体とヒータの機能を兼ねる金属配線膜４０２のみが形成され、金属配線膜４０２の両端を覆うように、金属配線膜４０２と電極１０３とを接続するための開口４１及び４２を有するポリイミド膜４０４が設けられている。なお、金属配線膜４０２には、例えば、図２に示すようなＮｉ配線を利用することができる。このような半導体チップ４を後述する基板１１１に実装し、両端の端子に電源と電圧計を接続することで、Ｎｉ配線に流れる電流を制御するとともに、ニッケルの抵抗温度係数（６．３Ｋ×１０−３／Ｋ）からＮｉ配線の各領域における温度を測定することが可能である。もちろん、Ｎｉ配線に替えて、例えばＣｕ配線を利用してもよい。その場合には、銅の抵抗温度係数（４．３×１０−３／Ｋ）を利用すればよい。 FIG. 7 shows a cross-sectional view of a semiconductor chip 3 according to Example 3 of the present invention. In the semiconductor chip 3, only the metal wiring film 402 that functions as a resistance temperature detector and a heater is formed, and an opening 41 for connecting the metal wiring film 402 and the electrode 103 so as to cover both ends of the metal wiring film 402. And 42 are provided. For the metal wiring film 402, for example, Ni wiring as shown in FIG. 2 can be used. Such a semiconductor chip 4 is mounted on a substrate 111, which will be described later, and a power source and a voltmeter are connected to terminals at both ends, thereby controlling the current flowing through the Ni wiring and the resistance temperature coefficient of nickel (6.3 K × 10 −3 / K), the temperature in each region of the Ni wiring can be measured. Of course, instead of the Ni wiring, for example, a Cu wiring may be used. In that case, the resistance temperature coefficient of copper (4.3 × 10 −3 / K) may be used.

このような構成の半導体チップ４によれば、半導体チップ１に比べてポリイミド膜及び金属配線膜をそれぞれ１つずつ省略できるため、製造プロセスの簡素化と、製造コストの大幅な低減が可能である。   According to the semiconductor chip 4 having such a configuration, each of the polyimide film and the metal wiring film can be omitted one by one as compared with the semiconductor chip 1, so that the manufacturing process can be simplified and the manufacturing cost can be greatly reduced. .

図８に、本発明の実施例４にかかる半導体チップ４の断面図を示す。半導体チップ４は、ヒータとしての金属配線膜３０２が形成され、金属配線膜３０２の両端を覆うように、金属配線膜３０２と電極１０３とを接続するための開口３２を有するポリイミド膜３０４が設けられている。   FIG. 8 is a sectional view of a semiconductor chip 4 according to the fourth embodiment of the present invention. The semiconductor chip 4 is provided with a metal wiring film 302 as a heater, and a polyimide film 304 having an opening 32 for connecting the metal wiring film 302 and the electrode 103 is provided so as to cover both ends of the metal wiring film 302. ing.

このような構成によれば、絶縁層としての２つのポリイミド膜（ポリイミド膜１０４ａ及びポリイミド膜１０４ｂ）を１つのポリイミド膜３０４で実現できるため、半導体チップ１に比べて層数を減少させ、より低コストに、簡便な方法で半導体チップを製造することが可能である。   According to such a configuration, since two polyimide films (polyimide film 104a and polyimide film 104b) as insulating layers can be realized by one polyimide film 304, the number of layers is reduced compared to the semiconductor chip 1, and the lower It is possible to manufacture a semiconductor chip by a simple method at a low cost.

ここから、実施例１乃至４にかかる半導体チップの実装方法、半導体チップの作製方法、実装部材の修復方法について説明する。以下、実施例１にかかる半導体チップ１について説明するが、実施例２乃至４にかかる半導体チップ２−４についても同様である。   From here, the mounting method of the semiconductor chip concerning Example 1 thru | or 4, the manufacturing method of a semiconductor chip, and the repair method of a mounting member are demonstrated. Hereinafter, the semiconductor chip 1 according to the first embodiment will be described, but the same applies to the semiconductor chip 2-4 according to the second to fourth embodiments.

＜半導体チップの実装方法＞
半導体チップ１を基板１１１に実装する方法について説明する。図９は、半導体チップ１と実装基板１１１が、固着材料としてのはんだボール１０５を挟んで搭載されたものの断面図である。半導体チップ１のヒータは、その共振周波数が１３．５６ＭＨｚとしている。
図１０に外部アンテナ８０１と搬送波制御装置８０２の模式図を示す。搬送波制御装置は外部アンテナからさまざまな周波数帯域の電磁波が放出するよう、電源と制御装置を兼ねている。 <Semiconductor chip mounting method>
A method for mounting the semiconductor chip 1 on the substrate 111 will be described. FIG. 9 is a cross-sectional view of a semiconductor chip 1 and a mounting substrate 111 mounted with a solder ball 105 as a fixing material interposed therebetween. The heater of the semiconductor chip 1 has a resonance frequency of 13.56 MHz.
FIG. 10 shows a schematic diagram of the external antenna 801 and the carrier wave control device 802. The carrier wave control device doubles as a power source and a control device so that electromagnetic waves in various frequency bands are emitted from the external antenna.

図９において、半導体チップ１と実装基板１１１の電極は位置あわせは正確にされているものの、電気的に接続されてはいない状態である。半導体チップ１の直上に搬送波制御装置と接続したコイルアンテナを接近させ、半導体チップ１のコイルの共振周波数１３．５６ＭＨｚと同程度の電磁波を輻射させることで半導体チップ１のコイルに起電力が生じる。起電力による電流はコイルの電気抵抗Rによりジュール熱を生じることから、半導体チップ４は均一に加熱され、はんだの融点以上の温度となったときはんだボールが溶融する。搬送波制御装置により電磁波輻射を止めることで、半導体チップ１は室温に戻り、この過程ではんだボールは凝固し、半導体チップ１は実装基板１１１に実装される。   In FIG. 9, the electrodes of the semiconductor chip 1 and the mounting substrate 111 are accurately aligned but not electrically connected. An electromotive force is generated in the coil of the semiconductor chip 1 by bringing a coil antenna connected to the carrier wave control device close to the semiconductor chip 1 and radiating an electromagnetic wave having a resonance frequency of 13.56 MHz of the coil of the semiconductor chip 1. Since the current due to the electromotive force generates Joule heat due to the electric resistance R of the coil, the semiconductor chip 4 is uniformly heated, and the solder ball is melted when the temperature becomes higher than the melting point of the solder. By stopping electromagnetic wave radiation by the carrier wave control device, the semiconductor chip 1 returns to room temperature. In this process, the solder balls are solidified and the semiconductor chip 1 is mounted on the mounting substrate 111.

＜半導体チップ積層体の作製方法＞
図１１を用いて複数の半導体チップ１を積層させた半導体チップ積層体５を作製する方法について説明する。図１１は、第１の半導体チップ１、第２の半導体チップ１、第３の半導体チップ１がはんだボールを挟んで置かれたものの断面図である。なお、半導体チップ積層体５は、例えば、半導体チップ１の電極領域にスルーホール５０１を形成して導通をとり、電極表面はスズめっきを形成している。位置あわせは正確にされているものの、チップ１の電極同士は電気的に接続されてはいない状態である。 <Method for Fabricating Semiconductor Chip Laminate>
A method of manufacturing a semiconductor chip stacked body 5 in which a plurality of semiconductor chips 1 are stacked will be described with reference to FIG. FIG. 11 is a cross-sectional view of the first semiconductor chip 1, the second semiconductor chip 1, and the third semiconductor chip 1 placed with the solder balls interposed therebetween. In addition, the semiconductor chip laminated body 5 is made conductive by forming a through hole 501 in the electrode region of the semiconductor chip 1, for example, and the electrode surface is formed with tin plating. Although the alignment is correct, the electrodes of the chip 1 are not electrically connected to each other.

また第１の半導体チップに設けたヒータ配線の共振周波数f1、第２の半導体チップに設けたヒータ配線の共振周波数f2、第３の半導体チップに設けたヒータ配線の共振周波数f3は、いずれも１３．５６ＭＨｚ近傍ではあるもののf1≠f2≠f3となるよう設計したものである。即ち、複数の半導体チップのうち、少なくとも２つにおいて、共振周波数を異なるように設計した。   Further, the resonance frequency f1 of the heater wiring provided in the first semiconductor chip, the resonance frequency f2 of the heater wiring provided in the second semiconductor chip, and the resonance frequency f3 of the heater wiring provided in the third semiconductor chip are all 13. It is designed so that f1 ≠ f2 ≠ f3 though it is in the vicinity of 56 MHz. That is, at least two of the plurality of semiconductor chips are designed to have different resonance frequencies.

この設計において、共振周波数ｆ０は一般的に、

Figure 2012049338

と表される。ここで、半導体チップ１のコイル状ヒータ配線１０２を形成する面積、巻き数、配線長により半導体チップアンテナの自己インダクタンスL_chipを設定し、またコイル状ヒータ配線の厚さ、配線間隔や配線長により半導体チップのコイル状ヒータ配線１０２のキャパシタンスC_chipを設定することができる。自己インダクタンスL_chipとキャパシタンスC_chipと設定することにより、共振周波数f0_chipを設定する。 In this design, the resonant frequency f0 is generally
Figure 2012049338
It is expressed. Here, the self-inductance L_chip of the semiconductor chip antenna is set by the area, the number of turns, and the wiring length for forming the coiled heater wiring 102 of the semiconductor chip 1, and the semiconductor is determined by the thickness, wiring interval and wiring length of the coiled heater wiring. The capacitance C_chip of the coiled coil wiring 102 of the chip can be set. The resonant frequency f0_chip is set by setting the self-inductance L_chip and the capacitance C_chip.

ここで、f0_chipは以下のとおりに表される。

Figure 2012049338
Here, f0_chip is expressed as follows.
Figure 2012049338

また、搬送波制御装置およびこれと接続されたコイルアンテナの共振周波数については、自己インダクタンスL_rwおよびキャパシタンスC_rwを有するコイルアンテナに対し、可変キャパシタンスC_valとスイッチを直列に接続した回路を搬送波制御装置の内部にコイルアンテナと並列となるように設けた。スイッチによりアンテナの合成キャパシタンスC_com（ここで、C_com=C_rw+C_val）を設定することで、コイルアンテナからの搬送波の共振周波数は以下の式に示されるように制御される。

Figure 2012049338
Regarding the resonance frequency of the carrier wave control device and the coil antenna connected thereto, a circuit in which a variable capacitance C_val and a switch are connected in series to the coil antenna having the self-inductance L_rw and the capacitance C_rw is provided inside the carrier wave control device. It was provided in parallel with the coil antenna. By setting the combined capacitance C_com (where C_com = C_rw + C_val) of the antenna by the switch, the resonant frequency of the carrier wave from the coil antenna is controlled as shown in the following equation.
Figure 2012049338

キャパシタンスC_valとスイッチを直列に接続した回路を複数設けることにより、コイルアンテナからの搬送波の共振周波数を多段階で制御することも可能である。このように、コイルアンテナからの搬送波の共振周波数をf1、f2、f3に制御することにより、第１の半導体チップ１、第２の半導体チップ１、第３1の半導体チップ１をそれぞれ別個に加熱することができる。   By providing a plurality of circuits in which the capacitance C_val and the switch are connected in series, the resonance frequency of the carrier wave from the coil antenna can be controlled in multiple stages. In this way, the first semiconductor chip 1, the second semiconductor chip 1, and the third semiconductor chip 1 are heated separately by controlling the resonance frequencies of the carrier waves from the coil antenna to f1, f2, and f3, respectively. be able to.

即ち、搬送波制御装置と接続されたコイルアンテナを近接させ、周波数f1の電磁波を輻射させることで第１の半導体チップ１を選択的に加熱させることができる。これにより、半導体チップ１は実装基板１１１に実装される。搬送波制御装置の制御によりアンテナから周波数f2を放射することで第２の半導体チップ１と第１の半導体チップを接続した。また、第２の半導体チップ１と第１の半導体チップを接続する際、第１の半導体チップの測温抵抗体により第１のチップの温度をモニタしつつ第２のチップを加熱することで、第１のチップへの過剰な加熱を抑制することが可能となった。同様に、周波数f3の放射により第３の半導体チップ１と第２の半導体チップを接続した。このように、コイルアンテナからの電磁波の周波数を制御することで、特定の半導体チップの実装を実現できる。   That is, the first semiconductor chip 1 can be selectively heated by bringing the coil antenna connected to the carrier wave control device close and radiating the electromagnetic wave having the frequency f1. Thereby, the semiconductor chip 1 is mounted on the mounting substrate 111. The second semiconductor chip 1 and the first semiconductor chip were connected by radiating the frequency f2 from the antenna under the control of the carrier wave control device. Further, when connecting the second semiconductor chip 1 and the first semiconductor chip, by heating the second chip while monitoring the temperature of the first chip by the resistance temperature detector of the first semiconductor chip, It has become possible to suppress excessive heating of the first chip. Similarly, the third semiconductor chip 1 and the second semiconductor chip are connected by radiation of frequency f3. In this manner, by controlling the frequency of the electromagnetic wave from the coil antenna, a specific semiconductor chip can be mounted.

＜実装部材の修復方法＞
半導体パッケージが製品として長期稼動した際に懸念される接続部の実装信頼性の低下を修復する方法について説明する。 <Restoration method of mounting member>
A method for repairing a decrease in mounting reliability of a connection portion, which is a concern when a semiconductor package is operated as a product for a long time, will be described.

図１２は、図１１に示した３次元積層チップの接続部の一例を示したものである。半導体チップのスルーホールは銅めっきで充填されている。これに接続された電極のうち、片面の電極の表面にはニッケルとスズのめっき膜が逐次形成されている。他方の面の電極にはニッケルのめっき膜の上に金のバンプが形成されている。   FIG. 12 shows an example of the connection part of the three-dimensional multilayer chip shown in FIG. The through hole of the semiconductor chip is filled with copper plating. Among the electrodes connected to this, nickel and tin plating films are sequentially formed on the surface of one of the electrodes. Gold bumps are formed on the nickel plating film on the electrode on the other surface.

チップ間にエポキシ系Ｂステージ樹脂フィルム８５１をはさみつつ位置あわせしながら、こうした半導体チップを複数積層する。エポキシ系Ｂステージ樹脂フィルム８５１は、エポキシ系Ｂステージフィルムに熱可塑性樹脂を予め混錬したものである。   A plurality of such semiconductor chips are stacked while positioning the epoxy B-stage resin film 851 between the chips. The epoxy B stage resin film 851 is obtained by kneading a thermoplastic resin in advance with an epoxy B stage film.

このような半導体チップ積層体を、実施例１に示した方法で加熱することで、スズ系合金により電極間を接続するとともにエポキシ系材料でのチップ間充填により、図１２に示す半導体パッケージを作製した。   By heating such a semiconductor chip laminated body by the method shown in Example 1, the electrodes are connected with a tin-based alloy, and the semiconductor package shown in FIG. 12 is manufactured by inter-chip filling with an epoxy-based material. did.

このような半導体パッケージを製品として長期間稼動させた際、構成部材の熱膨張率の違いにより応力が生じる。これにより、エポキシ系充填材ではワレが、チップとの界面で剥離がそれぞれ進行する。稼動によるチップの熱を逃がす経路が減少するなど、実装信頼性を損ねる場合がある。   When such a semiconductor package is operated as a product for a long period of time, stress is generated due to a difference in coefficient of thermal expansion of the constituent members. As a result, cracking occurs in the epoxy filler, and peeling progresses at the interface with the chip. Mounting reliability may be impaired, for example, by reducing the number of paths through which the chip heat is released during operation.

エポキシ系Ｂステージ樹脂フィルム８５１を半導体チップ間に挟みつつ積層しておき、製品のライフサイクル中にチップに設けたヒータ配線にこのヒータ配線の共振周波数を含む電磁波を実施例１に記載の方法で適宜照射することにより、熱可塑性樹脂によりパッケージの応力を緩和させるとともにエポキシ系充填材でのワレやチップ界面剥離を再充填させることができる。   An epoxy B-stage resin film 851 is laminated while being sandwiched between semiconductor chips, and an electromagnetic wave including the resonance frequency of the heater wiring is applied to the heater wiring provided on the chip during the product life cycle by the method described in the first embodiment. By irradiating appropriately, the stress of the package can be relaxed by the thermoplastic resin, and cracking and chip interface peeling with the epoxy filler can be refilled.

これによれば、半導体パッケージの長期信頼性を向上させることができる。   According to this, the long-term reliability of the semiconductor package can be improved.

なお、上記の実施形態は、本発明の要旨を例示することを意図し、本発明を限定するものではない。多くの代替物、修正、変形例は当業者にとって明らかである。   In addition, said embodiment intends to illustrate the summary of this invention, and does not limit this invention. Many alternatives, modifications, and variations will be apparent to those skilled in the art.

１〜４：半導体チップ、５：半導体チップ積層体、８０：デバイス層、１００：シリコン基板、１０１：金属配線膜、１０１１：端子、１０１ａ：ＰｔＯ膜、１０１ｂ：Ｐｔ膜、１０１ｃ：ＴｉＯ膜、１０２：金属配線膜、１０２１：端子、１０３：電極、１０３１・１０３２：外部接続用電極、１０４ａ〜１０４ｃ：ポリイミド膜、１０５：はんだボール、１１・１２：開口、１１１：基板、３０１・３０２・４０２：金属配線膜、３０４・４０４：ポリイミド膜、２１・２２：開口、５０１：スルーホール、８０１：外部コイルアンテナ、８０２：搬送波制御装置、８５１：エポキシ系Ｂステージ樹脂フィルム 1-4: Semiconductor chip, 5: Semiconductor chip stack, 80: Device layer, 100: Silicon substrate, 101: Metal wiring film, 1011: Terminal, 101a: PtO film, 101b: Pt film, 101c: TiO film, 102 : Metal wiring film, 1021: Terminal, 103: Electrode, 1031-1032: External connection electrode, 104a to 104c: Polyimide film, 105: Solder ball, 11/12: Opening, 111: Substrate, 301/302/402: Metal wiring film, 304/404: Polyimide film, 21/22: Opening, 501: Through hole, 801: External coil antenna, 802: Carrier wave control device, 851: Epoxy B-stage resin film

Claims (11)

基板と、
前記基板の一方の面に形成されたデバイス層と、
電磁波の輻射により発熱するヒータ配線と、
前記デバイス層と電気的に接続される電極とを備えるヒータ配線付き半導体チップ。 A substrate,
A device layer formed on one side of the substrate;
Heater wiring that generates heat by radiation of electromagnetic waves;
A semiconductor chip with a heater wiring comprising an electrode electrically connected to the device layer. 前記ヒータ配線はコイル状に形成されることを特徴とする請求項１に記載のヒータ配線付き半導体チップ。   The semiconductor chip with heater wiring according to claim 1, wherein the heater wiring is formed in a coil shape. 前記基板の前記デバイス層が形成された面に温度により抵抗が変化する測温抵抗体が形成されたことを特徴とする請求項１に記載のヒータ配線付き半導体チップ。   2. The semiconductor chip with heater wiring according to claim 1, wherein a resistance temperature detector whose resistance varies with temperature is formed on a surface of the substrate on which the device layer is formed. 前記ヒータ配線と前記電極との間に絶縁層を設けることを特徴とする請求項１に記載の半導体チップ。   The semiconductor chip according to claim 1, wherein an insulating layer is provided between the heater wiring and the electrode. 前記絶縁層には、前記基板と前記電極とを接続する部分に開口が設けられることを特徴とする請求項４に記載の半導体チップ。   The semiconductor chip according to claim 4, wherein the insulating layer is provided with an opening at a portion connecting the substrate and the electrode. 前記ヒータ配線が前記基板上の前記デバイス層が形成された面に形成されることを特徴とする請求項１に記載のヒータ配線付き半導体チップ。   2. The semiconductor chip with heater wiring according to claim 1, wherein the heater wiring is formed on a surface of the substrate on which the device layer is formed. 前記デバイス層はプラチナ配線であることを特徴とする請求項１に記載のヒータ配線付き半導体チップ。   2. The semiconductor chip with heater wiring according to claim 1, wherein the device layer is platinum wiring. 前記ヒータ配線はニッケル配線であることを特徴とする請求項１に記載のヒータ配線付き半導体チップ。   2. The semiconductor chip with heater wiring according to claim 1, wherein the heater wiring is nickel wiring. 請求項１に記載のヒータ配線付き半導体チップを複数積層し、複数の前記ヒータ配線付き半導体チップのうち少なくとも２つにおいて、ヒータ配線の共振周波数を異ならせることを特徴とする半導体チップ積層体。   A semiconductor chip stack comprising a plurality of semiconductor chips with heater wiring according to claim 1, wherein at least two of the plurality of semiconductor chips with heater wiring have different resonance frequencies of the heater wiring. 請求項１に記載のヒータ配線付き半導体チップに外部アンテナから前記ヒータ配線に電磁波を輻射して前記ヒータ配線を発熱させ、前記電極の表面に配置された固着材料を溶解させることにより、ヒータ配線付き半導体チップを他の基板に実装することを特徴とするヒータ配線付き半導体チップの実装方法。   A semiconductor chip with a heater wiring according to claim 1, wherein an electromagnetic wave is radiated from an external antenna to the heater wiring to generate heat, and the fixing material disposed on the surface of the electrode is dissolved to dissolve the fixing material. A method of mounting a semiconductor chip with heater wiring, wherein the semiconductor chip is mounted on another substrate. 請求項１０に記載のヒータ配線付き半導体チップの実装方法によって実装されたヒータ配線付き半導体チップにおいて、
前記ヒータ配線を加熱して前記固着材料を溶融させ、加熱の停止により固着材料を再固着させ、前記電極と前記他の基板との接続を修復することを特徴とするヒータ付き半導体チップの修復方法。 In the semiconductor chip with heater wiring mounted by the mounting method of the semiconductor chip with heater wiring according to claim 10,
A method of repairing a semiconductor chip with a heater, wherein the heater wiring is heated to melt the fixing material, the fixing material is fixed again by stopping heating, and the connection between the electrode and the other substrate is repaired. .
JP2010190249A 2010-08-27 2010-08-27 Semiconductor chip with heater wiring Pending JP2012049338A (en)

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