JP2012023333A - 積層チップパッケージおよびその製造方法 - Google Patents
積層チップパッケージおよびその製造方法 Download PDFInfo
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- JP2012023333A JP2012023333A JP2011010372A JP2011010372A JP2012023333A JP 2012023333 A JP2012023333 A JP 2012023333A JP 2011010372 A JP2011010372 A JP 2011010372A JP 2011010372 A JP2011010372 A JP 2011010372A JP 2012023333 A JP2012023333 A JP 2012023333A
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Abstract
【解決手段】積層チップパッケージ1は、本体2と、本体2の側面2cに配置された複数のワイヤWを含む配線3とを備えている。本体2は、複数の階層部分10を含む主要部分2Mと、主要部分2Mの上面と下面の少なくとも一方に配置されて複数のワイヤWに接続された複数の端子4とを有している。各階層部分10は半導体チップを含んでいる。複数のワイヤWは、複数の共通ワイヤWAと複数の階層依存ワイヤWBとを含んでいる。少なくとも1つの階層部分10において、半導体チップは、複数の共通ワイヤWAに電気的に接続されていると共に、複数の階層依存ワイヤWBのうち、その階層部分10が利用する階層依存ワイヤWBにのみ選択的に、電気的に接続されている。
【選択図】図1
Description
それぞれ半導体チップとなる予定の、配列された複数の半導体チップ予定部を含む基礎構造物前ウェハを作製する工程と、
基礎構造物前ウェハに含まれる複数の半導体チップ予定部について、正常に動作する半導体チップ予定部と正常に動作しない半導体チップ予定部とを判別する工程と、
基礎構造物前ウェハが基礎構造物になるように、正常に動作する半導体チップ予定部では複数の共通電極および選択的接続電極が半導体チップ予定部に電気的に接続され、正常に動作しない半導体チップ予定部では複数の共通電極および選択的接続電極が半導体チップ予定部に電気的に接続されないように、複数の共通電極および選択的接続電極を形成する工程とを含んでいてもよい。
以下、本発明の実施の形態について図面を参照して詳細に説明する。始めに、図1ないし図5を参照して、本発明の第1の実施の形態に係る積層チップパッケージの構成について説明する。図1は、本発明の第1の実施の形態に係る積層チップパッケージの斜視図である。図2は、下側から見た図1の積層チップパッケージを示す斜視図である。図3は、図1の積層チップパッケージの配線を除いた部分を示す斜視図である。図4は、図1に示した積層チップパッケージに含まれる1つの階層部分を示す平面図である。図5は、図4に示した階層部分を示す斜視図である。
次に、本発明の第2の実施の形態について説明する。始めに、図50ないし図54を参照して、本実施の形態に係る積層チップパッケージ1について説明する。図50は、本実施の形態に係る積層チップパッケージ1の斜視図である。図51は、下側から見た図50の積層チップパッケージ1を示す斜視図である。図52は、図50の積層チップパッケージ1の配線を除いた部分を示す斜視図である。図53は、図50に示した積層チップパッケージ1に含まれる1つの階層部分を示す平面図である。図54は、図53に示した階層部分を示す斜視図である。
Claims (19)
- 上面、下面および4つの側面を有する本体と、
前記本体の少なくとも1つの側面に配置された複数のワイヤを含む配線とを備え、
前記本体は、積層された複数の階層部分を含むと共に上面と下面を有する主要部分と、前記主要部分の上面と下面の少なくとも一方に配置されて前記複数のワイヤに電気的に接続された複数の端子とを有し、
前記複数の階層部分の各々は、半導体チップを含み、
前記複数のワイヤは、前記主要部分内の全ての階層部分に共通する用途を有する複数の共通ワイヤと、互いに異なる階層部分によって利用される複数の階層依存ワイヤとを含み、
前記複数の階層部分のうちの少なくとも1つにおいて、前記半導体チップは、前記複数の共通ワイヤに電気的に接続されていると共に、前記複数の階層依存ワイヤのうち、その階層部分が利用する階層依存ワイヤにのみ選択的に、電気的に接続されていることを特徴とする積層チップパッケージ。 - 前記本体は、更に、前記複数の端子を含むインターポーザ層を有することを特徴とする請求項1記載の積層チップパッケージ。
- 前記複数の階層部分の各々は、更に、前記複数の共通ワイヤに電気的に接続された複数の共通電極と、前記複数の階層依存ワイヤのうち、その階層部分が利用する階層依存ワイヤにのみ選択的に、電気的に接続された選択的接続電極とを含み、
前記複数の階層部分のうちの少なくとも1つにおいて、前記複数の共通電極および前記選択的接続電極が前記半導体チップに電気的に接続されることによって、前記半導体チップが前記複数の共通ワイヤおよび前記階層依存ワイヤに電気的に接続されていることを特徴とする請求項1記載の積層チップパッケージ。 - 前記半導体チップは、複数のメモリセルを含むことを特徴とする請求項1記載の積層チップパッケージ。
- 前記半導体チップは、4つの側面を有し、
前記階層部分は、更に、前記半導体チップの4つの側面のうちの少なくとも1つの側面を覆う絶縁部を含み、
前記絶縁部は、前記複数のワイヤが配置された前記本体の前記少なくとも1つの側面に配置された少なくとも1つの端面を有することを特徴とする請求項1記載の積層チップパッケージ。 - 前記複数の階層部分は、少なくとも1つの第1の種類の階層部分と、少なくとも1つの第2の種類の階層部分とを含み、
前記第1の種類の階層部分では、前記半導体チップは、前記複数の共通ワイヤに電気的に接続されていると共に、前記複数の階層依存ワイヤのうち、その階層部分が利用する階層依存ワイヤにのみ選択的に、電気的に接続され、
前記第2の種類の階層部分では、前記半導体チップは、いずれのワイヤにも電気的に接続されていないことを特徴とする請求項1記載の積層チップパッケージ。 - 前記第1の種類の階層部分における前記半導体チップは正常に動作するものであり、前記第2の種類の階層部分における前記半導体チップは正常に動作しないものであることを特徴とする請求項6記載の積層チップパッケージ。
- 前記複数の階層部分の各々は、更に、前記複数の共通ワイヤに電気的に接続された複数の共通電極と、前記複数の階層依存ワイヤのうち、その階層部分が利用する階層依存ワイヤにのみ選択的に、電気的に接続された選択的接続電極とを含み、
前記第1の種類の階層部分では、前記複数の共通電極および前記選択的接続電極が前記半導体チップに電気的に接続されることによって、前記半導体チップが前記複数の共通ワイヤおよび前記階層依存ワイヤに電気的に接続され、
前記第2の種類の階層部分では、前記複数の共通電極および前記選択的接続電極が前記半導体チップに電気的に接続されていないことによって、前記半導体チップが前記複数の共通ワイヤおよび前記階層依存ワイヤに電気的に接続されていないことを特徴とする請求項6記載の積層チップパッケージ。 - 請求項1記載の積層チップパッケージを複数個製造する方法であって、
各々が前記主要部分に含まれる階層部分のいずれかとなる予定の、配列された複数の予備階層部分を含み、後に隣接する予備階層部分の境界位置で切断される複数の基礎構造物を積層して、積層基礎構造物を作製する工程と、
前記積層基礎構造物を用いて、前記積層チップパッケージを複数個作製する工程とを備えたことを特徴とする積層チップパッケージの製造方法。 - 前記複数の階層部分は、少なくとも1つの第1の種類の階層部分と、少なくとも1つの第2の種類の階層部分とを含み、
前記第1の種類の階層部分では、前記半導体チップは、前記複数の共通ワイヤに電気的に接続されていると共に、前記複数の階層依存ワイヤのうち、その階層部分が利用する階層依存ワイヤにのみ選択的に、電気的に接続され、
前記第2の種類の階層部分では、前記半導体チップは、いずれのワイヤにも電気的に接続されていないことを特徴とする請求項9記載の積層チップパッケージの製造方法。 - 前記第1の種類の階層部分における前記半導体チップは正常に動作するものであり、前記第2の種類の階層部分における前記半導体チップは正常に動作しないものであることを特徴とする請求項10記載の積層チップパッケージの製造方法。
- 前記複数の階層部分の各々は、更に、前記複数の共通ワイヤに電気的に接続された複数の共通電極と、前記複数の階層依存ワイヤのうち、その階層部分が利用する階層依存ワイヤにのみ選択的に、電気的に接続された選択的接続電極とを含み、
前記第1の種類の階層部分では、前記複数の共通電極および前記選択的接続電極が前記半導体チップに電気的に接続されることによって、前記半導体チップが前記複数の共通ワイヤおよび前記階層依存ワイヤに電気的に接続され、
前記第2の種類の階層部分では、前記複数の共通電極および前記選択的接続電極が前記半導体チップに電気的に接続されていないことによって、前記半導体チップが前記複数の共通ワイヤおよび前記階層依存ワイヤに電気的に接続されておらず、
前記積層基礎構造物を作製する工程は、各基礎構造物を作製するための一連の工程として、
それぞれ前記半導体チップとなる予定の、配列された複数の半導体チップ予定部を含む基礎構造物前ウェハを作製する工程と、
前記基礎構造物前ウェハに含まれる複数の半導体チップ予定部について、正常に動作する半導体チップ予定部と正常に動作しない半導体チップ予定部とを判別する工程と、
前記基礎構造物前ウェハが前記基礎構造物になるように、正常に動作する半導体チップ予定部では前記複数の共通電極および前記選択的接続電極が前記半導体チップ予定部に電気的に接続され、正常に動作しない半導体チップ予定部では前記複数の共通電極および前記選択的接続電極が前記半導体チップ予定部に電気的に接続されないように、前記複数の共通電極および前記選択的接続電極を形成する工程とを含むことを特徴とする請求項11記載の積層チップパッケージの製造方法。 - 積層され且つ互いに電気的に接続された主パッケージと追加部分とを備えた複合型積層チップパッケージであって、
前記主パッケージは、上面、下面および4つの側面を有する本体と、前記本体の少なくとも1つの側面に配置された複数のワイヤを含む配線とを備え、
前記本体は、積層された複数の階層部分を含むと共に上面と下面を有する主要部分と、前記主要部分の上面と下面の少なくとも一方に配置されて前記複数のワイヤに電気的に接続された複数の端子とを有し、
前記複数の階層部分の各々は、半導体チップを含み、
前記複数のワイヤは、前記主要部分内の全ての階層部分に共通する用途を有する複数の共通ワイヤと、互いに異なる階層部分によって利用される複数の階層依存ワイヤとを含み、
前記複数の階層部分は、少なくとも1つの第1の種類の階層部分と、少なくとも1つの第2の種類の階層部分とを含み、
前記第1の種類の階層部分における前記半導体チップは正常に動作するものであり、前記第1の種類の階層部分では、前記半導体チップは、前記複数の共通ワイヤに電気的に接続されていると共に、前記複数の階層依存ワイヤのうち、その階層部分が利用する階層依存ワイヤにのみ選択的に、電気的に接続され、
前記第2の種類の階層部分における前記半導体チップは正常に動作しないものであり、前記第2の種類の階層部分では、前記半導体チップは、いずれのワイヤにも電気的に接続されておらず、
前記追加部分は、
少なくとも1つの追加半導体チップと、
前記少なくとも1つの追加半導体チップが前記少なくとも1つの第2の種類の階層部分における半導体チップの代替となるように、前記主パッケージにおける前記複数の端子と前記少なくとも1つの追加半導体チップとの電気的接続関係を規定する追加部分配線とを備えたことを特徴とする複合型積層チップパッケージ。 - 前記本体は、更に、前記複数の端子を含むインターポーザ層を有することを特徴とする請求項13記載の複合型積層チップパッケージ。
- 前記追加部分は、上面、下面および4つの側面を有する追加部分本体を備え、
前記追加部分本体は、前記少なくとも1つの追加半導体チップを含み、
前記追加部分配線は、前記追加部分本体の少なくとも1つの側面に配置された複数の追加部分ワイヤと、前記追加部分本体の上面に配置されて前記複数の追加部分ワイヤに電気的に接続された複数の第1の追加部分端子と、前記追加部分本体の下面に配置されて前記複数の追加部分ワイヤに電気的に接続された複数の第2の追加部分端子とを含むことを特徴とする請求項13記載の複合型積層チップパッケージ。 - 前記複数の階層部分の各々は、更に、前記複数の共通ワイヤに電気的に接続された複数の共通電極と、前記複数の階層依存ワイヤのうち、その階層部分が利用する階層依存ワイヤにのみ選択的に、電気的に接続された選択的接続電極とを含み、
前記第1の種類の階層部分では、前記複数の共通電極および前記選択的接続電極が前記半導体チップに電気的に接続されることによって、前記半導体チップが前記複数の共通ワイヤおよび前記階層依存ワイヤに電気的に接続され、
前記第2の種類の階層部分では、前記複数の共通電極および前記選択的接続電極が前記半導体チップに電気的に接続されていないことによって、前記半導体チップが前記複数の共通ワイヤおよび前記階層依存ワイヤに電気的に接続されていないことを特徴とする請求項13記載の複合型積層チップパッケージ。 - 前記階層部分内の半導体チップおよび前記追加半導体チップは、それぞれ、複数のメモリセルを含むことを特徴とする請求項13記載の複合型積層チップパッケージ。
- 前記階層部分内の半導体チップは、4つの側面を有し、
前記階層部分は、更に、前記半導体チップの4つの側面のうちの少なくとも1つの側面を覆う絶縁部を含み、
前記絶縁部は、前記複数のワイヤが配置された前記本体の前記少なくとも1つの側面に配置された少なくとも1つの端面を有することを特徴とする請求項13記載の複合型積層チップパッケージ。 - 請求項13記載の複合型積層チップパッケージを製造する方法であって、
前記主パッケージを作製する工程と、
前記追加部分を作製する工程と、
前記主パッケージと追加部分とを積層し且つ互いに電気的に接続する工程と
を備えたことを特徴とする複合型積層チップパッケージの製造方法。
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