JP2011522350A - ハイブリッドメモリ管理 - Google Patents
ハイブリッドメモリ管理 Download PDFInfo
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- JP2011522350A JP2011522350A JP2011511797A JP2011511797A JP2011522350A JP 2011522350 A JP2011522350 A JP 2011522350A JP 2011511797 A JP2011511797 A JP 2011511797A JP 2011511797 A JP2011511797 A JP 2011511797A JP 2011522350 A JP2011522350 A JP 2011522350A
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- memory
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- memory device
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
- G06F12/023—Free address space management
- G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
- G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/10—Providing a specific technical effect
- G06F2212/1016—Performance improvement
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/10—Providing a specific technical effect
- G06F2212/1032—Reliability improvement, data loss prevention, degraded operation etc
- G06F2212/1036—Life time enhancement
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/72—Details relating to flash memory management
- G06F2212/7201—Logical to physical mapping or translation of blocks or pages
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/72—Details relating to flash memory management
- G06F2212/7211—Wear leveling
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/349—Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
- G11C2211/564—Miscellaneous aspects
- G11C2211/5641—Multilevel memory having cells with different number of storage levels
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
- Static Random-Access Memory (AREA)
- Memory System (AREA)
- Read Only Memory (AREA)
Abstract
Description
本開示の種々の実施形態は、SLCおよびMLCメモリの両方を有するハイブリッドメモリデバイスに格納されている論理ブロックアドレスの追跡された使用に基づいて、論理ブロックアドレスを管理する方法を示す。さらに、複数の論理ブロックアドレス管理動作を実行するために構成された装置が開示され、ハイブリッドメモリデバイスに格納される論理ブロックアドレスの追跡された使用に応じて動作が実行される。
Claims (20)
- 各メモリセルが第1の密度を有する、第1のメモリセルアレイと、各メモリセルが第2の密度を有する、第2のメモリセルアレイと、を備えるメモリデバイスに格納されるデータを管理するための方法であって、前記方法は、
前記メモリデバイスの論理アドレスに関連付けられた使用を決定することと、
前記使用に少なくとも部分的に基づいて、前記第1のメモリセルアレイおよび前記第2のメモリセルアレイのうちの1つに、前記論理アドレスに関連付けられたデータを格納することと、を含む、方法。 - 前記使用は、前記論理アドレスに対して実行された書き込み動作の回数を含む、請求項1に記載の方法。
- 前記第1のメモリアレイは、第1のメモリセル当たりのビット数を格納するように構成されるMLCメモリセルを備え、前記第2のメモリアレイは、第2のメモリセル当たりのビット数を格納するように構成されるMLCメモリセルを備え、前記第2の数は、前記第1の数よりも大きい、請求項1に記載の方法。
- 前記メモリデバイスの使用テーブルに、前記メモリデバイスの前記論理アドレスと関連付けられた前記使用を格納することをさらに含む、請求項1に記載の方法。
- 前記論理アドレスに関連付けられた前記使用を維持することをさらに含み、前記論理アドレスに関連付けられた前記使用を維持することは、前記論理アドレスのために実行される書き込み動作に応じて、前記使用テーブルを更新することを含む、請求項4に記載の方法。
- 前記使用は、前記論理アドレスに対して実行される書き込み動作の最も最近の発生に対応するタイムスタンプを含む、請求項4に記載の方法。
- 前記データを格納することは、前記論理アドレスを、前記データが格納される前記第1のメモリアレイおよび前記第2のメモリアレイのうちの1つにおける物理的位置に関連付けることをさらに含む、請求項1に記載の方法。
- 前記使用を決定することは、将来の使用を予測することを含む、請求項1に記載の方法。
- 前記データを、最初に、前記第1のメモリアレイおよび前記第2のメモリアレイのうちの1つに格納することをさらに含む、請求項1に記載の方法。
- 前記論理アドレスに関連付けられた使用に少なくとも部分的に基づいて、前記第2のメモリアレイに格納されるデータを、前記第1のメモリアレイに移動させることをさらに含む、請求項1に記載の方法。
- 前記データの前記使用は、前記メモリデバイスの起動後の特定の時間枠中に、前記データがアクセスされるかどうかに少なくとも部分的に基づく、請求項1に記載の方法。
- 前記論理アドレスに関連付けられた使用を決定することは、論理アドレスに関連付けられた使用を決定することであって、前記使用は、メモリの論理位置に関連付けられたデータの決定された特性に少なくとも部分的に応じて、かつ、前記特性に少なくとも部分的に基づいて決定される、ことと、前記データを、前記第1のメモリセルアレイおよび前記第2のメモリセルアレイのうちの1つに格納することとをさらに含む、請求項1に記載の方法。
- 前記データの前記特性は、前記データの使用の頻度である、請求項12に記載の方法。
- 各メモリセルが第1の密度を有する、第1のメモリセルアレイと、
各メモリセルが第2の密度を有する、第2のメモリセルアレイと、
制御回路であって、前記制御回路は、メモリデバイスの論理アドレスの使用データを決定し、かつ、前記使用に少なくとも部分的に基づいて、前記第1のメモリセルアレイおよび前記第2のメモリセルアレイのうちの1つに、前記論理アドレスに関連付けられたデータを格納するように構成される、制御回路と、を備える、メモリデバイス。 - 前記使用データは、前記論理アドレスで実行された書き込み動作の回数を含む、請求項14に記載のメモリデバイス。
- 前記制御回路は、前記第1および前記第2のメモリセルアレイで磨耗レベル分け動作を実行するようにさらに構成される、請求項14に記載のメモリデバイス。
- 前記使用データは、前記論理アドレスで最も最近の書き込み動作が実行されてから経過した時間を前記使用データから決定できるように、データを含む、請求項14に記載のメモリデバイス。
- 前記制御回路は、前記第1のメモリセルアレイまたは前記第2のメモリセルアレイ上の書き込み動作を選択的に実行し、各論理アドレスで実行される書き込み動作の回数に少なくとも部分的に基づいて、前記論理アドレスを物理的格納位置に割り当て、書き込み動作の前記回数が閾値を超える場合に、前記論理アドレスを前記第1のメモリセルアレイに再び割り当てるように、さらに構成される、請求項14に記載のメモリデバイス。
- 前記制御回路は、前記メモリデバイスの前記制御回路に連結されるホストからの受信コマンドに少なくとも部分的に応じて、前記第1のメモリセルアレイまたは前記第2のメモリセルアレイにデータを書き込むように、さらに構成される、請求項14に記載のメモリデバイス。
- 前記制御回路は、それの上で実行された書き込み動作の回数が最も少ない論理アドレスに関連付けられたデータを、前記第2のメモリセルアレイに移動させることにより、または、特定の期間よりも長くそれに書き込み動作を実行していない論理アドレスに関連付けられたデータを、前記第2のメモリセルアレイに移動させることにより、前記第2のメモリセルアレイの位置が利用可能である場合に、前記第1のメモリセルアレイ内の少なくとも特定の数のスペアの位置を維持するように、さらに構成される、請求項14に記載のメモリデバイス。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/127,945 US8060719B2 (en) | 2008-05-28 | 2008-05-28 | Hybrid memory management |
US12/127,945 | 2008-05-28 | ||
PCT/US2009/045386 WO2009155022A2 (en) | 2008-05-28 | 2009-05-28 | Hybrid memory management |
Related Child Applications (1)
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JP2014022399A Division JP2014116031A (ja) | 2008-05-28 | 2014-02-07 | メモリデバイスを備えた電子システム |
Publications (2)
Publication Number | Publication Date |
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JP2011522350A true JP2011522350A (ja) | 2011-07-28 |
JP5728672B2 JP5728672B2 (ja) | 2015-06-03 |
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ID=41381226
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
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JP2011511797A Expired - Fee Related JP5728672B2 (ja) | 2008-05-28 | 2009-05-28 | ハイブリッドメモリ管理 |
JP2014022399A Pending JP2014116031A (ja) | 2008-05-28 | 2014-02-07 | メモリデバイスを備えた電子システム |
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JP2014022399A Pending JP2014116031A (ja) | 2008-05-28 | 2014-02-07 | メモリデバイスを備えた電子システム |
Country Status (6)
Country | Link |
---|---|
US (4) | US8060719B2 (ja) |
EP (1) | EP2291746B1 (ja) |
JP (2) | JP5728672B2 (ja) |
KR (1) | KR101283711B1 (ja) |
CN (1) | CN102047230A (ja) |
WO (1) | WO2009155022A2 (ja) |
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WO2016088234A1 (ja) * | 2014-12-04 | 2016-06-09 | 株式会社 東芝 | 異なる特性の不揮発性半導体メモリの寿命を長くするストレージ装置 |
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US9390004B2 (en) | 2016-07-12 |
EP2291746A2 (en) | 2011-03-09 |
US8751733B2 (en) | 2014-06-10 |
US20090300269A1 (en) | 2009-12-03 |
US8060719B2 (en) | 2011-11-15 |
US20120059992A1 (en) | 2012-03-08 |
EP2291746A4 (en) | 2012-10-24 |
WO2009155022A2 (en) | 2009-12-23 |
JP2014116031A (ja) | 2014-06-26 |
US20130073807A1 (en) | 2013-03-21 |
EP2291746B1 (en) | 2014-10-29 |
WO2009155022A3 (en) | 2010-03-04 |
CN102047230A (zh) | 2011-05-04 |
US8296510B2 (en) | 2012-10-23 |
KR101283711B1 (ko) | 2013-07-08 |
KR20110015023A (ko) | 2011-02-14 |
US20140281177A1 (en) | 2014-09-18 |
JP5728672B2 (ja) | 2015-06-03 |
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