JP2011243790A - 配線方法、並びに、表面に配線が設けられた構造物、半導体装置、配線基板、メモリカード、電気デバイス、モジュール及び多層回路基板 - Google Patents
配線方法、並びに、表面に配線が設けられた構造物、半導体装置、配線基板、メモリカード、電気デバイス、モジュール及び多層回路基板 Download PDFInfo
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Images
Classifications
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- H—ELECTRICITY
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/18—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material
- H05K3/181—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material by electroless plating
- H05K3/182—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material by electroless plating characterised by the patterning method
- H05K3/184—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material by electroless plating characterised by the patterning method using masks
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- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C18/00—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating
- C23C18/16—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating by reduction or substitution, e.g. electroless plating
- C23C18/1601—Process or apparatus
- C23C18/1603—Process or apparatus coating on selected surface areas
- C23C18/1607—Process or apparatus coating on selected surface areas by direct patterning
- C23C18/1608—Process or apparatus coating on selected surface areas by direct patterning from pretreatment step, i.e. selective pre-treatment
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- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C18/00—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating
- C23C18/16—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating by reduction or substitution, e.g. electroless plating
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- C23C18/1646—Characteristics of the product obtained
- C23C18/165—Multilayered product
- C23C18/1653—Two or more layers with at least one layer obtained by electroless plating and one layer obtained by electroplating
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- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C18/00—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating
- C23C18/16—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating by reduction or substitution, e.g. electroless plating
- C23C18/18—Pretreatment of the material to be coated
- C23C18/1851—Pretreatment of the material to be coated of surfaces of non-metallic or semiconducting in organic material
- C23C18/1872—Pretreatment of the material to be coated of surfaces of non-metallic or semiconducting in organic material by chemical pretreatment
- C23C18/1886—Multistep pretreatment
- C23C18/1893—Multistep pretreatment with use of organic or inorganic compounds other than metals, first
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- C—CHEMISTRY; METALLURGY
- C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
- C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- C25D7/00—Electroplating characterised by the article coated
- C25D7/06—Wires; Strips; Foils
- C25D7/0607—Wires
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- H—ELECTRICITY
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
- H01L21/4828—Etching
- H01L21/4832—Etching a temporary substrate after encapsulation process to form leads
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- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
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- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
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- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L24/25—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of a plurality of high density interconnect connectors
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- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
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- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
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- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
- H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
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- H—ELECTRICITY
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- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
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- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68359—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during manufacture of interconnect decals or build up layers
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Abstract
【解決手段】複数の接続端子101a,102aが露出する半導体装置1の表面に絶縁層103を形成し、絶縁層の表面に樹脂被膜104を形成し、樹脂被膜の表面側から樹脂被膜の厚みと同じ又は厚みを超える深さの溝105を接続対象の接続端子の近傍を通過するように形成すると共に、その近傍通過部分から接続対象の接続端子に到達する連通孔106,107を形成し、溝及び連通孔の表面にメッキ触媒又はその前駆体を被着させ、樹脂被膜を溶解又は膨潤させることにより除去し、無電解メッキを行うことによりメッキ触媒又はメッキ触媒前駆体から形成されるメッキ触媒が残留する部分のみにメッキ膜を形成することにより、絶縁層の表面に位置する本体部と、この本体部から分岐して絶縁層の内部に延び、接続対象の接続端子に到達する分岐部とを有する配線108を設ける。
【選択図】図1
Description
図1及び図2を参照し、本発明の第1の実施形態に係る配線方法を説明する。図中、符号1は複数の被接続部が露出する構造物、符号10は半導体装置、符号100は封止樹脂で封止された半導体装置、符号101は絶縁基材、符号101aは絶縁基材の接続端子(被接続部)、符号102は半導体チップ、符号102aは半導体チップの接続端子(被接続部)、符号103は絶縁層、符号104は樹脂被膜、符号105は溝、符号106,107は連通孔、符号108は配線、符号108aは配線本体部、符号108bは配線分岐部、符号108xはメッキ触媒、符号109は封止樹脂である。
第1実施形態に係る配線方法においては、まず、図1(A)に示すように、絶縁基材101に半導体チップ102が搭載された構造物1を準備する。半導体チップ102としては、例えば、IC、LSI、VLSI、LEDチップ等である。絶縁基材101の表面には複数の接続端子101aが設けられ、半導体チップ102の表面には複数の接続端子102aが設けられている。これらの接続端子101a,102aは構造物1の表面に露出している。
(絶縁基材)
絶縁基材101としては、従来から半導体チップの実装に用いられているような各種有機基材や無機基材が特に限定なく用いられ得る。有機基材の具体例としては、エポキシ樹脂、アクリル樹脂、ポリカーボネート樹脂、ポリイミド樹脂、ポリフェニレンスルフィド樹脂、ポリフェニレンエーテル樹脂、シアネート樹脂、ベンゾオキサジン樹脂、ビスマレイミド樹脂等からなる基材が挙げられる。
絶縁層103としては、樹脂等の絶縁性有機材料や、シリカ(SiO2)等をはじめとするセラミックス等の絶縁性無機材料等が挙げられる。その他、絶縁基材101を構成する材料と同様の材料でもよい。
樹脂被膜104の形成方法は、図1(C)に示したように、少なくとも、絶縁層103の表面に樹脂被膜104が形成されるような方法であれば、特に限定されない。具体的には、例えば、絶縁層103の全面に、樹脂被膜104を形成し得る液状材料を塗布した後、乾燥させる方法や、予め支持基材に前記液状材料を塗布した後、乾燥することにより形成された被膜を絶縁層103の表面に転写する方法、あるいは貼り合せる方法等が挙げられる。なお、液状材料を塗布する方法としては、特に限定されない。具体的には、例えば、従来から知られたスピンコート法やバーコータ法、ディッピング法やスプレー法等が挙げられる。
メッキ触媒108xは、メッキ処理工程において無電解メッキ膜を形成したい部分のみに無電解メッキ膜を形成するために予め付与される触媒である。メッキ触媒108xとしては、無電解メッキ用の触媒として従来用いられるものであれば、特に限定なく用いられ得る。また、メッキ触媒108xに代えて、メッキ触媒の前駆体を被着させ、樹脂被膜104の除去後にメッキ触媒を生成させてもよい。メッキ触媒108xの具体例としては、例えば、金属パラジウム(Pd)、白金(Pt)、銀(Ag)等が挙げられる。
メッキ処理工程における無電解メッキの方法としては、メッキ触媒108xが被着された構造物1を、無電解メッキ液の槽に浸漬して、メッキ触媒108xが被着された部分のみに無電解メッキ膜を析出させるような方法が用いられ得る。
図3を参照し、本発明の第2の実施形態に係る配線方法を説明する。図中、符号2は複数の被接続部が露出する構造物、符号20は半導体装置、符号200は封止樹脂で封止された半導体装置、符号201は絶縁基材、符号201aは絶縁基材の接続端子(被接続部)、符号202は半導体チップ、符号202aは半導体チップの接続端子(被接続部)、符号203は絶縁層、符号204は樹脂被膜、符号205は溝、符号206,207は連通孔、符号208は配線、符号208aは配線本体部、符号208bは配線分岐部、符号209は封止樹脂である。
図4を参照し、本発明の第3の実施形態に係る配線方法を説明する。図中、符号3は複数の被接続部が露出する構造物、符号30は表面に配線が設けられた構造物、符号300は封止樹脂で封止され、表面に配線が設けられた構造物、符号301は銅板、符号301aは接続端子(被接続部)、符号302はレジスト、符号303はニッケルメッキを介した金メッキ膜、符号304はキャビティ、符号305は半導体チップ、符号305aは半導体チップの接続端子(被接続部)、符号306は絶縁層、符号307は樹脂被膜、符号308は配線、符号308aは配線本体部、符号308bは配線分岐部、符号309は封止樹脂である。
図5を参照し、本発明の第4の実施形態に係る配線方法を説明する。ただし、第3実施形態と同じ又は相当する構成要素には第3実施形態と同じ符号を用い、第3実施形態と異なる部分のみ説明する。図中、符号302aは支持板である。
図6を参照し、本発明の第5の実施形態に係る半導体装置を説明する。図中、符号400は封止樹脂409で封止された半導体装置、符号401aは絶縁基材の接続端子(被接続部)、符号405は半導体チップ、符号405aは半導体チップの接続端子(被接続部)、符号406は絶縁層、符号408は配線、符号409は封止樹脂である。なお、封止樹脂409は、取り除かれたものとして描かれていない。また、配線408は、一部のみが描かれている。
図7を参照し、本発明の第6の実施形態に係る半導体装置を説明する。図中、符号500は封止樹脂で封止された半導体装置、符号501aは絶縁基材の接続端子(被接続部)、符号505は半導体チップ、符号505aは半導体チップの接続端子(被接続部)、符号506は絶縁層、符号508は配線、符号508aは配線本体部、符号508bは配線分岐部である。なお、封止樹脂は、取り除かれたものとして描かれていない。また、配線508は、一部のみが描かれている。
図8を参照し、本発明の第7の実施形態に係る配線方法を説明する。図中、符号6は複数の被接続部が露出する構造物、符号60a,60bは半導体装置、符号600は封止樹脂で封止された半導体装置、符号601は絶縁基材、符号601aは絶縁基材の接続端子(被接続部)、符号602は半導体チップ、符号602aは半導体チップの接続端子(被接続部)、符号603,613は絶縁層、符号604,614は樹脂被膜、符号608,618は配線、符号608a,618aは配線本体部、符号608b,618bは配線分岐部、符号609は封止樹脂である。
図9を参照し、本発明の第8の実施形態に係る配線基板を説明する。図中、符号700は配線基板、符号701はプリント配線板、符号701aはプリント配線板の接続端子(被接続部)、符号702は半導体装置、符号702aは半導体装置の接続端子(被接続部)、符号703は絶縁層、符号708は配線、符号708aは配線本体部、符号708bは配線分岐部である。なお、配線708は、一部のみが描かれている。
図10を参照し、本発明の第9の実施形態に係るメモリカードを説明する。図中、符号800はメモリカード、符号801は支持体、符号801aは支持体の接続端子(被接続部)、符号802はメモリパッケージ、符号802aはメモリパッケージの接続端子(被接続部)、符号803は絶縁層、符号808は配線、符号808aは配線本体部、符号808bは配線分岐部である。なお、配線808は、一部のみが描かれている。
図11を参照し、本発明の第10の実施形態に係る電気デバイスを説明する。図中、符号900は電気デバイス、符号901は絶縁基材、符号901aは絶縁基材の接続端子(被接続部)、符号902は受動素子、符号902aは受動素子の接続端子(被接続部)、符号903は絶縁層、符号908は配線、符号908aは配線本体部、符号908bは配線分岐部である。なお、配線908は、一部のみが描かれている。
図12を参照し、本発明の第11の実施形態に係るモジュールを説明する。図中、符号1000はモジュール、符号1001は支持体、符号1001aは支持体の接続端子(被接続部)、符号1002は電気デバイス、符号1002aは電気デバイスの接続端子(被接続部)、符号1003は絶縁層、符号1008は配線、符号1008aは配線本体部、符号1008bは配線分岐部である。なお、配線1008は、一部のみが描かれている。
図13を参照し、本発明の第12の実施形態に係る多層回路基板を説明する。図中、符号1100は多層回路基板、符号1101は最下層の回路基板、符号1101aは最下層の回路基板の接続端子(被接続部)、符号1102は第2層目以上の回路基板、符号1102aは第2層目以上の回路基板の接続端子(被接続部)、符号1102bは第2層目以上の回路基板の内部回路、符号1103は絶縁層、符号1108は配線、符号1108aは配線本体部、符号1108bは配線分岐部である。なお、配線1108は、一部のみが描かれている。
図14を参照し、本発明の第13の実施形態に係る半導体装置を説明する。図中、符号1200は半導体装置(スタックチップパッケージ)、符号1201は絶縁基材、符号1201aは絶縁基材の接続端子(被接続部)、符号1202は半導体チップ、符号1202aは半導体チップの接続端子(被接続部)、符号1203は絶縁層、符号1208は配線、符号1208aは配線本体部、符号1208bは配線分岐部、符号1209は封止樹脂である。なお、配線1208は、一部のみが描かれている。
101 絶縁基材
101a,102a 被接続部(接続端子)
102 半導体チップ
103 絶縁層
104 樹脂被膜
108 配線
108a 配線本体部
108b 配線分岐部
Claims (14)
- 構造物の表面に露出する複数の被接続部を相互に配線で接続するための配線方法であって、
複数の被接続部が露出する構造物の表面に絶縁層を形成する絶縁層形成工程、及び、
絶縁層の表面に位置する本体部と、この本体部から分岐して絶縁層の内部に延び、接続対象の被接続部に到達する分岐部とを有する配線を設ける配線形成工程、
を備えることを特徴とする配線方法。 - 配線形成工程は、
絶縁層の表面に樹脂被膜を形成する樹脂被膜形成工程、
樹脂被膜の表面側から樹脂被膜の厚みと同じ又は厚みを超える深さの溝を接続対象の被接続部の近傍を通過するように形成すると共に、その近傍通過部分から接続対象の被接続部に到達する連通孔を形成する溝孔形成工程、
前記溝及び前記連通孔の表面にメッキ触媒又はその前駆体を被着させる触媒被着工程、
前記樹脂被膜を溶解又は膨潤させることにより除去する樹脂被膜除去工程、及び、
無電解メッキを行うことにより前記メッキ触媒又は前記メッキ触媒前駆体から形成されるメッキ触媒が残留する部分のみにメッキ膜を形成するメッキ処理工程、
を含むことを特徴とする請求項1に記載の配線方法。 - 配線形成工程は、
メッキ処理工程の後、電解メッキを行うことによりメッキ膜を厚膜化する電解メッキ工程をさらに含むことを特徴とする請求項2に記載の配線方法。 - 樹脂被膜は蛍光性物質を含有し、
配線形成工程は、
樹脂被膜除去工程の後、メッキ処理工程の前に、前記蛍光性物質からの発光を用いて樹脂被膜の除去不良を検査する検査工程をさらに含むことを特徴とする請求項2又は3に記載の配線方法。 - 配線形成工程の後、
配線の本体部が露出する絶縁層の表面にさらに絶縁層を積層する絶縁層積層工程、及び、
積層した絶縁層の表面に位置する本体部と、この本体部から分岐して絶縁層の内部に延び、接続対象の被接続部に到達する分岐部とを有する配線を設ける追加配線形成工程、
を1回以上繰り返すことを特徴とする請求項1から4のいずれか1項に記載の配線方法。 - 複数の被接続部が露出する構造物の表面に絶縁層が形成され、
この絶縁層の表面に配線の本体部が設けられ、
この配線本体部から配線の分岐部が分岐し、
この配線分岐部が絶縁層の内部に延び、接続対象の被接続部に到達していることを特徴とする表面に配線が設けられた構造物。 - 配線本体部が露出する絶縁層の表面に絶縁層が積層され、
この積層された絶縁層の表面に配線の本体部が設けられ、
この配線本体部から配線の分岐部が分岐し、
この配線分岐部が絶縁層の内部に延び、接続対象の被接続部に到達している構成が、
1段以上備えられていることを特徴とする請求項6に記載の表面に配線が設けられた構造物。 - 絶縁基材に半導体チップが搭載され、絶縁基材に設けられた接続端子及び半導体チップに設けられた接続端子が露出する構造物の表面に絶縁層が形成され、
この絶縁層の表面に配線の本体部が設けられ、
この配線本体部から配線の分岐部が分岐し、
この配線分岐部が絶縁層の内部に延び、絶縁基材の接続端子及び/又は半導体チップの接続端子に到達していることを特徴とする半導体装置。 - プリント配線板に半導体装置が実装され、プリント配線板に設けられた接続端子及び半導体装置に設けられた接続端子が露出する構造物の表面に絶縁層が形成され、
この絶縁層の表面に配線の本体部が設けられ、
この配線本体部から配線の分岐部が分岐し、
この配線分岐部が絶縁層の内部に延び、プリント配線板の接続端子及び/又は半導体装置の接続端子に到達していることを特徴とする配線基板。 - 支持体にメモリパッケージが取り付けられ、支持体に設けられた接続端子及びメモリパッケージに設けられた接続端子が露出する構造物の表面に絶縁層が形成され、
この絶縁層の表面に配線の本体部が設けられ、
この配線本体部から配線の分岐部が分岐し、
この配線分岐部が絶縁層の内部に延び、支持体の接続端子及び/又はメモリパッケージの接続端子に到達していることを特徴とするメモリカード。 - 絶縁基材に受動素子が搭載され、絶縁基材に設けられた接続端子及び受動素子に設けられた接続端子が露出する構造物の表面に絶縁層が形成され、
この絶縁層の表面に配線の本体部が設けられ、
この配線本体部から配線の分岐部が分岐し、
この配線分岐部が絶縁層の内部に延び、絶縁基材の接続端子及び/又は受動素子の接続端子に到達していることを特徴とする電気デバイス。 - 支持体に電気デバイスが取り付けられ、支持体に設けられた接続端子及び電気デバイスに設けられた接続端子が露出する構造物の表面に絶縁層が形成され、
この絶縁層の表面に配線の本体部が設けられ、
この配線本体部から配線の分岐部が分岐し、
この配線分岐部が絶縁層の内部に延び、支持体の接続端子及び/又は電気デバイスの接続端子に到達していることを特徴とするモジュール。 - 複数の回路基板が多段に積み重ねられた状態で結合され、回路基板に設けられた接続端子が露出する構造物の表面に絶縁層が形成され、
この絶縁層の表面に配線の本体部が設けられ、
この配線本体部から配線の分岐部が分岐し、
この配線分岐部が絶縁層の内部に延び、相互に異なる回路基板の接続端子に到達しており、
前記回路基板の接続端子は、回路基板の内部回路の端部であることを特長とする多層回路基板。 - 絶縁基材に複数の半導体チップが多段に積み重ねられた状態で搭載され、半導体チップに設けられた接続端子が露出する構造物の表面に絶縁層が形成され、
この絶縁層の表面に配線の本体部が設けられ、
この配線本体部から配線の分岐部が分岐し、
この配線分岐部が絶縁層の内部に延び、相互に異なる半導体チップの接続端子に到達していることを特徴とする半導体装置。
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JP2010115250A JP2011243790A (ja) | 2010-05-19 | 2010-05-19 | 配線方法、並びに、表面に配線が設けられた構造物、半導体装置、配線基板、メモリカード、電気デバイス、モジュール及び多層回路基板 |
TW100116399A TWI445477B (zh) | 2010-05-19 | 2011-05-10 | 配線方法、表面設有配線之構造物、半導體裝置、配線基板、記憶卡、電氣元件、模組及多層電路基板 |
US13/698,975 US9082635B2 (en) | 2010-05-19 | 2011-05-11 | Wiring method, structure having wiring provided on surface, semiconductor device, wiring board, memory card, electric device, module and multilayer circuit board |
CN201180024358.2A CN102893711B (zh) | 2010-05-19 | 2011-05-11 | 配线方法、以及在表面设有配线的构造物、半导体装置、配线基板、存储卡、电气器件、模块及多层电路基板 |
EP11783233A EP2574156A1 (en) | 2010-05-19 | 2011-05-11 | Wiring method, structure having wiring provided on surface, semiconductor device, wiring board, memory card, electric device, module, and multilayer circuit board |
PCT/JP2011/002628 WO2011145294A1 (ja) | 2010-05-19 | 2011-05-11 | 配線方法、並びに、表面に配線が設けられた構造物、半導体装置、配線基板、メモリカード、電気デバイス、モジュール及び多層回路基板 |
US14/733,308 US20150271924A1 (en) | 2010-05-19 | 2015-06-08 | Wiring method, structure having wiring provided on surface, semiconductor device, wiring board, memory card, electric device, module, and multilayer circuit board |
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US20150271924A1 (en) | 2015-09-24 |
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