JP2011211194A - 配線板及びその製造方法 - Google Patents
配線板及びその製造方法 Download PDFInfo
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Abstract
【解決手段】 CPU901の信号用パッド901b、メモリ902の信号用パッド902bを一辺側に配置し、それら信号パッドを配置した辺側を対向させた状態でビルドアップ多層配線板11に実装させ、耐熱基板80の信号線83を介してCPUの信号用パッド901bとメモリの信号用パッド902bとを接続する。耐熱基板80の短い信号線43によりCPU−メモリ間を接続することで、CPU−メモリ間で大容量、高速伝送を可能にできる。
【選択図】 図8
Description
前記貫通孔に収容されている第2基板と、
前記貫通孔に充填された充填剤とを備えるプリント配線板であって、
前記第2基板は、前記第1基板に実装される前記複数個のチップの端子を固定するパッドと、該パッドを連結させ複数個のチップの端子を電気的に接続する信号線とを備えることを技術的特徴とする。
CPU、メモリの信号用パッドを一辺側に配置し、それら信号パッドを配置した辺側を対向させた状態で第1基板に実装させ、第2基板の信号線を介してCPUの信号用パッドとメモリの信号用パッドとを接続する。第2基板の短い信号線によりCPU−メモリ間を接続することで、CPU−メモリ間で大容量、高速伝送を可能にできる。
また、テーパ部を設けることで、充填材とビルドアップ層との接触面積が大きくなり、半導体素子との熱膨張係数の差により生じる応力を緩和でき、ビルドアップ層へ生じるクラックが抑制されると推測される。
次に、本発明の第1実施形態に係る製造方法により製造されるプリント配線板10の構成について、図7、図8、図9、図10を参照して説明する。図7は、プリント配線板10の断面図を示している。図8は、図7に示すプリント配線板10にCPUチップ901、メモリチップ902を取り付けた半導体装置を示している。図9は、図7に示すプリント配線板10の平面図を示している。図10は、実装されるCPUチップ901、メモリチップ902の底面図を示す。
図9の平面図中に示すように、インターポーザ80のバンプ82A、82Bは、ピッチP2(約40μm)に配置されている。また、ビルドアップ多層配線板の半田バンプ78Sは、ピッチP1(約130μm)に配置されている。そして、耐熱基板80の信号線43のL/Sは、1/1μm〜3/3μmに設定されている。第1実施形態では、インターポーザ80はシリコンから成り、信号線83及びバンプ82B、バンプ82Aは、半導体製造工程を用いることでファインに製造されている。耐熱基板81を形成する材料としては、熱膨張係数2〜10ppmのシリコン、セラミック、ガラスを用いることができる。
(1)厚さ0.2〜0.8mmのガラスエポキシ樹脂またはBT(ビスマレイミドトリアジン)樹脂からなる絶縁性基板30の両面に5〜250μmの銅箔32がラミネートされている銅張積層板30Aを出発材料とした(図1(A))。まず、この銅張積層板をドリル削孔して通孔33を穿設し(図1(B))、無電解めっき処理および電解めっき処理を施し、スルーホール導体36を形成する(図1(C))。その後、スルーホール導体36を形成した基板30を水洗いし、乾燥した後、黒化処理、および、還元処理を行い、スルーホール36の側壁導体層及び表面に粗化面を形成する(図示せず)。
さらに、粗面化処理(粗化深さ3μm)した該基板の表面に、パラジウム触媒を付与することにより、層間樹脂絶縁層の表面およびバイアホール用開口の内壁面に触媒核を付着させた。
また、テーパ部を設けることで、充填樹脂とビルドアップ層(層間樹脂絶縁層)との接触面積が大きくなり、半導体素子との熱膨張係数の差により生じる応力を緩和できる。その結果、ビルドアップ層へ生じるクラックが抑制されると推測される。
第2実施形態のプリント配線板について、第2実施形態に係るプリント配線板の平面図を示す図11を参照して説明する。
第2実施形態のプリント配線板の構成は図7及び図9を参照して上述した第1実施形態と同様である。但し、第1実施形態では、貫通孔31の開口部が矩形になるように角柱形状に形成されたのに対して、第2実施形態では、貫通孔31の開口部が円形になるように円筒形状に形成されている。また、インターポーザ80は、角部が面取りされ、角部で応力が集中しないように構成されている。
11 多層プリント配線板
30 コア基板
36 スルーホール
40 樹脂充填層
50 層間樹脂絶縁層
58 導体回路
60 バイアホール
70 ソルダーレジスト層
78S 半田バンプ
80 耐熱基板
82A、82B バンプ
83 信号線
901 CPUチップ
902 メモリチップ
Claims (13)
- 第1面と第2面とを有し、第1貫通孔を有する第1基板と、
前記第1貫通孔の内部に形成されて表裏を電気的に接続するスルーホール導体と、
前記第1基板の第1面上に形成されていて、層間樹脂絶縁層と第1導体回路とが交互に積層されてなり、最外面に開口する開口部を有するビルドアップ層と、
前記開口部に収容されている第2基板と、
前記第2基板上に形成されている第2導体回路と、
前記開口部内に充填されている充填材と、を有する配線板であって、
前記開口部は、前記ビルドアップ層の最外面に向かいテーパするテーパ部を有する。 - 前記テーパ部はレーザーにより形成されている請求項1の配線板。
- 前記第1導体回路は、複数の半導体素子を実装する第1実装パッドを有する請求項1の配線板。
- 前記第2導体回路は、複数の半導体素子を実装する第2実装パッドを有する請求項1の配線板。
- 前記第2実装パッドのピッチは、前記第1実装パッドのピッチよりも小さい請求項1の配線板。
- 前記第2導体回路は、前記複数の半導体素子の間を接続する信号線である請求項1の配線板。
- 前記第2基板は、熱膨張係数2〜10ppmの材料から形成されている請求項1の配線板。
- 前記第2基板は、シリコン、セラミック、ガラスから選択されるいずれか1種からなる請求項1の配線板。
- 前記第2導体回路のL/Sは、前記第1導体回路のL/Sよりも小さい請求項1のプリント配線板。
- 前記第1導体回路は、電源用又はグランド用の導体である請求項1の配線板。
- 前記ビルドアップ層は受動素子を有する請求項1の配線板。
- 第1面と第2面とを有し、第1貫通孔を有する第1基板を準備することと、
前記第1基板の表裏を電気的に接続するスルーホール導体を形成することと、
前記第1基板の第1面上に、層間樹脂絶縁層と第1導体回路とが交互に積層されてなるビルドアップ層を形成することと、
前記ビルドアップ層の最外面に開口する開口部を形成することと、
前記開口部に、第2基板と該第2基板上に形成された第2導体回路とを有するインターポーザを収容することと、
前記開口部内に充填材を充填することと、を含む配線板の製造方法であって、
前記開口部に、前記ビルドアップ層の最外面に向かいテーパするテーパ部を設ける。 - 前記テーパ部はレーザーにより形成される。
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