JP2011146563A - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 96
- 239000000758 substrate Substances 0.000 claims abstract description 18
- 230000002093 peripheral effect Effects 0.000 claims description 17
- 238000009792 diffusion process Methods 0.000 abstract description 12
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 abstract description 5
- 230000004048 modification Effects 0.000 description 34
- 238000012986 modification Methods 0.000 description 34
- 230000001681 protective effect Effects 0.000 description 20
- 239000000523 sample Substances 0.000 description 15
- 239000000463 material Substances 0.000 description 14
- 230000000694 effects Effects 0.000 description 13
- 238000000034 method Methods 0.000 description 13
- 239000010949 copper Substances 0.000 description 8
- 229910052581 Si3N4 Inorganic materials 0.000 description 5
- 238000005229 chemical vapour deposition Methods 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- 239000000470 constituent Substances 0.000 description 3
- 230000007547 defect Effects 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 238000001459 lithography Methods 0.000 description 3
- 230000003014 reinforcing effect Effects 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 230000002950 deficient Effects 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
- 230000009977 dual effect Effects 0.000 description 2
- 230000006355 external stress Effects 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 230000000717 retained effect Effects 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 230000035882 stress Effects 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- 238000010521 absorption reaction Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 238000005336 cracking Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 230000000704 physical effect Effects 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 150000003377 silicon compounds Chemical class 0.000 description 1
- 238000005728 strengthening Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 230000003313 weakening effect Effects 0.000 description 1
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Abstract
【解決手段】半導体装置は、半導体基板11の上方に形成され、外部との電気的な接続を取る接続部25である電極パッドと、半導体基板と接続部との間に積層された絶縁膜14等にそれぞれ形成され、上層の配線34が接続部と接続された複数の第1配線層及び該第1配線層同士を接続するビア31よりなる積層構造体27と、複数の絶縁膜に積層構造体の周囲を隙間なく囲むように形成され、複数の第2配線層40等及び該第2配線層同士を線状に接続するラインビア41よりなるリング構造体28と、接続部と内部回路とを電気的に接続する引き出し配線32Aとを有している。積層構造体とリング構造体とは複数の第1配線層の少なくとも1つによって互いに接続されており、引き出し配線はリング構造体と接続されている。
【選択図】図4
Description
本発明の第1の実施形態に係る半導体装置について図面を参照しながら説明する。
図5に第1の実施形態の第1変形例に係る半導体装置の断面構成を示す。図5に示すように、本変形例に係る半導体装置の電極パッド構造53は、リング構造体28と接続された積層構造体27から内部回路に引き出される引き出し配線44Aを電源配線とし、且つ電源配線を最上層の第4の絶縁膜21に形成される第6の配線44によって形成している。
図6〜図8は第1の実施形態の第2変形例に係る半導体装置における電極パッド構造を示している。
図9〜図11は第1の実施形態の第3変形例に係る半導体装置における電極パッド構造を示している。
図12及び図13は第1の実施形態の第4変形例に係る半導体装置における電極パッド構造を示している。
図14は第1の実施形態の第5変形例に係る半導体装置における電極パッド構造を示している。
以下、本発明の第2の実施形態に係る半導体装置について図面を参照しながら説明する。
図18〜図20は第2の実施形態の第1変形例に係る半導体装置における電極パッド構造を示している。
12 第1の絶縁膜
13 ライナ膜
14 第2の絶縁膜
17 第3の絶縁膜
21 第4の絶縁膜
21A 第4の絶縁膜
24 第1の保護絶縁膜
25 接続部(電極パッド)
26 第2の保護絶縁膜
27 積層構造体
28 リング構造体
30 第1の配線
31 ビア
32 第2の配線
32A 引き出し配線
33 ビア
34 第3の配線
40 第4の配線
41 ラインビア
42 第5の配線
42A 引き出し配線
43 ラインビア
44 第6の配線
44A 引き出し配線
51 半導体チップ
51a チップ端面
53 パッド電極構造
Claims (12)
- 半導体基板の上方に形成され、外部との電気的な接続を取る接続部である電極パッドと、
前記半導体基板と前記接続部との間に積層された複数の絶縁膜にそれぞれ形成され、上層の配線が前記接続部と接続された複数の第1配線層及び該第1配線層同士を接続するビアよりなる積層構造体と、
前記複数の絶縁膜に前記積層構造体の周囲を隙間なく囲むように形成され、複数の第2配線層及び該第2配線層同士を線状に接続するラインビアよりなるリング構造体と、
前記接続部と内部回路とを電気的に接続する引き出し配線とを備え、
前記積層構造体と前記リング構造体とは、前記複数の第1配線層の少なくとも1つによって互いに接続されており、
前記引き出し配線は、前記リング構造体と接続されていることを特徴とする半導体装置。 - 前記引き出し配線は電源配線であり、且つ、前記複数の第2配線層のうちの上層の配線と接続されていることを特徴とする請求項1に記載の半導体装置。
- 前記複数の第1配線層は、前記内部回路に向かう方向に延びる形状となるように配置された配線を有していることを特徴とする請求項1又は2に記載の半導体装置。
- 前記複数の第1の配線層のうち前記リング構造体と接続される配線は、前記接続部から2層下に配置された配線であることを特徴とする請求項3に記載の半導体装置。
- 前記複数の第1配線層は、前記半導体基板における前記電極パッドから最も近い端面に並行な方向に延びる形状となるように配置された配線を有していることを特徴とする請求項1〜4のいずれか1項に記載の半導体装置。
- 前記複数の第1配線層は、前記内部回路に向かう方向に延びる形状となるように配置された第1の配線と、前記半導体基板における前記電極パッドから最も近い端面に並行な方向に延びる形状となるように配置された第2の配線とを有し、
前記第2の配線は、前記第1の配線よりも下層に設けられていることを特徴とする請求項1又は2に記載の半導体装置。 - 前記複数の第2配線層における上層の配線は、その下層の配線と比べて幅が広いことを特徴とする請求項1〜6のうちいずれかに1項に記載の半導体装置。
- 前記複数の第2配線層における上層の配線は、その外周面が下層の配線の外周面と比べて外側に位置することを特徴とする請求項1〜7のうちいずれかに1項に記載の半導体装置。
- 前記ラインビアは、上層のラインビアと下層のラインビアとからなり、
前記上層のラインビアは、前記下層のラインビアと比べて幅が広いことを特徴とする請求項1〜8のうちいずれかに1項に記載の半導体装置。 - 前記ラインビアは、上層のラインビアと下層のラインビアとからなり、
前記下層のラインビアは、複数本が互いに沿うように形成されていることを特徴とする請求項1〜9のうちいずれかに1項に記載の半導体装置。 - 前記複数の第2配線層における下層の配線は、複数本が互いに沿うように形成されていることを特徴とする請求項1〜10のうちいずれかに1項に記載の半導体装置。
- 前記絶縁膜は、互いに誘電率が異なる複数の絶縁層からなり、
上層の絶縁層の誘電率は、下層の絶縁層の誘電率よりも高いことを特徴とする請求項1〜11のうちいずれかに1項に記載の半導体装置。
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JP2010006732A JP2011146563A (ja) | 2010-01-15 | 2010-01-15 | 半導体装置 |
US12/976,618 US8421236B2 (en) | 2010-01-15 | 2010-12-22 | Semiconductor device |
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Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2013038112A (ja) * | 2011-08-04 | 2013-02-21 | Sony Corp | 半導体装置、半導体装置の製造方法、及び、電子機器 |
JP2013058584A (ja) * | 2011-09-08 | 2013-03-28 | Renesas Electronics Corp | 半導体集積回路装置 |
JP2013149940A (ja) * | 2011-09-27 | 2013-08-01 | Infineon Technologies Ag | 保護リングを備えた半導体構造 |
JP2013197516A (ja) * | 2012-03-22 | 2013-09-30 | Seiko Instruments Inc | 半導体装置 |
US9111763B2 (en) | 2011-07-05 | 2015-08-18 | Sony Corporation | Semiconductor device, fabrication method for a semiconductor device and electronic apparatus |
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