JP2006332533A - 半導体素子及びその製造方法 - Google Patents
半導体素子及びその製造方法 Download PDFInfo
- Publication number
- JP2006332533A JP2006332533A JP2005157538A JP2005157538A JP2006332533A JP 2006332533 A JP2006332533 A JP 2006332533A JP 2005157538 A JP2005157538 A JP 2005157538A JP 2005157538 A JP2005157538 A JP 2005157538A JP 2006332533 A JP2006332533 A JP 2006332533A
- Authority
- JP
- Japan
- Prior art keywords
- frame
- layer
- conductor layer
- semiconductor element
- columnar
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 56
- 238000004519 manufacturing process Methods 0.000 title claims description 9
- 239000004020 conductor Substances 0.000 claims abstract description 67
- 239000011810 insulating material Substances 0.000 claims abstract description 13
- 239000000463 material Substances 0.000 claims description 7
- 239000011159 matrix material Substances 0.000 claims description 5
- 238000005336 cracking Methods 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 102
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 7
- 229910052721 tungsten Inorganic materials 0.000 description 7
- 239000010937 tungsten Substances 0.000 description 7
- 238000000034 method Methods 0.000 description 6
- 229910052782 aluminium Inorganic materials 0.000 description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 5
- 239000000523 sample Substances 0.000 description 5
- 239000013039 cover film Substances 0.000 description 3
- 239000010408 film Substances 0.000 description 3
- 239000011229 interlayer Substances 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000001035 drying Methods 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 229910016909 AlxOy Inorganic materials 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 229910020781 SixOy Inorganic materials 0.000 description 1
- UQZIWOQVLUASCR-UHFFFAOYSA-N alumane;titanium Chemical compound [AlH3].[Ti] UQZIWOQVLUASCR-UHFFFAOYSA-N 0.000 description 1
- 238000004380 ashing Methods 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000012805 post-processing Methods 0.000 description 1
- 230000000644 propagated effect Effects 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
- H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
- H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
- H01L2224/02165—Reinforcing structures
- H01L2224/02166—Collar structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05075—Plural internal layers
- H01L2224/0508—Plural internal layers being stacked
- H01L2224/05085—Plural internal layers being stacked with additional elements, e.g. vias arrays, interposed between the stacked layers
- H01L2224/05089—Disposition of the additional element
- H01L2224/05093—Disposition of the additional element of a plurality of vias
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05075—Plural internal layers
- H01L2224/0508—Plural internal layers being stacked
- H01L2224/05085—Plural internal layers being stacked with additional elements, e.g. vias arrays, interposed between the stacked layers
- H01L2224/05089—Disposition of the additional element
- H01L2224/05093—Disposition of the additional element of a plurality of vias
- H01L2224/05095—Disposition of the additional element of a plurality of vias at the periphery of the internal layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05075—Plural internal layers
- H01L2224/0508—Plural internal layers being stacked
- H01L2224/05085—Plural internal layers being stacked with additional elements, e.g. vias arrays, interposed between the stacked layers
- H01L2224/05089—Disposition of the additional element
- H01L2224/05093—Disposition of the additional element of a plurality of vias
- H01L2224/05096—Uniform arrangement, i.e. array
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/05624—Aluminium [Al] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/85399—Material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01004—Beryllium [Be]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01014—Silicon [Si]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01019—Potassium [K]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01022—Titanium [Ti]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01074—Tungsten [W]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01087—Francium [Fr]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/049—Nitrides composed of metals from groups of the periodic table
- H01L2924/0494—4th Group
- H01L2924/04941—TiN
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Wire Bonding (AREA)
Abstract
【解決手段】 半導体素子は、内部に形成された配線層14と、配線層14と離間して形成され電極の表面面を形成する導電体層18とを有する。互いに近接して配置された複数の柱状部材16が、配線層14と導電体層18との間に延在する。枠状部材44は、複数の柱状部材16とそれらの間に充填された絶縁材料よりなる絶縁層20との周囲を包囲するように、配線層14と導電体層18との間に延在する。
【選択図】 図9
Description
10 半導体基板
12 層間絶縁膜
14 下部配線層
16 導電性プラグ
18 上部導電体層
20 絶縁層
22 カバー膜
40 ボンディングパッド
42 中間導電体層
44 枠状部材
Claims (9)
- 表面に電極を有する半導体素子であって、
半導体素子の内部に形成された配線層と、
該配線層と離間して形成され、該電極の表面を形成する導電体層と、
前記配線層と該導電体層との間に延在し、導電性材料で形成され、互いに近接して配置された複数の柱状部材と、
該複数の柱状部材の間に充填された絶縁材料よりなる絶縁層と、
前記配線層と該導電体層との間に延在し、前記複数の柱状部材と前記絶縁層との周囲を包囲するように枠状に形成された枠状部材と
を有することを特徴とする半導体素子。 - 請求項1記載の半導体素子であって、
前記枠状部材は、前記柱状部材を形成する前記導電性材料により形成されていることを特徴とする半導体素子。 - 請求項1記載の半導体素子であって、
前記枠状部材は、前記絶縁層を形成する前記絶縁材料より高い柔軟性を有する材料で形成されていることを特徴とする半導体素子。 - 請求項1記載の半導体素子であって、
前記枠状部材の外形は前記導電体層の外形に実質的に等しいことを特徴とする半導体素子。 - 請求項1記載の半導体素子であって、
前記柱状部材はマトリクス状に配列されていることを特徴とする半導体素子。 - 請求項1記載の半導体素子であって、
前記配線層と前記導電体層との間に中間導電体層が設けられ、
前記柱状部材は、前記配線層と前記中間導電体層との間に延在する第1の柱状部材と、前記中間導電体層と前記導電体層との間に延在する第2の柱状部材とを含み、
前記枠状部材は、前記配線層と前記中間導電体層との間に延在する第1の枠状部材と、前記中間導電体層と前記導電体層との間に延在する第2の枠状部材とを含むことを特徴とする半導体素子。 - 請求項6記載の半導体素子であって、
前記第1及び第2の枠状部材は、前記第1及び第2の柱状部材を形成する前記導電性材料により形成されていることを特徴とする半導体素子。 - 表面に電極を有する半導体素子の製造方法であって、
半導体素子の内部における配線層の上に、複数の柱状部材と該複数の柱状部材を包囲する枠状部材とを導電性材料により形成し、
該柱状部材の間に絶縁材料を充填して絶縁層を形成し、
前記複数の柱状部材と前記絶縁層と前記枠状部材との上に導電体層を形成することにより、該導電体層の表面を前記電極の表面とする
ことを特徴とする半導体素子の製造方法。 - 請求項8記載の半導体素子の製造方法であって、
前記枠状部材を前記柱状部材と同じ材料で形成することを特徴とする半導体素子の製造方法。
Priority Applications (6)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005157538A JP2006332533A (ja) | 2005-05-30 | 2005-05-30 | 半導体素子及びその製造方法 |
TW094128726A TWI278050B (en) | 2005-05-30 | 2005-08-23 | Semiconductor element and manufacturing method thereof |
US11/208,549 US7298051B2 (en) | 2005-05-30 | 2005-08-23 | Semiconductor element and manufacturing method thereof |
KR1020050083036A KR100666907B1 (ko) | 2005-05-30 | 2005-09-07 | 반도체 소자 및 그 제조 방법 |
CN200510099898A CN100587947C (zh) | 2005-05-30 | 2005-09-09 | 半导体元件及其制造方法 |
US11/907,160 US7446029B2 (en) | 2005-05-30 | 2007-10-10 | Semiconductor element and manufacturing method thereof |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005157538A JP2006332533A (ja) | 2005-05-30 | 2005-05-30 | 半導体素子及びその製造方法 |
Publications (1)
Publication Number | Publication Date |
---|---|
JP2006332533A true JP2006332533A (ja) | 2006-12-07 |
Family
ID=37462346
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2005157538A Pending JP2006332533A (ja) | 2005-05-30 | 2005-05-30 | 半導体素子及びその製造方法 |
Country Status (5)
Country | Link |
---|---|
US (2) | US7298051B2 (ja) |
JP (1) | JP2006332533A (ja) |
KR (1) | KR100666907B1 (ja) |
CN (1) | CN100587947C (ja) |
TW (1) | TWI278050B (ja) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2015103776A (ja) * | 2013-11-28 | 2015-06-04 | 日本電信電話株式会社 | 多層配線用パッド構造 |
US11296013B2 (en) | 2019-11-28 | 2022-04-05 | Socionext Inc. | Semiconductor wafer and semiconductor device for suppressing the propagation of cracks |
Families Citing this family (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007042817A (ja) * | 2005-08-02 | 2007-02-15 | Sanyo Electric Co Ltd | 絶縁ゲート型半導体装置およびその製造方法 |
JP5066836B2 (ja) * | 2005-08-11 | 2012-11-07 | セイコーエプソン株式会社 | 電気光学装置及び電子機器 |
CN100413066C (zh) | 2005-11-30 | 2008-08-20 | 中芯国际集成电路制造(上海)有限公司 | 低k介电材料的接合焊盘和用于制造半导体器件的方法 |
US7679180B2 (en) * | 2006-11-07 | 2010-03-16 | Taiwan Semiconductor Manufacturing Co., Ltd. | Bond pad design to minimize dielectric cracking |
US7749778B2 (en) * | 2007-01-03 | 2010-07-06 | International Business Machines Corporation | Addressable hierarchical metal wire test methodology |
JP5034740B2 (ja) * | 2007-07-23 | 2012-09-26 | ルネサスエレクトロニクス株式会社 | 半導体装置及びその製造方法 |
JP4799542B2 (ja) * | 2007-12-27 | 2011-10-26 | 株式会社東芝 | 半導体パッケージ |
US8178980B2 (en) * | 2008-02-05 | 2012-05-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Bond pad structure |
JP2011146563A (ja) * | 2010-01-15 | 2011-07-28 | Panasonic Corp | 半導体装置 |
US8659170B2 (en) * | 2010-01-20 | 2014-02-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device having conductive pads and a method of manufacturing the same |
US8614508B2 (en) * | 2011-09-21 | 2013-12-24 | Stats Chippac Ltd. | Integrated circuit system with test pads and method of manufacture thereof |
JP5729290B2 (ja) | 2011-12-16 | 2015-06-03 | 富士通株式会社 | 半導体装置の製造方法、電子装置の製造方法及び基板 |
KR101678162B1 (ko) * | 2015-07-01 | 2016-11-21 | 서울대학교산학협력단 | 유연성 소자용 접속 구조물 및 이의 제조 방법 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH08293523A (ja) * | 1995-02-21 | 1996-11-05 | Seiko Epson Corp | 半導体装置およびその製造方法 |
JPH1187505A (ja) * | 1997-09-11 | 1999-03-30 | Nec Corp | 半導体装置の製造方法 |
JP2005079288A (ja) * | 2003-08-29 | 2005-03-24 | Seiko Epson Corp | 多層配線の形成方法および電子デバイス |
JP2006005202A (ja) * | 2004-06-18 | 2006-01-05 | Nec Electronics Corp | 半導体装置 |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3482779B2 (ja) | 1996-08-20 | 2004-01-06 | セイコーエプソン株式会社 | 半導体装置およびその製造方法 |
US5986343A (en) * | 1998-05-04 | 1999-11-16 | Lucent Technologies Inc. | Bond pad design for integrated circuits |
US6448650B1 (en) * | 1998-05-18 | 2002-09-10 | Texas Instruments Incorporated | Fine pitch system and method for reinforcing bond pads in semiconductor devices |
US6552438B2 (en) * | 1998-06-24 | 2003-04-22 | Samsung Electronics Co. | Integrated circuit bonding pads including conductive layers with arrays of unaligned spaced apart insulating islands therein and methods of forming same |
JP2001358169A (ja) | 2000-06-15 | 2001-12-26 | Nec Corp | 半導体装置 |
KR100421043B1 (ko) | 2000-12-21 | 2004-03-04 | 삼성전자주식회사 | 비정렬되고 소정 거리 이격된 섬형 절연체들의 배열을 갖는 도전막을 포함하는 집적 회로 본딩 패드 |
KR100437460B1 (ko) * | 2001-12-03 | 2004-06-23 | 삼성전자주식회사 | 본딩패드들을 갖는 반도체소자 및 그 제조방법 |
-
2005
- 2005-05-30 JP JP2005157538A patent/JP2006332533A/ja active Pending
- 2005-08-23 TW TW094128726A patent/TWI278050B/zh not_active IP Right Cessation
- 2005-08-23 US US11/208,549 patent/US7298051B2/en active Active
- 2005-09-07 KR KR1020050083036A patent/KR100666907B1/ko active IP Right Grant
- 2005-09-09 CN CN200510099898A patent/CN100587947C/zh not_active Expired - Fee Related
-
2007
- 2007-10-10 US US11/907,160 patent/US7446029B2/en active Active
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH08293523A (ja) * | 1995-02-21 | 1996-11-05 | Seiko Epson Corp | 半導体装置およびその製造方法 |
JPH1187505A (ja) * | 1997-09-11 | 1999-03-30 | Nec Corp | 半導体装置の製造方法 |
JP2005079288A (ja) * | 2003-08-29 | 2005-03-24 | Seiko Epson Corp | 多層配線の形成方法および電子デバイス |
JP2006005202A (ja) * | 2004-06-18 | 2006-01-05 | Nec Electronics Corp | 半導体装置 |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2015103776A (ja) * | 2013-11-28 | 2015-06-04 | 日本電信電話株式会社 | 多層配線用パッド構造 |
US11296013B2 (en) | 2019-11-28 | 2022-04-05 | Socionext Inc. | Semiconductor wafer and semiconductor device for suppressing the propagation of cracks |
Also Published As
Publication number | Publication date |
---|---|
US20080038914A1 (en) | 2008-02-14 |
US7446029B2 (en) | 2008-11-04 |
US7298051B2 (en) | 2007-11-20 |
US20060267222A1 (en) | 2006-11-30 |
TW200642017A (en) | 2006-12-01 |
KR100666907B1 (ko) | 2007-01-11 |
KR20060124532A (ko) | 2006-12-05 |
CN1873962A (zh) | 2006-12-06 |
TWI278050B (en) | 2007-04-01 |
CN100587947C (zh) | 2010-02-03 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP2006332533A (ja) | 半導体素子及びその製造方法 | |
KR100329407B1 (ko) | 반도체 소자의 전극 구조 | |
US9373591B2 (en) | Semiconductor device for preventing crack in pad region and fabricating method thereof | |
JPH0817859A (ja) | 半導体装置 | |
JP2005236277A (ja) | 半導体集積回路 | |
US8697566B2 (en) | Bump structure and manufacturing method thereof | |
JP2010050177A (ja) | 半導体装置 | |
US8044482B2 (en) | Semiconductor device | |
JP2009164607A (ja) | ボンディングパッド構造物及びその製造方法、並びにボンディングパッド構造物を有する半導体パッケージ | |
US6710448B2 (en) | Bonding pad structure | |
KR101589690B1 (ko) | 반도체 소자의 본딩 패드 및 그의 제조방법 | |
US8247903B2 (en) | Semiconductor device | |
JP2015002234A (ja) | 半導体装置及びその製造方法 | |
JP2007059867A (ja) | 半導体装置 | |
US10256201B2 (en) | Bonding pad structure having island portions and method for manufacturing the same | |
US9111755B1 (en) | Bond pad and passivation layer having a gap and method for forming | |
JP2005327763A (ja) | 半導体装置 | |
US7632749B1 (en) | Semiconductor device having a pad metal layer and a lower metal layer that are electrically coupled, whereas apertures are formed in the lower metal layer below a center area of the pad metal layer | |
KR100971211B1 (ko) | 크랙 방지를 위한 반도체 칩 패키지 및 그 제조 방법 | |
JP2005116562A (ja) | 半導体装置 | |
WO2021187187A1 (ja) | 半導体装置、半導体装置の製造方法、及び電子機器 | |
JP2007242644A (ja) | 半導体装置及びその製造方法 | |
JP2007123303A (ja) | 半導体装置 | |
US20100127401A1 (en) | Semiconductor device | |
JP2007527120A (ja) | 応力緩和部を備えた電子装置 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20080509 |
|
A711 | Notification of change in applicant |
Free format text: JAPANESE INTERMEDIATE CODE: A712 Effective date: 20080729 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20100413 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20100611 |
|
A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 20100629 |