JP2011091280A - Wiring board and method of manufacturing the same - Google Patents

Wiring board and method of manufacturing the same Download PDF

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JP2011091280A
JP2011091280A JP2009244988A JP2009244988A JP2011091280A JP 2011091280 A JP2011091280 A JP 2011091280A JP 2009244988 A JP2009244988 A JP 2009244988A JP 2009244988 A JP2009244988 A JP 2009244988A JP 2011091280 A JP2011091280 A JP 2011091280A
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wiring conductor
insulating resin
resin layer
layer
strip
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JP5455116B2 (en
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Koichi Osumi
孝一 大隅
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Kyocera SLC Technologies Corp
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a wiring board high in degree of freedom in design of a wiring conductor, and small in size and high in density; and to provide a method of manufacturing the same. <P>SOLUTION: The wiring board includes: a lower insulating resin layer 3; a plurality of lower belt-shaped wiring conductors 4b formed on the lower insulating resin layer 3 abreast; an upper insulating resin layer 3 embedding the lower belt-shaped wiring conductors 4b; conductive projections 4c which are formed on the lower belt-shaped wiring conductors 4b to stand abreast with widths corresponding to the widths of the lower belt-shaped wiring conductors 4b and whose upper surfaces are exposed from the upper insulating resin layer 3; and upper belt-shaped wiring conductors 4a which are formed on the conductive projections 4c and the upper insulating resin layer 3 and have a plurality of semiconductor element connection pads 4A, with which electrode terminals of a semiconductor element are connected, on the respective conductive projections 4c. A part of the upper belt-shaped wiring conductor 4a has a lead-out part 4a' extending from its semiconductor element connection pad 4A toward at least one of both sides of the row of the semiconductor element connection pad 4A. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

本発明は配線基板およびその製造方法に関し、より詳細には、例えばペリフェラル型の半導体集積回路素子をフリップチップ接続により搭載するのに好適な配線基板およびその製造方法に関する。   The present invention relates to a wiring board and a manufacturing method thereof, and more particularly to a wiring board suitable for mounting, for example, a peripheral type semiconductor integrated circuit element by flip chip connection and a manufacturing method thereof.

従来から、半導体集積回路素子として、多数の電極端子を、その一方の主面の外周に沿って配設した、いわゆるペリフェラル型の半導体集積回路素子がある。
このような半導体集積回路素子を配線基板に搭載する方法として、フリップチップ接続により接続する方法がある。フリップチップ接続とは、配線基板上に設けた配線導体の一部を半導体集積回路素子の電極端子の配置に対応した並びに半導体素子接続パッドとして露出させ、この半導体素子接続パッドと前記半導体集積回路素子の電極端子とを対向させ、これらを半田等の導電バンプを介して電気的に接続する方法である。 2. Description of the Related Art Conventionally, as a semiconductor integrated circuit element, there is a so-called peripheral type semiconductor integrated circuit element in which a large number of electrode terminals are arranged along the outer periphery of one main surface thereof.
As a method of mounting such a semiconductor integrated circuit element on a wiring board, there is a method of connecting by flip chip connection. The flip-chip connection means that a part of the wiring conductor provided on the wiring board is exposed as a semiconductor element connection pad corresponding to the arrangement of the electrode terminals of the semiconductor integrated circuit element, and the semiconductor element connection pad and the semiconductor integrated circuit element are exposed. This electrode terminal is opposed to each other, and these are electrically connected via conductive bumps such as solder.

図８は、ペリフェラル型の半導体集積回路素子をフリップチップ接続により搭載した従来の配線基板を示す概略断面図であり、図９は、図８の配線基板において上面側における最表層の配線導体を透視して示す上面図である。   FIG. 8 is a schematic cross-sectional view showing a conventional wiring board on which peripheral type semiconductor integrated circuit elements are mounted by flip-chip connection. FIG. 9 is a perspective view of the uppermost wiring conductor on the upper surface side of the wiring board of FIG. FIG.

図８に示すように、従来の配線基板１２０は、上面から下面にかけてコア用の配線導体１０２が配設されたコア用の絶縁基板１０３の上下面にビルドアップ用の絶縁樹脂層１０４とビルドアップ用の配線導体１０５とが交互に積層され、さらに、その最表面には保護用のソルダーレジスト層１０６が披着されている。   As shown in FIG. 8, the conventional wiring board 120 includes a build-up insulating resin layer 104 and a build-up on the upper and lower surfaces of the core insulating board 103 in which the core wiring conductors 102 are disposed from the upper surface to the lower surface. Wiring conductors 105 are alternately laminated, and a protective solder resist layer 106 is displayed on the outermost surface.

コア用の絶縁基板１０３の上面から下面にかけては複数のスルーホール１０７がドリル加工により形成されている。絶縁基板１０３の上下面およびスルーホール１０７の内面にはコア用の配線導体１０２部が披着され、スルーホール１０７の内部には埋め込み樹脂１０８が充填されている。   A plurality of through holes 107 are formed by drilling from the upper surface to the lower surface of the core insulating substrate 103. The core wiring conductor 102 is shown on the upper and lower surfaces of the insulating substrate 103 and the inner surface of the through hole 107, and the through hole 107 is filled with a filling resin 108.

ビルドアップ用の絶縁樹脂層１０４には、それぞれに複数のビアホール１０９がレーザ加工により形成されている。各絶縁樹脂層１０４の表面およびビアホール１０９の内面には、ビルドアップ用の配線導体１０５が披着形成されている。配線導体１０５は、配線基板１２０の上面側における最表層の絶縁樹脂層１０４上に披着された一部が半導体集積回路素子１０１の電極端子に導電バンプ１１０を介して電気的に接続される半導体素子接続パッド１０５Ａを有する帯状配線導体１０５ａである。この帯状配線導体１０５ａのうち、ソルダーレジスト層１０６から露出した露出部が半導体素子接続パッド１０５Ａを形成しており、この半導体素子接続パッド１０５Ａに半導体集積回路素子１０１の電極端子が半田や金等から成る導電バンプ１１０を介して電気的に接続される。また、配線基板１２０の下面側における最外層の絶縁樹脂層１０４上に披着された一部が外部電気回路基板の配線導体に電気的に接続される外部接続用パッド１０５Ｂを形成しており、この外部接続パッド１０５Ｂに、外部電気回路基板の配線導体が半田ボール１１１を介して電気的に接続される。   A plurality of via holes 109 are formed in each of the build-up insulating resin layers 104 by laser processing. A buildup wiring conductor 105 is formed on the surface of each insulating resin layer 104 and the inner surface of the via hole 109. A part of the wiring conductor 105 on the uppermost insulating resin layer 104 on the upper surface side of the wiring substrate 120 is electrically connected to the electrode terminal of the semiconductor integrated circuit element 101 via the conductive bump 110. This is a strip-shaped wiring conductor 105a having an element connection pad 105A. Of the strip-shaped wiring conductor 105a, an exposed portion exposed from the solder resist layer 106 forms a semiconductor element connection pad 105A, and the electrode terminal of the semiconductor integrated circuit element 101 is formed of solder, gold, or the like on the semiconductor element connection pad 105A. The conductive bumps 110 are electrically connected. In addition, a part of the outermost insulating resin layer 104 on the lower surface side of the wiring board 120 is formed as an external connection pad 105B that is electrically connected to the wiring conductor of the external electric circuit board. The wiring conductor of the external electric circuit board is electrically connected to the external connection pad 105B through the solder ball 111.

ソルダーレジスト層１０６は、最表層の配線導体１０５を保護するとともに半導体素子接続パッド１０５Ａや外部接続パッド１０５Ｂの露出部を画定する。このようなソルダーレジスト層１０６は、光感光性を有する熱硬化性樹脂ペーストまたはフィルムを配線導体１０５が形成された最外層の絶縁樹脂層１０４上に積層した後、半導体素子接続パッド１０５Ａや外部接続パッド１０５Ｂを露出させる開口を有するように露光および現像し、硬化させることにより形成される。なお、図９に示すように、上面側のソルダーレジスト層１０６は、半導体素子接続パッド１０５Ａを露出させるスリット状の開口１０６ａを有している。   The solder resist layer 106 protects the outermost wiring conductor 105 and defines exposed portions of the semiconductor element connection pads 105A and the external connection pads 105B. Such a solder resist layer 106 is formed by laminating a thermosetting resin paste or film having photosensitivity on the outermost insulating resin layer 104 on which the wiring conductor 105 is formed, and then connecting the semiconductor element connection pad 105A or external connection. It is formed by exposing, developing and curing so as to have an opening for exposing the pad 105B. As shown in FIG. 9, the solder resist layer 106 on the upper surface side has a slit-like opening 106a for exposing the semiconductor element connection pad 105A.

そして、半導体集積回路素子１０１の電極端子と半導体素子接続パッド１０５Ａとを導電バンプ１１０を介して電気的に接続した後、半導体集積回路素子１０１と配線基板１２０との間にエポキシ樹脂等の熱硬化性樹脂から成るアンダーフィルと呼ばれる充填樹脂１１２を充填し、半導体集積回路素子１０１が配線基板１２０上に実装される。   Then, after electrically connecting the electrode terminals of the semiconductor integrated circuit element 101 and the semiconductor element connection pads 105A via the conductive bumps 110, thermosetting of epoxy resin or the like between the semiconductor integrated circuit element 101 and the wiring board 120 is performed. Filling resin 112 called underfill made of a conductive resin is filled, and semiconductor integrated circuit element 101 is mounted on wiring board 120.

ところで近時、半導体集積回路素子１０１は、その高集積度化が急激に進み、半導体集積回路素子１０１における電極端子のピッチは１００μｍ以下と狭ピッチになってきている。これに伴い、半導体素子接続パッド１０５Ａのピッチも１００μｍ以下となるとともに幅も５０μｍ以下と狭くなってきている。このように半導体素子接続パッド１０５Ａのピッチおよび幅が狭くなると、これらの半導体素子接続パッド１０５Ａをビアホール１０９を介して下層の配線導体１０５に接続するには、帯状配線導体１０５ａを半導体素子接続パッド１０５Ａから上面側における最表層の絶縁樹脂層１０４上の外周部に引き出して帯状配線導体１０５ａのピッチを１５０〜２００μｍ程度に拡げ、そのピッチが拡がった部位においてビアホール１０９を介して下層の配線導体１０５に接続する必要がある。なぜなら、ビアホール１０９はレーザ加工により形成されており直径が３０〜１００μｍ程度あり、この直径のビアホール１０９を介して上下の配線導体１０５同士を狭いピッチのままで接続すると、隣接する配線導体１０５間で電気的な短絡が発生するからである。ビアホール１０９を介して接続される配線導体１０５間の絶縁信頼性の確保やビアホール１０９や配線導体１０５の製造上のずれを考慮するとビアホール１０９のピッチは１５０〜２００μｍ程度必要となる。   Recently, the semiconductor integrated circuit element 101 has been rapidly integrated, and the pitch of electrode terminals in the semiconductor integrated circuit element 101 has become narrower than 100 μm. Along with this, the pitch of the semiconductor element connection pads 105A is also reduced to 100 μm or less and the width is reduced to 50 μm or less. When the pitch and width of the semiconductor element connection pads 105A are thus reduced, in order to connect these semiconductor element connection pads 105A to the lower wiring conductors 105 via the via holes 109, the belt-like wiring conductors 105a are connected to the semiconductor element connection pads 105A. To the outer peripheral portion on the uppermost insulating resin layer 104 on the upper surface side, the pitch of the band-like wiring conductor 105a is expanded to about 150 to 200 μm, and the lower-layer wiring conductor 105 is connected to the lower wiring conductor 105 via the via hole 109 at the portion where the pitch is increased. Need to connect. This is because the via hole 109 is formed by laser processing and has a diameter of about 30 to 100 μm, and when the upper and lower wiring conductors 105 are connected at a narrow pitch through the via hole 109 having this diameter, the adjacent wiring conductors 105 are connected to each other. This is because an electrical short circuit occurs. In consideration of ensuring insulation reliability between the wiring conductors 105 connected via the via holes 109 and manufacturing deviations of the via holes 109 and the wiring conductors 105, the pitch of the via holes 109 needs to be about 150 to 200 μm.

従来の配線基板では、上述のように、半導体素子接続パッド１０５Ａを下層の配線導体１０５に接続するために帯状配線導体１０５ａを半導体素子接続パッド１０５Ａから上面側における最表層の絶縁樹脂層１０４上の外周部に引き出して帯状配線導体１０５ａのピッチを１５０〜２００μｍ程度に拡げ、そのピッチが拡がった部位においてビアホール１０９を介して下層の配線導体１０５に接続する必要があることから、半導体素子接続パッド１０５Ａと他の層の配線導体１０５とを接続するための設計自由度が大きく制限される。そのため、配線基板の小型化・高密度化が困難であるという問題点を有していた。   In the conventional wiring board, as described above, in order to connect the semiconductor element connection pad 105A to the lower wiring conductor 105, the strip-shaped wiring conductor 105a is disposed on the uppermost insulating resin layer 104 on the upper surface side from the semiconductor element connection pad 105A. Since the pitch of the strip-shaped wiring conductor 105a is extended to about 150 to 200 μm by being drawn out to the outer peripheral portion and needs to be connected to the lower wiring conductor 105 via the via hole 109 at the portion where the pitch is widened, the semiconductor element connection pad 105A The degree of freedom in design for connecting the wiring conductor 105 of the other layer to the wiring layer 105 is greatly limited. For this reason, it has been difficult to reduce the size and density of the wiring board.

特開２０００−７７４７１号公報JP 2000-77471 A

本発明の課題は、半導体素子接続パッドと他の層の配線導体とを接続するための設計自由度が高く、小型で高密度の配線基板およびその製造方法を提供することにある。   SUMMARY OF THE INVENTION An object of the present invention is to provide a small and high-density wiring board having a high degree of design freedom for connecting a semiconductor element connection pad and a wiring conductor of another layer, and a method for manufacturing the same.

本発明の配線基板は、下層の絶縁樹脂層と、該下層の絶縁樹脂層上に複数並んで形成された下層の帯状配線導体と、該下層の帯状配線導体を埋設する上層の絶縁樹脂層と、前記下層の帯状配線導体上に該下層の帯状配線導体の幅と一致する幅で横に一列に並ぶように形成されており、上面が前記上層の絶縁樹脂層から露出する導電突起と、該導電突起および前記上層の絶縁樹脂層上に形成されており、半導体素子の電極端子が接続される複数の半導体素子接続パッドを各前記導電突起上に有する複数の上層の帯状配線導体とを具備し、前記上層の帯状配線導体の一部は、前記半導体素子接続パッドから該半導体素子接続パッドの並びの両側の少なくとも一方に向けて延びる引き出し部を有していることを特徴とするものである。   The wiring board of the present invention includes a lower insulating resin layer, a plurality of lower strip-shaped wiring conductors formed side by side on the lower insulating resin layer, and an upper insulating resin layer in which the lower strip-shaped wiring conductor is embedded. A conductive protrusion that is formed on the lower strip-shaped wiring conductor so as to be aligned in a horizontal row with a width that matches the width of the lower strip-shaped wiring conductor; and an upper surface that is exposed from the upper insulating resin layer; A plurality of upper layer strip-like wiring conductors formed on the conductive protrusions and the upper insulating resin layer and having a plurality of semiconductor element connection pads on each of the conductive protrusions to which electrode terminals of the semiconductor elements are connected; A part of the strip-shaped wiring conductor in the upper layer has a lead portion extending from the semiconductor element connection pad toward at least one of both sides of the array of the semiconductor element connection pads.

本発明の配線基板の製造方法は、下層の絶縁樹脂層上に下層の帯状配線導体を複数並べて形成するとともに該下層の帯状配線導体上に導電突起を前記下層の帯状配線導体の幅と一致する幅で形成する工程と、粗化面を有する金属箔の前記粗化面上に塗布された半硬化の熱硬化性樹脂材料を、前記下層の絶縁樹脂層および前記下層の帯状配線導体および前記導電突起上に、前記金属箔の前記粗化面が前記導電突起上面に当接するまで前記金属箔上から圧接して前記下層の帯状配線導体および前記導電突起を前記熱硬化性樹脂材料中に埋設するとともに、前記熱硬化性樹脂材料を熱硬化させて該熱硬化性樹脂材料の硬化物から成る上層の絶縁樹脂層を形成する工程と、前記上層の絶縁樹脂層の表面から前記金属箔をエッチング除去するとともに前記導電突起上に残る前記熱硬化性樹脂材料の残渣を除去する工程と、前記導電突起上および前記上層の絶縁樹脂層上に上層の帯状配線導体を、前記導電突起上に半導体素子接続パッドを有するように形成する工程とを行うことを特徴とするものである。   In the method for manufacturing a wiring board according to the present invention, a plurality of lower strip wiring conductors are formed side by side on a lower insulating resin layer, and conductive protrusions on the lower strip wiring conductor coincide with the width of the lower strip wiring conductor. A semi-cured thermosetting resin material applied on the roughened surface of the metal foil having a roughened surface and a step of forming a width, the lower insulating resin layer, the lower belt-like wiring conductor, and the conductive On the protrusion, the lower-layer strip conductor and the conductive protrusion are embedded in the thermosetting resin material by pressing from above the metal foil until the roughened surface of the metal foil contacts the upper surface of the conductive protrusion. And a step of thermally curing the thermosetting resin material to form an upper insulating resin layer made of a cured product of the thermosetting resin material, and etching and removing the metal foil from the surface of the upper insulating resin layer. And before A step of removing a residue of the thermosetting resin material remaining on the conductive protrusion, an upper-layer strip conductor on the conductive protrusion and the upper insulating resin layer, and a semiconductor element connection pad on the conductive protrusion. In this way, the forming step is performed.

本発明の配線基板によれば、下層の絶縁樹脂層上に複数並んで形成された下層の帯状配線導体上に、この下層の帯状配線導体と一致する幅で導電突起が形成されており、この導電突起上に半導体素子接続パッドを有するとともに半導体素子接続パッドの並びの両側の少なくとも一方に向けて延びる引き出し部を有する上層の帯状配線導体が形成されていることから、半導体素子接続パッドは、半導体素子接続パッドと同じピッチの導電突起を介して下層の帯状配線導体に接続されるとともに上層の帯状配線導体の引き出し部からも他の層の配線導体に接続可能となるので、半導体素子接続パッドと他の層の配線導体とを接続するための設計自由度が高くなり、それにより小型で高密度の配線基板とすることができる。   According to the wiring board of the present invention, the conductive protrusions are formed on the lower strip-shaped wiring conductor formed side by side on the lower insulating resin layer with a width that matches the lower strip-shaped wiring conductor. Since the upper layer strip-like wiring conductor having the semiconductor element connection pads on the conductive protrusions and the leading portions extending toward at least one of the both sides of the semiconductor element connection pads is formed, Since it is connected to the lower band-shaped wiring conductor via conductive protrusions of the same pitch as the element connection pad and can be connected to the wiring conductor of another layer from the lead-out portion of the upper-layer band-shaped wiring conductor, the semiconductor element connection pad and The degree of freedom of design for connecting to the wiring conductors of other layers is increased, and thereby a small and high-density wiring board can be obtained.

また、本発明の配線基板の製造方法によれば、下層の絶縁樹脂層上に複数並んで形成された下層の帯状配線導体上に導電突起を下層の帯状配線導体と一致する幅で形成し、その上から金属箔に塗布された半硬化の熱硬化性樹脂材料を圧接して下層の帯状配線導体および導電突起を熱硬化性樹脂材料中に埋設するとともに熱硬化性樹脂材料を熱硬化させて上層の絶縁樹脂層を形成し、しかる後、上層の絶縁樹脂層上から金属箔を除去するとともに導電突起上の樹脂残渣を除去し、その上に上層の帯状配線導体を、導電突起上に半導体素子接続パッド有するように形成することら、半導体素子接続パッドと他の層の配線導体とを接続するための設計自由度が高く、かつ小型で高密度の配線基板を提供することができる。   In addition, according to the method for manufacturing a wiring board of the present invention, a conductive protrusion is formed on the lower strip-shaped wiring conductor formed side by side on the lower insulating resin layer with a width that matches the lower strip-shaped wiring conductor, A semi-cured thermosetting resin material applied to the metal foil is pressed from above to embed the underlying strip-like wiring conductor and conductive protrusion in the thermosetting resin material and thermoset the thermosetting resin material. An upper insulating resin layer is formed, and then the metal foil is removed from the upper insulating resin layer and the resin residue on the conductive protrusion is removed, and the upper strip-shaped wiring conductor is formed on the conductive protrusion. By forming the element connection pads, it is possible to provide a small and high-density wiring board having a high degree of design freedom for connecting the semiconductor element connection pads and wiring conductors of other layers.

図１は、本発明の配線基板の実施形態の一例を示す断面図である。FIG. 1 is a cross-sectional view showing an example of an embodiment of a wiring board according to the present invention. 図２は、図１に示す配線基板の上面図である。FIG. 2 is a top view of the wiring board shown in FIG. 図３は、図１および図２に示す配線基板における一部の構成部材のみを抜き出した要部斜視図である。FIG. 3 is a perspective view of a main part in which only some constituent members in the wiring board shown in FIGS. 1 and 2 are extracted. （ａ）〜（ｅ）は、本発明の配線基板の製造方法を説明するための工程毎の要部斜視図であり、（ａ’）〜（ｅ’）は、（ａ）〜（ｅ）に対応する要部断面図である。(A)-(e) is a principal part perspective view for every process for demonstrating the manufacturing method of the wiring board of this invention, (a ')-(e') is (a)-(e). It is principal part sectional drawing corresponding to these. （ｆ）〜（ｊ）は、本発明の配線基板の製造方法を説明するための工程毎の要部斜視図であり、（ｆ’）〜（ｊ’）は、（ｆ）〜（ｊ）に対応する要部断面図である。(F)-(j) is a principal part perspective view for every process for demonstrating the manufacturing method of the wiring board of this invention, (f ')-(j') is (f)-(j). It is principal part sectional drawing corresponding to these. （ｋ）〜（ｏ）は、本発明の配線基板の製造方法を説明するための工程毎の要部斜視図であり、（ｋ’）〜（ｏ’）は、（ｋ）〜（ｏ）に対応する要部断面図である。(K)-(o) is a principal part perspective view for every process for demonstrating the manufacturing method of the wiring board of this invention, (k ')-(o') is (k)-(o). It is principal part sectional drawing corresponding to these. （ｐ）〜（ｑ）は、本発明の配線基板の製造方法を説明するための工程毎の要部斜視図であり、（ｐ’）〜（ｑ’）は、（ｐ）〜（ｑ）に対応する要部断面図である。(P)-(q) is a principal part perspective view for every process for demonstrating the manufacturing method of the wiring board of this invention, (p ')-(q') is (p)-(q). It is principal part sectional drawing corresponding to these. 図８は、従来の配線基板を示す断面図である。FIG. 8 is a cross-sectional view showing a conventional wiring board. 図９は、図８に示す配線基板の上面図である。FIG. 9 is a top view of the wiring board shown in FIG.

次に、本発明の配線基板の実施形態の一例を添付の図面を基に説明する。図１に示すように、本発明にかかる配線基板１０は、上面から下面にかけてコア用の配線導体２が配設されたコア用の絶縁基板１の上下面にビルドアップ用の絶縁樹脂層３とビルドアップ用の配線導体４とが交互に積層され、さらに、その最表面には保護用のソルダーレジスト層５が披着されている。   Next, an example of an embodiment of a wiring board according to the present invention will be described with reference to the accompanying drawings. As shown in FIG. 1, a wiring board 10 according to the present invention has a build-up insulating resin layer 3 on the upper and lower surfaces of a core insulating substrate 1 in which core wiring conductors 2 are arranged from the upper surface to the lower surface. Build-up wiring conductors 4 are alternately laminated, and a protective solder resist layer 5 is displayed on the outermost surface.

絶縁基板１は、厚みが０．０５〜０．４ｍｍ程度であり、例えばガラス繊維束を縦横に織ったガラスクロスにビスマレイミドトリアジン樹脂やエポキシ樹脂等の熱硬化性樹脂を含浸させた電気絶縁材料から成り、配線基板１０のコア部材として機能する。   The insulating substrate 1 has a thickness of about 0.05 to 0.4 mm. For example, an electrically insulating material obtained by impregnating a glass cloth in which glass fiber bundles are woven vertically and horizontally with a thermosetting resin such as bismaleimide triazine resin or epoxy resin. And functions as a core member of the wiring board 10.

絶縁基板１の上面から下面にかけては、直径が０．０５〜０．３ｍｍ程度の複数のスルーホール６が形成されており、絶縁基板１の上下面およびスルーホール６の内面には、コア用の配線導体２が披着されている。コア用の配線導体２は、絶縁基板１の上下面では、主として銅箔から形成されており、スルーホール６内面では、無電解銅めっきおよびその上の電解銅めっきから形成されている。   A plurality of through holes 6 having a diameter of about 0.05 to 0.3 mm are formed from the upper surface to the lower surface of the insulating substrate 1, and the upper and lower surfaces of the insulating substrate 1 and the inner surface of the through hole 6 are for cores. A wiring conductor 2 is shown. The core wiring conductor 2 is mainly formed of copper foil on the upper and lower surfaces of the insulating substrate 1, and is formed of electroless copper plating and electrolytic copper plating thereon on the inner surface of the through hole 6.

また、スルーホール６内部には、エポキシ樹脂等の熱硬化性樹脂から成る埋め込み樹脂７が充填されており、絶縁基板１の上下面に形成された配線導体２同士がスルーホール６を介して電気的に接続されている。   The through hole 6 is filled with an embedded resin 7 made of a thermosetting resin such as an epoxy resin, and the wiring conductors 2 formed on the upper and lower surfaces of the insulating substrate 1 are electrically connected through the through hole 6. Connected.

このような絶縁基板１は、ガラス織物に未硬化の熱硬化性樹脂を含浸させたシートの上下面に配線導体２用の銅箔を貼着した後、そのシートを熱硬化させ、これに上面から下面にかけてスルーホール６用のドリル加工を施すことにより製作される。   Such an insulating substrate 1 is obtained by sticking a copper foil for the wiring conductor 2 on the upper and lower surfaces of a sheet in which a glass fabric is impregnated with an uncured thermosetting resin, and then thermally curing the sheet, The through hole 6 is drilled from the bottom to the bottom.

コア用の配線導体２は、絶縁基板１用のシートの上下全面に厚みが３〜５０μｍ程度の銅箔を上述のように貼着しておくとともに、これらの銅箔および絶縁基板１にスルーホール６を穿孔した後、このスルーホール６の内面および銅箔表面に無電解銅めっきおよび電解銅めっきを順次施し、次にスルーホール６内を埋め込み樹脂７で充填した後、この上下面の銅箔および銅めっきをフォトリソグラフィ技術を用いて所定のパターンにエッチング加工することにより絶縁基板１の上下面およびスルーホール６の内面に形成される。   The core wiring conductor 2 has a copper foil having a thickness of about 3 to 50 μm adhered to the entire upper and lower surfaces of the sheet for the insulating substrate 1 as described above, and through holes are formed in the copper foil and the insulating substrate 1. 6 is drilled, electroless copper plating and electrolytic copper plating are sequentially applied to the inner surface of the through hole 6 and the surface of the copper foil, and then the through hole 6 is filled with the embedded resin 7. Then, the copper plating is formed on the upper and lower surfaces of the insulating substrate 1 and the inner surface of the through hole 6 by etching into a predetermined pattern using a photolithography technique.

埋め込み樹脂７は、スルーホール６を塞ぐことによりスルーホール６の直上および直下にビルドアップ用の絶縁樹脂層３を形成可能とするためのものであり、未硬化のペースト状の熱硬化性樹脂をスルーホール６内にスクリーン印刷法により充填し、これを熱硬化させた後、その上下面を略平坦に研磨することにより形成される。   The embedding resin 7 is for making it possible to form the insulating resin layer 3 for buildup directly above and below the through-hole 6 by closing the through-hole 6, and an uncured pasty thermosetting resin is used. The through-hole 6 is formed by filling the through-hole 6 by screen printing, thermally curing it, and then polishing the upper and lower surfaces thereof substantially flatly.

絶縁基板１の上下面に積層されたビルドアップ用の絶縁樹脂層３は、それぞれの厚みが２０〜６０μｍ程度であり、絶縁基板１と同様にガラスクロスに熱硬化性樹脂を含浸させた電気絶縁材料や、あるいはエポキシ樹脂等の熱硬化性樹脂に酸化ケイ素等の無機絶縁フィラーを分散させた電気絶縁材料から成る。各絶縁樹脂層３には、直径が３０〜１００μｍ程度の複数のビアホール８が形成されている。   The insulating resin layers 3 for buildup laminated on the upper and lower surfaces of the insulating substrate 1 each have a thickness of about 20 to 60 μm. Similarly to the insulating substrate 1, the glass cloth is impregnated with a thermosetting resin. It consists of a material or an electrically insulating material in which an inorganic insulating filler such as silicon oxide is dispersed in a thermosetting resin such as an epoxy resin. A plurality of via holes 8 having a diameter of about 30 to 100 μm are formed in each insulating resin layer 3.

各絶縁樹脂層３の表面およびビアホール８内面には、無電解銅めっきおよびその上の電解銅めっきから成るビルドアップ用の配線導体４が披着形成されている。そして、絶縁樹脂層３を挟んで上層に位置する配線導体４と下層に位置する配線導体４とをビアホール８を介して電気的に接続することにより高密度配線が立体的に形成される。   A build-up wiring conductor 4 made of electroless copper plating and electrolytic copper plating thereon is formed on the surface of each insulating resin layer 3 and the inner surface of the via hole 8. Then, the wiring conductor 4 located in the upper layer and the wiring conductor 4 located in the lower layer are electrically connected via the via hole 8 with the insulating resin layer 3 interposed therebetween, whereby a high-density wiring is formed in three dimensions.

配線導体４は、配線基板１０の上面側における最表層の絶縁樹脂層３上に披着された一部がソルダーレジスト層５から露出して半導体集積回路素子１０１の電極と半田等の導電バンプ１１０を介して電気的に接続される半導体素子接続パッド４Ａを形成しており、配線基板１０の下面側の最表層の絶縁樹脂層３上に披着された一部がソルダーレジスト層５から露出して外部電気回路基板の配線導体に半田ボール１１１を介して電気的に接続される外部接続パッド４Ｂを形成している。   A part of the wiring conductor 4 exposed on the uppermost insulating resin layer 3 on the upper surface side of the wiring substrate 10 is exposed from the solder resist layer 5, and conductive bumps 110 such as electrodes of the semiconductor integrated circuit element 101 and solder. A semiconductor element connection pad 4A is formed which is electrically connected through the wiring board 10, and a part of the semiconductor substrate connection pad 4A exposed on the outermost insulating resin layer 3 on the lower surface side of the wiring substrate 10 is exposed from the solder resist layer 5. Thus, external connection pads 4B that are electrically connected to the wiring conductors of the external electric circuit board via the solder balls 111 are formed.

そして、半導体集積回路素子１０１の電極端子と半導体素子接続パッド４Ａとを導電バンプ１１０を介して電気的に接続した後、半導体集積回路素子１０１と配線基板１０との間にエポキシ樹脂等の熱硬化性樹脂から成るアンダーフィルと呼ばれる充填樹脂１１２を充填し、半導体集積回路素子１０１が配線基板１０上に実装される。   Then, after the electrode terminals of the semiconductor integrated circuit element 101 and the semiconductor element connection pads 4A are electrically connected via the conductive bumps 110, a thermosetting such as epoxy resin is performed between the semiconductor integrated circuit element 101 and the wiring board 10. Filling resin 112 called underfill made of a conductive resin is filled, and semiconductor integrated circuit element 101 is mounted on wiring substrate 10.

なお、本例の配線基板１０においては、半導体素子接続パッド４Ａは、図２に上面側における最表層の絶縁樹脂層３上に形成された配線導体４を透視した上面図で示すように、１００μｍ以下（例えば５０〜８０μｍ）のピッチで複数並んだ幅が２０〜４０μｍ程度の帯状配線導体４ａの一部をソルダーレジスト層５に設けたスリット状の開口部５ａ内に横に一列に並べて露出させることにより形成されている。   In the wiring substrate 10 of this example, the semiconductor element connection pad 4A is 100 μm as shown in a top view of the wiring conductor 4 formed on the uppermost insulating resin layer 3 on the upper surface side in FIG. A portion of the strip-like wiring conductor 4a having a width of about 20 to 40 μm arranged at a pitch of the following (for example, 50 to 80 μm) is exposed in a line in the slit-like opening 5 a provided in the solder resist layer 5. It is formed by.

さらに、図３に上面側における最表層の絶縁樹脂層３およびその下層の絶縁樹脂層３上に被着された配線導体４の一部のみを抜き出した要部拡大斜視図で示すように、下層の絶縁樹脂層３上に半導体素子接続パッド４Ａの並びに対応した複数の下層の帯状配線導体４ｂが形成されているとともに、この下層の帯状配線導体４ｂの上に、半導体素子接続パッド４Ａと接続する導電突起４ｃが下層の帯状配線導体４ｂと一致する幅で横に一列に並んで形成されている。このように、半導体素子接続パッド４Ａと下層の帯状配線導体４ｂとは、下層の帯状配線導体４ｂと一致する幅の導電突起４ｃを介して接続されていることから、半導体素子接続パッド４Ａと下層の配線導体４ｂとを狭いピッチのままで接続することができる。さらに、上層の帯状配線導体４ａの一部は、半導体素子接続パッド４Ａから配線基板１０の外周側や中央側に向けて延びる引き出し部４ａ’を有しており、この引き出し部４ａ’を上面側における最表層の絶縁樹脂層３に形成されたビアホール８を介して下層の配線導体４に接続することで、半導体素子接続パッド４Ａと他の層の配線導体４とを接続するための設計自由度が高いものとなる。したがって、本発明の配線基板１０によれば、小型で高密度の配線基板とすることができる。   Further, as shown in FIG. 3 in an enlarged perspective view of the main part, only the uppermost insulating resin layer 3 on the upper surface side and a part of the wiring conductor 4 deposited on the insulating resin layer 3 below the uppermost layer are extracted. A plurality of lower-layer strip-like wiring conductors 4b corresponding to the semiconductor element connection pads 4A are formed on the insulating resin layer 3 and connected to the semiconductor-element connection pads 4A on the lower-layer strip-like wiring conductors 4b. The conductive protrusions 4c are formed side by side in a row with a width that coincides with the lower strip-shaped wiring conductor 4b. As described above, the semiconductor element connection pad 4A and the lower strip-shaped wiring conductor 4b are connected via the conductive protrusions 4c having a width matching the lower strip-shaped wiring conductor 4b. The wiring conductor 4b can be connected with a narrow pitch. Furthermore, a part of the upper layer strip-shaped wiring conductor 4a has a lead portion 4a ′ extending from the semiconductor element connection pad 4A toward the outer peripheral side or the center side of the wiring substrate 10, and this lead portion 4a ′ is connected to the upper surface side. The degree of freedom in design for connecting the semiconductor element connection pad 4A and the wiring conductor 4 of the other layer by connecting to the lower wiring conductor 4 through the via hole 8 formed in the outermost insulating resin layer 3 in FIG. Is expensive. Therefore, according to the wiring board 10 of the present invention, a small and high-density wiring board can be obtained.

次に、本発明の配線基板の製造方法に従い、上述の下層の絶縁樹脂層３、下層の帯状配線導体４ｂ、導電突起４ｃ、上層の絶縁樹脂層３および上層の帯状配線導体４ａおよびその上のソルダーレジスト層５を形成する方法の例について図４〜図７を基にして説明する。なお、図４〜図７は、本例における工程毎の要部斜視図およびそれに対応する断面図を示している。   Next, according to the method for manufacturing the wiring board of the present invention, the lower insulating resin layer 3, the lower strip-shaped wiring conductor 4b, the conductive protrusion 4c, the upper insulating resin layer 3, the upper strip-shaped wiring conductor 4a and the upper layer An example of a method for forming the solder resist layer 5 will be described with reference to FIGS. 4 to 7 show a perspective view of a main part for each step in this example and a cross-sectional view corresponding thereto.

まず、図４（ａ），（ａ’）に示すように、下層の絶縁樹脂層３を絶縁基板１上またはその上の絶縁樹脂層３上に形成する。このような下層の絶縁樹脂層３は、未硬化の絶縁樹脂フィルムを絶縁基板１またはその上の絶縁樹脂層３上に貼着するとともに熱硬化させることにより形成される。   First, as shown in FIGS. 4A and 4A, a lower insulating resin layer 3 is formed on the insulating substrate 1 or on the insulating resin layer 3 thereon. Such a lower insulating resin layer 3 is formed by sticking an uncured insulating resin film on the insulating substrate 1 or the insulating resin layer 3 thereon and thermally curing it.

次に、図４（ｂ），（ｂ’）に示すように、下層の絶縁樹脂層３の表面に、電解めっき用の下地金属層５１を無電解めっきにより被着形成する。下地金属層５１の厚みは０．１〜２μｍ程度である。下地金属層５１を形成する無電解めっきとしては無電解銅めっきが好ましい。   Next, as shown in FIGS. 4B and 4B, a base metal layer 51 for electrolytic plating is deposited on the surface of the lower insulating resin layer 3 by electroless plating. The thickness of the base metal layer 51 is about 0.1 to 2 μm. As the electroless plating for forming the base metal layer 51, electroless copper plating is preferable.

ついで、図４（ｃ），（ｃ’）に示すように、下地金属層５１の表面に、第一レジスト層Ｒ１を形成する。第一レジスト層Ｒ１は、下層の帯状配線導体４ｂに対応する形状の開口を有しており、光感光性アルカリ現像型ドライフィルムレジストを下地金属層５１上に貼着するとともにそれにフォトリソグラフィ技術を用いて露光および現像を行なうことにより下層の帯状配線導体４ｂに対応する形状の開口を有するパターンに形成される。また、第一レジスト層Ｒ１の厚みは、下層の帯状配線導体４ｂおよびその上に形成される導電突起４ｃの合計厚みよりも若干厚い厚みであるのがよい。   Next, as shown in FIGS. 4C and 4C, a first resist layer R <b> 1 is formed on the surface of the base metal layer 51. The first resist layer R1 has an opening having a shape corresponding to the lower strip-shaped wiring conductor 4b, and a photo-sensitive alkali development type dry film resist is stuck on the base metal layer 51 and photolithography technology is applied thereto. By using and exposing and developing, it is formed in the pattern which has an opening of the shape corresponding to the lower strip | belt-shaped wiring conductor 4b. Further, the thickness of the first resist layer R1 is preferably slightly thicker than the total thickness of the lower strip-shaped wiring conductor 4b and the conductive protrusion 4c formed thereon.

ついで、図４（ｄ），（ｄ’）に示すように、第一レジスト層Ｒ１の開口内に露出する下地金属層５１上に電解めっきにより下層の帯状配線導体４ｂを被着形成する。下層の帯状配線導体４ｂを形成するための電解めっきとしては、電解銅めっきが好ましい。ここで、下層の帯状配線導体４ｂの厚みは、第一レジスト層Ｒ１より薄くなっている。具体的には、下層の帯状配線導体４ｂの厚みは、８〜２０μｍ、好ましくは１０〜１５μｍであるのがよい。   Next, as shown in FIGS. 4D and 4D, a lower band-shaped wiring conductor 4b is formed by electrolytic plating on the base metal layer 51 exposed in the opening of the first resist layer R1. As the electrolytic plating for forming the lower strip-shaped wiring conductor 4b, electrolytic copper plating is preferable. Here, the thickness of the lower strip-shaped wiring conductor 4b is smaller than that of the first resist layer R1. Specifically, the thickness of the lower strip-shaped wiring conductor 4b is 8 to 20 μm, preferably 10 to 15 μm.

ついで、図４（ｅ），（ｅ’）に示すように、第一レジスト層Ｒ１および下層の帯状配線導体４ｂの表面に第二レジスト層Ｒ２を形成する。第二レジスト層Ｒ２は、導電突起４ｃが形成される位置に導電突起４ｃの長さに対応した幅で下層の帯状配線導体４ｂを真横に横切る開口を有しており、光感光性アルカリ現像型ドライフィルムレジストを第一レジスト層Ｒ１および下層の帯状配線導体４ｂ上に貼着するとともにそれにフォトリソグラフィ技術を用いて露光および現像を行なうことにより前述の開口を有するパターンに形成される。なお、第二レジスト層Ｒ２の厚みは第一レジスト層Ｒ１の厚み以上であることが好ましい。   Next, as shown in FIGS. 4E and 4E ', a second resist layer R2 is formed on the surface of the first resist layer R1 and the lower strip wiring conductor 4b. The second resist layer R2 has an opening at a position corresponding to the length of the conductive protrusion 4c at the position where the conductive protrusion 4c is formed, and extends across the lower strip-shaped wiring conductor 4b. A dry film resist is stuck on the first resist layer R1 and the lower strip-like wiring conductor 4b, and is exposed to light and developed using a photolithography technique to form a pattern having the aforementioned openings. In addition, it is preferable that the thickness of 2nd resist layer R2 is more than the thickness of 1st resist layer R1.

ついで、図５（ｆ），（ｆ’）に示すように、第一レジスト層Ｒ１の開口内および第二レジスト層Ｒ２の開口内に露出する下層の帯状配線導体４ｂ上に、導電突起４ｃを電解めっきにより形成する。導電突起４ｃを形成するための電解めっきとしては、電解銅めっきが好ましい。なお、導電突起４ｃの高さは８〜２０μｍ、好ましくは１０〜１５μｍであり、第一レジスト層Ｒ１の上面よりも若干低い位置とする。このとき、導電突起４ｃは、第一レジスト層Ｒ１の開口内および第二レジスト層Ｒ２の開口内に露出する下層の帯状配線導体４ｂ上に形成されるので、その幅が第一レジスト層Ｒ１の開口で画定される幅、すなわち下層の帯状配線導体４ｂの幅と一致する幅で形成される。   Next, as shown in FIGS. 5F and 5F, conductive protrusions 4c are formed on the lower strip-like wiring conductor 4b exposed in the opening of the first resist layer R1 and the opening of the second resist layer R2. It is formed by electrolytic plating. As electrolytic plating for forming the conductive protrusions 4c, electrolytic copper plating is preferable. The height of the conductive protrusion 4c is 8 to 20 [mu] m, preferably 10 to 15 [mu] m, and is slightly lower than the upper surface of the first resist layer R1. At this time, the conductive protrusion 4c is formed on the lower strip-like wiring conductor 4b exposed in the opening of the first resist layer R1 and in the opening of the second resist layer R2, so that the width thereof is the same as that of the first resist layer R1. The width is defined by the opening, that is, the width coincides with the width of the lower strip-shaped wiring conductor 4b.

導電突起４ｃを形成後、図５（ｇ），（ｇ’）に示すように、第一レジスト層Ｒ１および第二レジスト層Ｒ２を除去する。第一レジスト層Ｒ１および第二レジスト層Ｒ２の除去は、例えば水酸化ナトリウム水溶液への浸漬により行なうことができる。   After forming the conductive protrusions 4c, the first resist layer R1 and the second resist layer R2 are removed as shown in FIGS. The removal of the first resist layer R1 and the second resist layer R2 can be performed, for example, by immersion in an aqueous sodium hydroxide solution.

次に、図５（ｈ），（ｈ’）に示すように、下層の帯状配線導体４ｂが形成された部分以外の下地金属層５１を除去する。これにより、隣接する下層の帯状配線導体４ｂ間が電気的に独立することになる。このとき、下層の帯状配線導体４ｂの上に形成された導電突起４ｃは、その幅が下層の帯状配線導体４ｂと一致する幅で形成されており、下層の帯状配線導体４ｂからはみ出すことはないので、隣接する下層の帯状配線導体４ｂ間の電気的な絶縁が良好に保たれる。なお、下層の帯状配線導体４ｂが形成された部分以外の下地金属層５１を除去するには、第一レジスト層Ｒ１および第二レジスト層Ｒ２を除去した後に露出する下地金属層５１を例えば過硫酸ナトリウムあるいは過酸化水素水を含有するエッチング液によりエッチング除去する方法が採用される。   Next, as shown in FIGS. 5H and 5H, the base metal layer 51 other than the portion where the lower strip-shaped wiring conductor 4b is formed is removed. As a result, the adjacent lower layer strip-like wiring conductors 4b are electrically independent. At this time, the conductive protrusion 4c formed on the lower strip-shaped wiring conductor 4b has a width that matches the lower strip-shaped wiring conductor 4b, and does not protrude from the lower strip-shaped wiring conductor 4b. Therefore, the electrical insulation between the adjacent lower layer strip-like wiring conductors 4b is kept good. In order to remove the base metal layer 51 other than the portion where the lower strip-like wiring conductor 4b is formed, the base metal layer 51 exposed after the removal of the first resist layer R1 and the second resist layer R2 is, for example, persulfuric acid. A method of etching away with an etching solution containing sodium or hydrogen peroxide solution is employed.

ついで、図５（ｉ），（ｉ’）に示すように、下層の絶縁樹脂層３および下層の帯状配線導体４ｂおよび導電突起４ｃ上に、粗化面を有する金属箔Ｆの前記粗化面に塗布された半硬化の熱硬化性樹脂材料３Ｐを、金属箔Ｆの粗化面が導電突起４ｃの上面に当接するまで金属箔Ｆ上から圧接して下層の帯状配線導体４ｂおよび導電突起４ｃを熱硬化性樹脂材料３Ｐ中に埋設する。なお、金属箔Ｆとしては、電解銅箔が好適に用いられ、熱硬化性樹脂材料３Ｐとしては、エポキシ樹脂やビスマレイミドトリアジン樹脂等の熱硬化性樹脂となる樹脂組成物に酸化ケイ素粉末等の無機絶縁フィラーを含有させた熱硬化性樹脂材料を金属箔Ｆの粗化面上で半硬化のシート状としたものが使用される。なお、金属箔Ｆとしては、熱硬化性樹脂材料３Ｐが塗布された面が十点平均粗さＲｚで１．０〜８．０μｍの粗化面となっており、この粗化面が導電突起４ｃの上面に当接するまで熱硬化性樹脂材料３Ｐを圧接することにより下層の帯状配線導体４ｂおよび導電突起４ｃが熱硬化性樹脂材料３Ｐ中に良好に埋設されるとともに、導電突起４ｃ上に残存する熱硬化性樹脂材料３Ｐの樹脂残渣を極めて少ないものとすることができる。   Next, as shown in FIGS. 5 (i) and (i ′), the roughened surface of the metal foil F having a roughened surface on the lower insulating resin layer 3, the lower belt-like wiring conductor 4 b and the conductive protrusion 4 c. The semi-cured thermosetting resin material 3P applied to the metal foil F is pressed from above the metal foil F until the roughened surface of the metal foil F comes into contact with the upper surface of the conductive protrusion 4c, and the lower strip-like wiring conductor 4b and conductive protrusion 4c. Is embedded in the thermosetting resin material 3P. As the metal foil F, an electrolytic copper foil is preferably used, and as the thermosetting resin material 3P, a resin composition that becomes a thermosetting resin such as an epoxy resin or a bismaleimide triazine resin, a silicon oxide powder, or the like. A thermosetting resin material containing an inorganic insulating filler in a semi-cured sheet shape on the roughened surface of the metal foil F is used. In addition, as the metal foil F, the surface to which the thermosetting resin material 3P is applied is a roughened surface having a ten-point average roughness Rz of 1.0 to 8.0 μm, and this roughened surface is a conductive protrusion. By pressing the thermosetting resin material 3P until it comes into contact with the upper surface of 4c, the lower strip-shaped wiring conductor 4b and the conductive protrusion 4c are well embedded in the thermosetting resin material 3P and remain on the conductive protrusion 4c. The resin residue of the thermosetting resin material 3P to be made can be made extremely small.

次に、熱硬化性樹脂材料３Ｐを熱硬化させて上層の絶縁樹脂層３とした後、 図５（ｊ），（ｊ’）に示すように、金属箔Ｆをエッチング除去する。このとき、導電突起４ｃの上面には熱硬化性樹脂材料３Ｐが硬化した樹脂残渣が極めて薄い状態で残る。また、上層の絶縁樹脂層３の表面には金属箔Ｆの粗化面に対応した粗化面が形成される。なお、金属箔Ｆのエッチング除去は、例えば金属箔Ｆが銅箔から成る場合であれば、塩化第二銅を含有するエッチング液により行なえばよい。   Next, the thermosetting resin material 3P is thermally cured to form the upper insulating resin layer 3, and then the metal foil F is removed by etching as shown in FIGS. 5 (j) and (j '). At this time, the resin residue obtained by curing the thermosetting resin material 3P remains on the upper surface of the conductive protrusion 4c in an extremely thin state. Further, a roughened surface corresponding to the roughened surface of the metal foil F is formed on the surface of the upper insulating resin layer 3. For example, if the metal foil F is made of a copper foil, the metal foil F may be removed by an etching solution containing cupric chloride.

次に、図６（ｋ），（ｋ’）に示すように、上層の絶縁樹脂層３の表面にプラズマエッチング処理やアルカリ過マンガン酸エッチング処理を施すことにより、導電突起４ｃ上に残っていた樹脂残渣を除去して導電突起４ｃの上面を露出させる。   Next, as shown in FIGS. 6 (k) and (k ′), the surface of the upper insulating resin layer 3 was left on the conductive protrusions 4c by performing plasma etching treatment or alkaline permanganate etching treatment. The resin residue is removed to expose the upper surface of the conductive protrusion 4c.

次に、図６（ｌ），（ｌ’）に示すように、上層の絶縁樹脂層３の表面および露出した導電突起４ｃの上面に、電解めっき用の下地金属層５２を無電解めっきにより被着形成する。下地金属層５２の厚みは０．１〜２μｍ程度である。下地金属層５２としては、下地金属層５１の場合と同様に無電解銅めっきが好ましい。   Next, as shown in FIGS. 6 (l) and (l '), a base metal layer 52 for electrolytic plating is applied to the surface of the upper insulating resin layer 3 and the exposed upper surface of the conductive protrusion 4c by electroless plating. It forms. The thickness of the base metal layer 52 is about 0.1 to 2 μm. As the base metal layer 52, electroless copper plating is preferable as in the case of the base metal layer 51.

図６（ｍ），（ｍ’）に示すように、下地金属層５２の表面に、第三レジスト層Ｒ３を形成する。第三レジスト層Ｒ３は、上層の帯状配線導体４ａに対応する形状の開口を有しており、光感光性アルカリ現像型ドライフィルムレジストを下地金属層５２上に貼着するとともにそれにフォトリソグラフィ技術を用いて露光および現像を行なうことにより上層の帯状配線導体４ａに対応する形状の開口を有するパターンに形成される。また、第三レジスト層Ｒ３の厚みは、上層の帯状配線導体４ａの厚みよりも若干厚い厚みであるのがよい。   As shown in FIGS. 6M and 6M ′, a third resist layer R3 is formed on the surface of the base metal layer 52. The third resist layer R3 has an opening having a shape corresponding to the upper layer strip-like wiring conductor 4a, and a photo-sensitive alkali development type dry film resist is attached onto the base metal layer 52 and photolithography technology is applied thereto. By performing exposure and development using the pattern, a pattern having an opening having a shape corresponding to the upper strip-shaped wiring conductor 4a is formed. The thickness of the third resist layer R3 is preferably slightly thicker than the thickness of the upper strip-shaped wiring conductor 4a.

ついで、図６（ｎ），（ｎ’）に示すように、第三レジスト層Ｒ３の開口内に露出する下地金属層５２上に電解めっきにより上層の帯状配線導体４ａを被着形成する。上層の帯状配線導体４ａを形成するための電解めっきとしては、電解銅めっきが好ましい。ここで、上層の帯状配線導体４ａの厚みは、第三レジスト層Ｒ３より薄くなっている。具体的には、上層の帯状配線導体４ａの厚みは、８〜２０μｍ、好ましくは１０〜１５μｍであるのがよい。また、上層の帯状配線導体４ａの幅は、導電突起４ｃの幅よりも５〜１０μｍ程度広いことが好ましい。   Next, as shown in FIGS. 6 (n) and (n '), the upper layer strip-shaped wiring conductor 4a is deposited on the underlying metal layer 52 exposed in the opening of the third resist layer R3 by electrolytic plating. Electrolytic copper plating is preferable as the electrolytic plating for forming the upper layer strip-like wiring conductor 4a. Here, the thickness of the upper strip-shaped wiring conductor 4a is smaller than that of the third resist layer R3. Specifically, the thickness of the upper-layer strip-shaped wiring conductor 4a is 8 to 20 μm, preferably 10 to 15 μm. Moreover, it is preferable that the width | variety of the strip | belt-shaped wiring conductor 4a of an upper layer is about 5-10 micrometers wider than the width | variety of the conductive protrusion 4c.

上層の帯状配線導体４ａを形成後、図６（ｏ），（ｏ’）に示すように、第三レジスト層Ｒ３を除去する。第三レジスト層Ｒ３の除去は、第一レジスト層Ｒ１および第二レジスト層Ｒ２の場合と同様に、例えば水酸化ナトリウム水溶液への浸漬により行なうことができる。   After forming the upper layer strip-shaped wiring conductor 4a, the third resist layer R3 is removed as shown in FIGS. 6 (o) and (o '). The removal of the third resist layer R3 can be performed, for example, by immersion in an aqueous sodium hydroxide solution, as in the case of the first resist layer R1 and the second resist layer R2.

次に、図７（ｐ），（ｐ’）に示すように、上層の帯状配線導体４ａが形成された部分以外の下地金属層５２を除去する。これにより、隣接する上層の帯状配線導体４ａ間が電気的に独立することになる。上層の帯状配線導体４ａが形成された部分以外の下地金属層５２を除去するには、前記下地金属層５１の場合と同様に、第三レジスト層Ｒ３を除去した後に露出する下地金属層５２を例えば過硫酸ナトリウムあるいは過酸化水素水を含有するエッチング液によりエッチング除去する方法が採用される。   Next, as shown in FIGS. 7 (p) and (p '), the base metal layer 52 other than the portion where the upper band-like wiring conductor 4a is formed is removed. As a result, the adjacent upper layer strip-shaped wiring conductors 4a are electrically independent. In order to remove the base metal layer 52 other than the portion where the upper strip-shaped wiring conductor 4a is formed, the base metal layer 52 exposed after the third resist layer R3 is removed is removed in the same manner as the base metal layer 51. For example, a method of removing by etching with an etching solution containing sodium persulfate or hydrogen peroxide is employed.

このとき、本発明の配線基板の製造方法によれば、上層の帯状配線導体４ａが下層の帯状配線導体４ｂ上に形成された導電突起４ｃを介して下層の帯状配線導体４ｂに接続されることから、半導体素子接続パッド４Ａと下層の帯状配線導体４ｂとを狭いピッチのままで接続することができる。さらに、半導体素子接続パッド４Ａから配線基板１０の外周側や中央側に向けて延びる引き出し部４ａ’を上層の絶縁樹脂層３に形成された図示しないビアホール８を介して下層の配線導体４に接続することで、半導体素子接続パッド４Ａと他の層の配線導体４とを接続するための設計自由度を高いものとすることができる。   At this time, according to the method for manufacturing a wiring board of the present invention, the upper layer strip conductor 4a is connected to the lower strip conductor 4b through the conductive protrusion 4c formed on the lower strip conductor 4b. Therefore, the semiconductor element connection pad 4A and the lower strip-shaped wiring conductor 4b can be connected with a narrow pitch. Further, a lead portion 4a ′ extending from the semiconductor element connection pad 4A toward the outer peripheral side or the center side of the wiring substrate 10 is connected to the lower wiring conductor 4 through a via hole 8 (not shown) formed in the upper insulating resin layer 3. As a result, the degree of freedom in design for connecting the semiconductor element connection pads 4A and the wiring conductors 4 of other layers can be increased.

最後に、図７（ｑ），（ｑ’）に示すように、上層の絶縁樹脂層３および上層の帯状配線導体４ａ上に、半導体素子接続パッド４Ａを露出させるスリット状の開口を有するソルダーレジスト層５を形成する。ソルダーレジスト層５は、例えば光感光性を有するアクリル変性エポキシ樹脂のフィルムを上層の絶縁樹脂層３および上層の帯状配線導体４ａ上に貼着するとともにそのフィルムをフォトリソグラフィ技術を採用して前記開口を有する所定のパターンに露光および現像した後、熱硬化および紫外線硬化させることにより形成される。かくして、本発明の配線基板の製造方法によれば、小型で高密度の配線基板を提供することができる。   Finally, as shown in FIGS. 7 (q) and 7 (q '), a solder resist having slit-like openings exposing the semiconductor element connection pads 4A on the upper insulating resin layer 3 and the upper strip-like wiring conductor 4a. Layer 5 is formed. The solder resist layer 5 is formed by, for example, adhering a photo-sensitive acrylic modified epoxy resin film on the upper insulating resin layer 3 and the upper strip-shaped wiring conductor 4a and using the photolithography technique to apply the film to the opening. It is formed by exposing and developing a predetermined pattern having a heat curing and ultraviolet curing. Thus, according to the method for manufacturing a wiring board of the present invention, a small and high-density wiring board can be provided.

３ 絶縁樹脂層
３Ｐ 熱硬化性樹脂材料
４ａ 上層の帯状配線導体
４ａ’ 引き出し部
４Ａ 半導体素子接続パッド
４ｂ 下層の帯状配線導体
４ｃ 導電突起
１０１ 半導体素子
Ｆ 金属箔 DESCRIPTION OF SYMBOLS 3 Insulating resin layer 3P Thermosetting resin material 4a Upper strip | belt-shaped wiring conductor 4a 'Lead part 4A Semiconductor element connection pad 4b Lower strip | belt-shaped wiring conductor 4c Conductive protrusion 101 Semiconductor element F Metal foil

Claims (2)

下層の絶縁樹脂層と、該下層の絶縁樹脂層上に複数並んで形成された下層の帯状配線導体と、該下層の帯状配線導体を埋設する上層の絶縁樹脂層と、前記下層の帯状配線導体上に該下層の帯状配線導体の幅と一致する幅で横に一列に並ぶように形成されており、上面が前記上層の絶縁樹脂層から露出する導電突起と、該導電突起および前記上層の絶縁樹脂層上に形成されており、半導体素子の電極端子が接続される複数の半導体素子接続パッドを各前記導電突起上に有する複数の上層の帯状配線導体とを具備し、前記上層の帯状配線導体の一部は、前記半導体素子接続パッドから該半導体素子接続パッドの並びの両側の少なくとも一方に向けて延びる引き出し部を有していることを特徴とする配線基板。   A lower insulating resin layer; a plurality of lower layer wiring conductors formed side by side on the lower insulating resin layer; an upper insulating resin layer in which the lower band wiring conductor is embedded; and the lower band wiring conductor A conductive protrusion whose upper surface is exposed from the upper insulating resin layer, the upper surface of the conductive protrusion and the upper layer being insulated; A plurality of upper layer strip-shaped wiring conductors formed on the resin layer and having a plurality of semiconductor element connection pads on each of the conductive protrusions to which electrode terminals of the semiconductor elements are connected, and the upper layer strip-shaped wiring conductor A part of the wiring board has a lead portion extending from the semiconductor element connection pad toward at least one of both sides of the array of the semiconductor element connection pads. 下層の絶縁樹脂層上に下層の帯状配線導体を複数並べて形成するとともに該下層の帯状配線導体上に導電突起を前記下層の帯状配線導体の幅と一致する幅で形成する工程と、粗化面を有する金属箔の前記粗化面上に塗布された半硬化の熱硬化性樹脂材料を、前記下層の絶縁樹脂層および前記下層の帯状配線導体および前記導電突起上に、前記金属箔の前記粗化面が前記導電突起上面に当接するまで前記金属箔上から圧接して前記下層の帯状配線導体および前記導電突起を前記熱硬化性樹脂材料中に埋設するとともに、前記熱硬化性樹脂材料を熱硬化させて該熱硬化性樹脂材料の硬化物から成る上層の絶縁樹脂層を形成する工程と、前記上層の絶縁樹脂層の表面から前記金属箔をエッチング除去するとともに前記導電突起上に残る前記熱硬化性樹脂材料の残渣を除去する工程と、前記導電突起上および前記上層の絶縁樹脂層上に上層の帯状配線導体を、前記導電突起上に半導体素子接続パッドを有するように形成する工程とを行うことを特徴とする配線基板の製造方法。   Forming a plurality of lower strip-shaped wiring conductors on the lower insulating resin layer side by side and forming conductive protrusions on the lower strip-shaped wiring conductor with a width matching the width of the lower strip-shaped wiring conductor; and a roughened surface A semi-cured thermosetting resin material applied on the roughened surface of the metal foil having the metal foil on the roughened insulating resin layer, the lower-layer strip-shaped wiring conductor, and the conductive protrusions. The lower surface strip-shaped wiring conductor and the conductive protrusion are embedded in the thermosetting resin material by pressing from above the metal foil until the conversion surface contacts the upper surface of the conductive protrusion, and the thermosetting resin material is heated. A step of curing to form an upper insulating resin layer made of a cured product of the thermosetting resin material; and removing the metal foil from the surface of the upper insulating resin layer by etching and the heat remaining on the conductive protrusions Curability Performing a step of removing a residue of the fat material, and a step of forming an upper band-like wiring conductor on the conductive protrusion and the upper insulating resin layer so as to have a semiconductor element connection pad on the conductive protrusion. A method of manufacturing a wiring board, characterized in that
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Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5662398A (en) * 1979-10-26 1981-05-28 Nippon Electric Co Method of manufacturing high density multilayer board
JPH0423390A (en) * 1990-05-18 1992-01-27 Internatl Business Mach Corp <Ibm> Manufacture of multilayer wiring board
JPH0455167U (en) * 1990-09-17 1992-05-12
JP2000294930A (en) * 1999-04-06 2000-10-20 Mitsubishi Electric Corp Manufacture of multilayer printed circuit board and semiconductor device using the multilayer printed circuit board
JP2001284783A (en) * 2000-03-30 2001-10-12 Shinko Electric Ind Co Ltd Substrate for surface-mounting and surface-mounting structure
JP2002094243A (en) * 2000-09-18 2002-03-29 Toagosei Co Ltd Method for manufacturing multi-layer printed wiring board
JP2005159261A (en) * 2003-10-31 2005-06-16 Sankyo Kasei Co Ltd Circuit substrate for solid configuration

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5662398A (en) * 1979-10-26 1981-05-28 Nippon Electric Co Method of manufacturing high density multilayer board
JPH0423390A (en) * 1990-05-18 1992-01-27 Internatl Business Mach Corp <Ibm> Manufacture of multilayer wiring board
JPH0455167U (en) * 1990-09-17 1992-05-12
JP2000294930A (en) * 1999-04-06 2000-10-20 Mitsubishi Electric Corp Manufacture of multilayer printed circuit board and semiconductor device using the multilayer printed circuit board
JP2001284783A (en) * 2000-03-30 2001-10-12 Shinko Electric Ind Co Ltd Substrate for surface-mounting and surface-mounting structure
JP2002094243A (en) * 2000-09-18 2002-03-29 Toagosei Co Ltd Method for manufacturing multi-layer printed wiring board
JP2005159261A (en) * 2003-10-31 2005-06-16 Sankyo Kasei Co Ltd Circuit substrate for solid configuration

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