JP2011086648A - 半導体装置および半導体装置の製造方法 - Google Patents
半導体装置および半導体装置の製造方法 Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 204
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 39
- 239000000758 substrate Substances 0.000 claims abstract description 129
- 238000000034 method Methods 0.000 claims abstract description 96
- 239000012535 impurity Substances 0.000 claims description 17
- 238000005530 etching Methods 0.000 claims description 12
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 6
- 229910052710 silicon Inorganic materials 0.000 claims description 6
- 239000010703 silicon Substances 0.000 claims description 6
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 claims description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 2
- 229910002601 GaN Inorganic materials 0.000 claims 1
- 229910010271 silicon carbide Inorganic materials 0.000 claims 1
- 238000000576 coating method Methods 0.000 abstract description 16
- 239000011248 coating agent Substances 0.000 abstract description 14
- 230000015572 biosynthetic process Effects 0.000 abstract description 9
- 239000010408 film Substances 0.000 description 113
- 238000009792 diffusion process Methods 0.000 description 22
- 238000005468 ion implantation Methods 0.000 description 22
- 230000005684 electric field Effects 0.000 description 20
- 229910052796 boron Inorganic materials 0.000 description 19
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 15
- 230000015556 catabolic process Effects 0.000 description 13
- 238000000206 photolithography Methods 0.000 description 13
- 238000001312 dry etching Methods 0.000 description 10
- 238000004088 simulation Methods 0.000 description 9
- 229910018125 Al-Si Inorganic materials 0.000 description 8
- 229910018520 Al—Si Inorganic materials 0.000 description 8
- 230000000052 comparative effect Effects 0.000 description 7
- 230000000694 effects Effects 0.000 description 7
- 238000002513 implantation Methods 0.000 description 7
- HAYXDMNJJFVXCI-UHFFFAOYSA-N arsenic(5+) Chemical compound [As+5] HAYXDMNJJFVXCI-UHFFFAOYSA-N 0.000 description 6
- -1 boron ions Chemical class 0.000 description 6
- 230000003647 oxidation Effects 0.000 description 6
- 238000007254 oxidation reaction Methods 0.000 description 6
- 238000009826 distribution Methods 0.000 description 4
- 238000004544 sputter deposition Methods 0.000 description 4
- 239000012141 concentrate Substances 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- 238000002474 experimental method Methods 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- 230000001133 acceleration Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000012423 maintenance Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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Abstract
【解決手段】本発明に係る半導体装置は、半導体基板7表面に、電極層8およびリセス部12が形成されている。さらに、半導体基板7内には、リセス部12の底面および電極層8と接触する、リサーフ層が形成されている。また、リセス部12を充填するように、半導体基板7の上面13に絶縁膜15が形成される。また、リセス部12の上方における絶縁膜15上に、フィールドプレート電極11が形成される。
【選択図】図1
Description
図1は、実施の形態1に係る高耐圧型半導体装置(ダイオード)の接合終端部の構成を示す断面図である。
図10は、リサーフ層9の深さと高耐圧型半導体装置の耐圧(600Vクラス)との相関を示す、シミュレーション結果である。
上記において、半導体基板7の上面13と絶縁膜15の上面との間における段差が大きくなると、当該段差においてレジストを塗布するとき、レジスト塗布ムラが発生することに言及した。図18は、当該段差に起因したレジスト塗布ムラの発生を示す実験結果である。図18に示す実験結果は、複数種類の上記段差を形成し、各段差毎にレジスト塗布ムラ発生の有無を調査した結果である。
図19に示すように、本発明に係る半導体装置において、フィールドプレート電極11を接地電位とし、半導体基板7の下面29に対して600Vを印加したとする。ここで、図20の拡大断面図が示すように、リセス部12の側面部は、テーパー形状でないとする。つまり、リセス部12の底面に対してリセス部12の側面部が垂直に形成されているとする。この場合には、リセス部12、電極層8およびリサーフ層9周辺の領域では、図21に示す電界分布が形成される。図21は、上記電圧印加および図19,20の構成を想定した、シミュレーション結果である。
本実施の形態では、実施の形態4で説明した側面部がテーパー形状を有するリセス部12(図22の参照)の形成方法について、拡大工程断面図を用いて説明する。なお、各拡大工程断面図は、形成されるリセス部12の側面部周辺を拡大図示している。
リセス部12の底面部とリセス部12の側面部とが接続するコーナ部では、半導体基板7内に生じる電界が集中しやすくなる。したがって、当該コーナ部における電界緩和が、半導体装置の安定的な耐圧保持につながる。
実施の形態6で説明したように、リセス部12の底面部と接続するコーナ部では、半導体基板7内に生じる電界が集中しやすくなる。そこで、本実施の形態では、リセス部12の底面と接続するコーナ部は、電極層8により覆われている。図28は、本実施の形態に係る半導体装置の構成を示す拡大断面図である。
実施の形態6、7で説明したように、リセス部12の底面部と接続するコーナ部では、半導体基板7内に生じる電界が集中しやすくなる。そこで、本実施の形態では、平面視において、フィールドプレート電極11は、リセス部12の底面と接続するコーナ部35を完全に覆うように形成されている。図30は、本実施の形態に係る半導体装置の構成を示す拡大断面図である。
Claims (11)
- 第一の導電型を有し、リセス部が形成された上面を有する半導体基板と、
第二の導電型を有し、前記リセス部に隣接して前記半導体基板の表面内に形成される電極層と、
前記電極層よりも濃度が低い前記第二の導電型の不純物を有し、前記リセス部の底面および前記電極層と接触するように前記半導体基板内に形成される、リサーフ層と、
前記リセス部を充填するように、前記半導体基板の上面に形成される絶縁膜と、
前記リセス部の上方における前記絶縁膜上に形成されるフィールドプレート電極とを、備えている、
ことを特徴とする半導体装置。 - 前記リセス部内に形成された前記絶縁膜の厚さは、
1μm以上である、
ことを特徴とする請求項1に記載の半導体装置。 - 前記リセス部の側面部は、
テーパー形状を有している、
ことを特徴とする請求項1に記載の半導体装置。 - 前記リセス部の底面と接続するコーナ部は、
丸みを帯びている、
ことを特徴とする請求項1に記載の半導体装置。 - 前記リセス部の底面と接続するコーナ部は、
前記電極層により覆われている、
ことを特徴とする請求項1に記載の半導体装置。 - 前記フィールドプレート電極は、
平面視において、前記リセス部の底面と接続するコーナ部を覆うように形成されている、
ことを特徴とする請求項1に記載の半導体装置。 - 前記半導体基板は、
シリコン、炭化シリコン、または窒化ガリウムを含む、
ことを特徴とする請求項1に記載の半導体装置。 - (A)第一の導電型を有する半導体基板の表面に、リセス部を形成する工程と、
(B)半導体基板に第二の導電型の不純物を導入することにより、前記リセス部に隣接することとなる電極層を前記半導体基板の表面内に形成する工程と、
(C)前記電極層よりも濃度が低い前記第二の導電型の不純物を前記半導体基板に導入することにより、前記リセスの底面および前記電極層と接触することとなるリサーフ層を、前記半導体基板内に形成する工程と、
(D)前記リセス部を充填するように、絶縁膜を形成する工程と、
(E)前記リセス部上方における前記絶縁膜上に、フィールドプレート電極を形成する工程とを、備えている、
ことを特徴とする半導体装置の製造方法。 - 前記工程(C)は、
前記工程(A)の後に、前記リセス部の底面に対して、前記不純物を導入することにより、前記リサーフ層を形成する工程である、
ことを特徴とする請求項8に記載の半導体装置の製造方法。 - 前記工程(A)は、
(A−1)前記半導体基板の上面に、側面部がテーパー形状である開口部を有するレジストを形成する工程と、
(A−2)前記レジストをマスクとして使用して、前記半導体基板をエッチングすることにより、前記リセス部を形成する工程とを、備えている、
ことを特徴とする請求項8に記載の半導体装置の製造方法。 - 前記工程(A−2)は、
前記レジストに対する前記半導体基板のエッチング選択比が、1である条件で、前記エッチングを行う工程である、
ことを特徴とする請求項10に記載の半導体装置の製造方法。
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CN109411530A (zh) * | 2018-11-30 | 2019-03-01 | 中国振华集团永光电子有限公司(国营第八七三厂) | 一种电力电子半导体芯片终端结构及其制造方法 |
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JP6168961B2 (ja) | 2013-10-10 | 2017-07-26 | 三菱電機株式会社 | 半導体装置 |
CN105405869A (zh) * | 2015-11-25 | 2016-03-16 | 电子科技大学 | 浅沟槽结终端扩展结构 |
US9653556B1 (en) * | 2016-02-29 | 2017-05-16 | Toshiba Corporation | Field plate for high-voltage field effect transistors |
US10861931B2 (en) * | 2016-12-08 | 2020-12-08 | Cree, Inc. | Power semiconductor devices having gate trenches and buried edge terminations and related methods |
CN107464835A (zh) * | 2017-07-03 | 2017-12-12 | 成都迈斯派尔半导体有限公司 | 一种半导体功率器件及其终端结构 |
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