JP2011082287A - 半導体装置及びその製造方法 - Google Patents
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 30
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- 238000001764 infiltration Methods 0.000 description 5
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- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 4
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 239000004020 conductor Substances 0.000 description 4
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
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Abstract
【解決手段】支持体10に、接続電極20aを支持体10側に向けて半導体チップ20を仮固定する工程と、支持体10及び半導体チップ20の上に、半導体チップ20を被覆する樹脂染込防止用絶縁層30を形成する工程と、樹脂染込防止用絶縁層30の上に、半導体チップ20の周囲及び背面側を封止する樹脂基板50を形成する工程と、支持体10を除去することにより、半導体チップ20の接続電極20aを露出させる工程とを含む。半導体チップ20の接続電極20aにビルドアップ配線BWが直接接続される。
【選択図】図5
Description
本発明の実施形態を説明する前に、本発明に関連する関連技術の問題点について説明する。図1及び図2は関連技術の半導体装置の製造方法を示す図である。
図3〜図8は本発明の実施形態の半導体装置の製造方法を示す図である。本発明の半導体装置は半導体パッケージとも呼称される。
Claims (10)
- 支持体に、半導体チップの接続電極を前記支持体側に向けて前記半導体チップを仮固定する工程と、
前記支持体及び前記半導体チップの上に、前記半導体チップを被覆する樹脂染込防止用絶縁層を形成する工程と、
前記樹脂染込防止用絶縁層の上に、前記半導体チップの周囲及び背面側を封止する樹脂基板を形成する工程と、
前記支持体を除去することにより、前記半導体チップの接続電極を露出させる工程とを有することを特徴とする半導体装置の製造方法。 - 前記支持体を除去する工程の後に、
前記半導体チップの表面及び前記樹脂染込防止用絶縁層の上に、前記半導体チップの前記接続電極に直接接続される配線層を形成する工程をさらに有することを特徴とする請求項1に記載の半導体装置の製造方法。 - 前記支持体に前記半導体チップを仮固定する工程において、
前記支持体の上に粘着シートを介して前記半導体チップを仮固定し、
前記支持体を除去した後に、前記粘着シートを引き剥がすことを特徴とする請求項1又は2に記載の半導体装置の製造方法。 - 前記支持体に前記半導体チップを仮固定する工程において、
前記支持体の上に複数の前記半導体チップを配置し、
前記配線層を形成する工程の後に、
前記複数の半導体チップの境界部を切断することにより、個々の半導体装置を得る工程をさらに有することを特徴とする請求項2に記載の半導体装置の製造方法。 - 前記樹脂染込防止用絶縁層を形成する工程は、
半硬化状態の熱硬化性の樹脂シートを前記支持体及び前記半導体チップの上に真空雰囲気で貼付し、加熱処理することにより、前記樹脂シートを硬化させる工程であること特徴とする請求項1又は2に記載の半導体装置の製造方法。 - 前記樹脂基板を形成する工程は、
前記樹脂染込防止用絶縁層の上に熱硬化性の粉末樹脂又は液状樹脂を形成し、加圧/加熱処理によって硬化させる工程であることを特徴とする請求項1又は2に記載の半導体装置の製造方法。 - 前記支持体は金属板からなり、
前記支持体を除去する工程において、前記金属板をウェットエッチングによって除去することを特徴とする請求項1又は2に記載の半導体装置の製造方法。 - 表面側に接続電極を備えた半導体チップと、
前記半導体チップの背面及び側面を被覆し、かつ前記半導体チップの前記側面の上部から周囲に延在する樹脂染込防止用絶縁層と、
前記樹脂染込防止用絶縁層の下に形成され、前記前記半導体チップの周囲及び背面側を封止する樹脂基板とを有することを特徴とする半導体装置。 - 前記半導体チップ及び前記樹脂染込防止用絶縁層の上に形成され、前記半導体チップの接続電極に接続された配線層をさらに有することを特徴とする請求項8に記載の半導体装置。
- 前記樹脂染込防止用絶縁層は、熱硬化性の樹脂シートから形成され、
前記樹脂基板は、熱硬化性の粉末樹脂又は液状樹脂から形成されることを特徴とする請求項8に記載の半導体装置。
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JP2009232163A JP5325736B2 (ja) | 2009-10-06 | 2009-10-06 | 半導体装置及びその製造方法 |
US12/897,085 US8293576B2 (en) | 2009-10-06 | 2010-10-04 | Semiconductor device and method of manufacturing the same |
US13/584,115 US8536715B2 (en) | 2009-10-06 | 2012-08-13 | Semiconductor device and method of manufacturing the same |
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Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2013038300A (ja) * | 2011-08-10 | 2013-02-21 | Fujitsu Ltd | 電子装置及びその製造方法 |
JP2013187434A (ja) * | 2012-03-09 | 2013-09-19 | Fujitsu Ltd | 半導体装置、半導体装置の製造方法、電子装置及び基板 |
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US20120306100A1 (en) | 2012-12-06 |
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