JP2011023627A - Semiconductor device and method of manufacturing the same - Google Patents

Semiconductor device and method of manufacturing the same Download PDF

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JP2011023627A
JP2011023627A JP2009168597A JP2009168597A JP2011023627A JP 2011023627 A JP2011023627 A JP 2011023627A JP 2009168597 A JP2009168597 A JP 2009168597A JP 2009168597 A JP2009168597 A JP 2009168597A JP 2011023627 A JP2011023627 A JP 2011023627A
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substrate
wiring layer
layer
insulating layer
semiconductor device
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JP2011023627A5 (en
JP5426261B2 (en
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Michio Horiuchi
道夫 堀内
Yasue Tokutake
安衛 徳武
Yuichi Matsuda
勇一 松田
Tomoo Yamazaki
智生 山崎
Yuta Sakaguchi
勇太 坂口
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Shinko Electric Industries Co Ltd
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Shinko Electric Industries Co Ltd
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    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device that has high reliability in connection between semiconductor elements and substrates and is capable of performing high-density packaging, and to provide a method of manufacturing the semiconductor device. <P>SOLUTION: The semiconductor device 10 includes: the substrate 13 including a plurality of conductors 12 passing through from one surface 13a to the other surface 13b; a first insulating layer 16a that is formed on one surface 13a of the substrate 13 and incorporates a semiconductor element 14; a first wiring layer 17a formed on the first insulating layer 16a and electrically connected to one portion of a plurality of conductors 12 exposed from one surface 13a of the substrate 13 and to the semiconductor element 14 via through-holes 16x, 16y provided in the first insulating layer 16a; a second insulating layer 16b formed on the other surface 13b of the substrate 13; and a second wiring layer 17b formed on the second insulating layer 16b and electrically connected to one portion of the plurality of conductors 12 exposed from the other surface 13b of the substrate 13 via a through-hole 16z provided in the second insulating layer 16b. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

本発明は、半導体素子と基板とを含んで構成された半導体装置及びその製造方法に関する。   The present invention relates to a semiconductor device including a semiconductor element and a substrate and a method for manufacturing the same.

従来から、基板上に半導体素子を実装した半導体装置が知られている。以下、図１を参照しながら、基板上に半導体素子を実装した従来の半導体装置について説明する。図１は、基板上に半導体素子を実装した従来の半導体装置を例示する断面図である。図１を参照するに、半導体装置３００は、多層基板５００と、半導体素子４００と、はんだバンプ４１０と、アンダーフィル樹脂層４２０とを有する。多層基板５００の中心部には、支持体５１０が設けられている。   Conventionally, a semiconductor device in which a semiconductor element is mounted on a substrate is known. A conventional semiconductor device in which a semiconductor element is mounted on a substrate will be described below with reference to FIG. FIG. 1 is a cross-sectional view illustrating a conventional semiconductor device in which a semiconductor element is mounted on a substrate. Referring to FIG. 1, the semiconductor device 300 includes a multilayer substrate 500, a semiconductor element 400, a solder bump 410, and an underfill resin layer 420. A support 510 is provided at the center of the multilayer substrate 500.

支持体５１０の第１主面５１０ａ上には、第１配線層６１０ａが形成されている。又、支持体５１０には、第１主面５１０ａから第２主面５１０ｂに貫通するスルービア６９０が形成されている。第１配線層６１０ａは、スルービア６９０を介して後述する第４配線層６１０ｂと電気的に接続されている。更に、第１配線層６１０ａを覆うように第１絶縁層５２０ａが形成されており、第１絶縁層５２０ａ上には、第２配線層６２０ａが形成されている。第１配線層６１０ａと第２配線層６２０ａとは、第１絶縁層５２０ａを貫通するビアホール５２０ｘを介して電気的に接続されている。   A first wiring layer 610 a is formed on the first main surface 510 a of the support 510. The support 510 is formed with a through via 690 penetrating from the first main surface 510a to the second main surface 510b. The first wiring layer 610a is electrically connected to a later-described fourth wiring layer 610b via a through via 690. Further, a first insulating layer 520a is formed so as to cover the first wiring layer 610a, and a second wiring layer 620a is formed on the first insulating layer 520a. The first wiring layer 610a and the second wiring layer 620a are electrically connected through a via hole 520x that penetrates the first insulating layer 520a.

更に、第２配線層６２０ａを覆うように第２絶縁層５３０ａが形成されている。第２絶縁層５３０ａ上には、第３配線層６３０ａが形成されている。第２配線層６２０ａと第３配線層６３０ａとは、第２絶縁層５３０ａを貫通するビアホール５３０ｘを介して電気的に接続されている。   Further, a second insulating layer 530a is formed so as to cover the second wiring layer 620a. A third wiring layer 630a is formed on the second insulating layer 530a. The second wiring layer 620a and the third wiring layer 630a are electrically connected through a via hole 530x that penetrates the second insulating layer 530a.

更に、第３配線層６３０ａを覆うように、開口部５５０ｘを有するソルダーレジスト膜５５０ａが形成されている。第３配線層６３０ａのソルダーレジスト膜５５０ａの開口部５５０ｘから露出する部分は、電極パッドとして機能する（以降、第３配線層６３０ａのソルダーレジスト膜５５０ａの開口部５５０ｘから露出する部分を電極パッド６３０ａという場合がある）。以降、電極パッド６３０ａが形成されている面を、多層基板５００の第１主面という場合がある。   Further, a solder resist film 550a having an opening 550x is formed so as to cover the third wiring layer 630a. The portion exposed from the opening 550x of the solder resist film 550a of the third wiring layer 630a functions as an electrode pad (hereinafter, the portion exposed from the opening 550x of the solder resist film 550a of the third wiring layer 630a is the electrode pad 630a). Sometimes). Hereinafter, the surface on which the electrode pad 630a is formed may be referred to as a first main surface of the multilayer substrate 500.

支持体５１０の第２主面５１０ｂ上には、第４配線層６１０ｂが形成され、更に、第４配線層６１０ｂを覆うように第３絶縁層５２０ｂが形成されている。第３絶縁層５２０ｂ上には、第５配線層６２０ｂが形成されている。第４配線層６１０ｂと第５配線層６２０ｂとは、第３絶縁層５２０ｂを貫通するビアホール５２０ｙを介して電気的に接続されている。   A fourth wiring layer 610b is formed on the second main surface 510b of the support 510, and a third insulating layer 520b is formed so as to cover the fourth wiring layer 610b. A fifth wiring layer 620b is formed on the third insulating layer 520b. The fourth wiring layer 610b and the fifth wiring layer 620b are electrically connected through a via hole 520y that penetrates the third insulating layer 520b.

更に、第５配線層６２０ｂを覆うように第４絶縁層５３０ｂが形成されている。第４絶縁層５３０ｂ上には、第６配線層６３０ｂが形成されている。第５配線層６２０ｂと第６配線層６３０ｂとは、第４絶縁層５３０ｂを貫通するビアホール５３０ｙを介して電気的に接続されている。   Further, a fourth insulating layer 530b is formed so as to cover the fifth wiring layer 620b. A sixth wiring layer 630b is formed on the fourth insulating layer 530b. The fifth wiring layer 620b and the sixth wiring layer 630b are electrically connected through a via hole 530y that penetrates the fourth insulating layer 530b.

更に、第６配線層６３０ｂを覆うように、開口部５５０ｙを有するソルダーレジスト膜５５０ｂが形成されている。第６配線層６３０ｂのソルダーレジスト膜５５０ｂの開口部５５０ｙから露出する部分は、電極パッドとして機能する（以降、第６配線層６３０ｂのソルダーレジスト膜５５０ｂの開口部５５０ｙから露出する部分を電極パッド６３０ｂという場合がある）。以降、電極パッド６３０ｂが形成されている面を、多層基板５００の第２主面という場合がある。   Further, a solder resist film 550b having an opening 550y is formed so as to cover the sixth wiring layer 630b. The portion of the sixth wiring layer 630b exposed from the opening 550y of the solder resist film 550b functions as an electrode pad (hereinafter, the portion of the sixth wiring layer 630b exposed from the opening 550y of the solder resist film 550b is the electrode pad 630b). Sometimes). Hereinafter, the surface on which the electrode pad 630b is formed may be referred to as a second main surface of the multilayer substrate 500.

一部の電極パッド６３０ｂ上には、はんだバンプ６８０が形成されている。はんだバンプ６８０は、半導体装置３００を回路基板（図示せず）に実装する際に、回路基板の対応する端子と電気的に接続される外部接続端子として機能する。又、一部の電極パッド６３０ｂ上には、チップコンデンサ１００が実装されている。電極パッド６３０ｂとチップコンデンサ１００の外部電極２６０ａ及び２６０ｂとは電気的に接続されている。   Solder bumps 680 are formed on some of the electrode pads 630b. The solder bump 680 functions as an external connection terminal that is electrically connected to a corresponding terminal of the circuit board when the semiconductor device 300 is mounted on a circuit board (not shown). A chip capacitor 100 is mounted on some electrode pads 630b. The electrode pad 630b and the external electrodes 260a and 260b of the chip capacitor 100 are electrically connected.

多層基板５００の第１主面上には半導体素子４００が実装されている。半導体素子４００は、シリコン等からなる薄板化された半導体基板（図示せず）上に半導体集積回路（図示せず）や電極パッド（図示せず）が形成されたものである。半導体素子４００の電極パッド（図示せず）上には、はんだバンプ４１０が形成されている。   A semiconductor element 400 is mounted on the first main surface of the multilayer substrate 500. The semiconductor element 400 includes a semiconductor integrated circuit (not shown) and electrode pads (not shown) formed on a thinned semiconductor substrate (not shown) made of silicon or the like. Solder bumps 410 are formed on electrode pads (not shown) of the semiconductor element 400.

半導体素子４００の電極パッド（図示せず）は、はんだバンプ４１０により、多層基板５００の対応する電極パッド６３０ａと電気的に接続されている。はんだバンプ４１０の材料としては、例えばＳｎとＣｕの合金、ＳｎとＡｇの合金、ＳｎとＡｇとＣｕの合金等を用いることができる。半導体素子４００と多層基板５００のソルダーレジスト膜５５０ａとの間には、アンダーフィル樹脂層４２０が充填されている。   Electrode pads (not shown) of the semiconductor element 400 are electrically connected to corresponding electrode pads 630 a of the multilayer substrate 500 by solder bumps 410. As a material of the solder bump 410, for example, an alloy of Sn and Cu, an alloy of Sn and Ag, an alloy of Sn, Ag, and Cu can be used. An underfill resin layer 420 is filled between the semiconductor element 400 and the solder resist film 550 a of the multilayer substrate 500.

又、従来から、基板に半導体素子を内蔵した半導体装置が知られている。以下、図２を参照しながら、基板に半導体素子を内蔵した従来の半導体装置について説明する。図２は、基板に半導体素子を内蔵した従来の半導体装置を例示する断面図である。図２を参照するに、半導体装置７００は、多層基板８００と、半導体素子４５０とを有する。半導体素子４５０は、樹脂８１０に埋め込まれている。半導体素子４５０及び樹脂８１０の一方の面には第１絶縁層８２０が形成されており、第１絶縁層８２０上には、第１配線層９１０が形成されている。第１配線層９１０と半導体素子４５０の電極パッド（図示せず）とは、第１絶縁層８２０を貫通するビアホール８２０ｘを介して電気的に接続されている。すなわち、半導体素子４５０と多層基板８００との電気的接続にバンプを用いていない。   Conventionally, a semiconductor device in which a semiconductor element is built in a substrate is known. Hereinafter, a conventional semiconductor device in which a semiconductor element is built in a substrate will be described with reference to FIG. FIG. 2 is a cross-sectional view illustrating a conventional semiconductor device in which a semiconductor element is built in a substrate. Referring to FIG. 2, the semiconductor device 700 includes a multilayer substrate 800 and a semiconductor element 450. The semiconductor element 450 is embedded in the resin 810. A first insulating layer 820 is formed on one surface of the semiconductor element 450 and the resin 810, and a first wiring layer 910 is formed on the first insulating layer 820. The first wiring layer 910 and an electrode pad (not shown) of the semiconductor element 450 are electrically connected via a via hole 820 x that penetrates the first insulating layer 820. That is, bumps are not used for electrical connection between the semiconductor element 450 and the multilayer substrate 800.

更に、第１配線層９１０を覆うように第２絶縁層８３０が形成されており、第２絶縁層８３０上には、第２配線層９２０が形成されている。第１配線層９１０と第２配線層９２０とは、第２絶縁層８３０を貫通するビアホール８３０ｘを介して電気的に接続されている。   Further, a second insulating layer 830 is formed so as to cover the first wiring layer 910, and a second wiring layer 920 is formed on the second insulating layer 830. The first wiring layer 910 and the second wiring layer 920 are electrically connected via a via hole 830x that penetrates the second insulating layer 830.

更に、第２配線層９２０を覆うように第３絶縁層８４０が形成されている。第３絶縁層８４０上には、第３配線層９３０が形成されている。第２配線層９２０と第３配線層９３０とは、第３絶縁層８４０を貫通するビアホール８４０ｘを介して電気的に接続されている。   Further, a third insulating layer 840 is formed so as to cover the second wiring layer 920. A third wiring layer 930 is formed on the third insulating layer 840. The second wiring layer 920 and the third wiring layer 930 are electrically connected via a via hole 840x that penetrates the third insulating layer 840.

更に、第３配線層９３０を覆うように、開口部８５０ｘを有するソルダーレジスト膜８５０が形成されている。第３配線層９３０のソルダーレジスト膜８５０の開口部８５０ｘから露出する部分は、電極パッドとして機能する（以降、第３配線層９３０のソルダーレジスト膜８５０の開口部８５０ｘから露出する部分を電極パッド９３０という場合がある）。電極パッド９３０上には、はんだバンプ９８０が形成されている。はんだバンプ９８０は、半導体装置７００を回路基板（図示せず）に実装する際に、回路基板の対応する端子と電気的に接続される外部接続端子として機能する。   Further, a solder resist film 850 having an opening 850x is formed so as to cover the third wiring layer 930. The portion exposed from the opening 850x of the solder resist film 850 of the third wiring layer 930 functions as an electrode pad (hereinafter, the portion exposed from the opening 850x of the solder resist film 850 of the third wiring layer 930 is the electrode pad 930). Sometimes). Solder bumps 980 are formed on the electrode pads 930. The solder bump 980 functions as an external connection terminal that is electrically connected to a corresponding terminal of the circuit board when the semiconductor device 700 is mounted on a circuit board (not shown).

特開平１０−３０８５６５号公報JP-A-10-308565

しかしながら、基板上に半導体素子を実装した従来の半導体装置３００では、半導体素子４００と多層基板５００とを電気的に接続するはんだバンプ４１０部分の接続信頼性が低いという問題があった。具体的には、半導体素子４００と多層基板５００との熱膨脹係数の違いに起因する応力破壊や、エレクトロマイグレーションに起因する断線等である。   However, the conventional semiconductor device 300 in which the semiconductor element is mounted on the substrate has a problem that the connection reliability of the solder bump 410 portion that electrically connects the semiconductor element 400 and the multilayer substrate 500 is low. Specifically, stress breakdown due to the difference in thermal expansion coefficient between the semiconductor element 400 and the multilayer substrate 500, disconnection due to electromigration, and the like.

又、基板に半導体素子を内蔵した従来の半導体装置７００では、半導体素子４５０と多層基板８００との電気的接続にバンプを用いていないため、半導体装置３００に比べて半導体素子４５０と多層基板８００との接続信頼性を向上することができる。しかしながら、半導体装置７００では、半導体素子４５０を樹脂８１０に埋め込んでから樹脂８１０の表面に第１配線層９１０等を形成するため、相互に接続された配線層を半導体素子４５０の表裏両面に形成することができず、高密度実装化が困難であるという問題があった。   Further, in the conventional semiconductor device 700 in which the semiconductor element is built in the substrate, bumps are not used for the electrical connection between the semiconductor element 450 and the multilayer substrate 800, so that the semiconductor element 450 and the multilayer substrate 800 are compared with the semiconductor device 300. The connection reliability can be improved. However, in the semiconductor device 700, the first wiring layer 910 and the like are formed on the surface of the resin 810 after embedding the semiconductor element 450 in the resin 810, so that interconnected wiring layers are formed on both the front and back surfaces of the semiconductor element 450. There is a problem that high-density mounting is difficult.

上記の点に鑑みて、半導体素子と基板との接続信頼性が高く、高密度実装化が可能な半導体装置及びその製造方法を提供することを課題とする。   In view of the above points, it is an object to provide a semiconductor device that has high connection reliability between a semiconductor element and a substrate and can be mounted at high density, and a manufacturing method thereof.

本半導体装置は、一方の面から他方の面に貫通する複数の導体を有する基板と、前記基板の前記一方の面に形成された、半導体素子を内蔵する第１絶縁層と、前記第１絶縁層上に形成され、かつ、前記第１絶縁層に設けられた貫通孔を介して前記基板の前記一方の面から露出する複数の導体の一部及び前記半導体素子と電気的に接続された第１配線層と、前記基板の前記他方の面に形成された第２絶縁層と、前記第２絶縁層上に形成され、かつ、前記第２絶縁層に設けられた貫通孔を介して前記基板の前記他方の面から露出する前記複数の導体の一部と電気的に接続された第２配線層と、を有することを要件とする。   The semiconductor device includes a substrate having a plurality of conductors penetrating from one surface to the other surface, a first insulating layer containing a semiconductor element formed on the one surface of the substrate, and the first insulation. A plurality of conductors formed on the layer and exposed from the one surface of the substrate through a through hole provided in the first insulating layer and electrically connected to the semiconductor element; One wiring layer, a second insulating layer formed on the other surface of the substrate, and the substrate through a through hole formed on the second insulating layer and provided in the second insulating layer And a second wiring layer electrically connected to a part of the plurality of conductors exposed from the other surface.

又、本半導体装置の製造方法は、一方の面から他方の面に貫通する複数の導体を有する基板を準備する第１工程と、前記基板の前記一方の面に半導体素子を固着する第２工程と、前記基板の前記一方の面に、前記半導体素子を被覆する第１絶縁層を形成する第３工程と、前記第１絶縁層上に、前記第１絶縁層に設けられた貫通孔を介して前記基板の前記一方の面から露出する複数の導体の一部及び前記半導体素子と電気的に接続された第１配線層を形成する第４工程と、前記基板の前記他方の面に、第２絶縁層を形成する第５工程と、前記第２絶縁層上に、前記第２絶縁層に設けられた貫通孔を介して前記基板の前記他方の面から露出する前記複数の導体の一部と電気的に接続された第２配線層を形成する第６工程と、を有することを要件とする。   The method for manufacturing a semiconductor device includes a first step of preparing a substrate having a plurality of conductors penetrating from one surface to the other surface, and a second step of fixing a semiconductor element to the one surface of the substrate. And a third step of forming a first insulating layer covering the semiconductor element on the one surface of the substrate, and a through hole provided in the first insulating layer on the first insulating layer. A fourth step of forming a part of the plurality of conductors exposed from the one surface of the substrate and a first wiring layer electrically connected to the semiconductor element; and A fifth step of forming two insulating layers, and a part of the plurality of conductors exposed from the other surface of the substrate via a through hole provided in the second insulating layer on the second insulating layer And a sixth step of forming a second wiring layer electrically connected to That.

開示の技術によれば、半導体素子と基板との接続信頼性が高く、高密度実装化が可能な半導体装置及びその製造方法を提供することができる。   According to the disclosed technology, it is possible to provide a semiconductor device that has high connection reliability between a semiconductor element and a substrate and can be mounted at high density, and a method for manufacturing the semiconductor device.

基板上に半導体素子を実装した従来の半導体装置を例示する断面図である。It is sectional drawing which illustrates the conventional semiconductor device which mounted the semiconductor element on the board | substrate. 基板に半導体素子を内蔵した従来の半導体装置を例示する断面図である。It is sectional drawing which illustrates the conventional semiconductor device which incorporated the semiconductor element in the board | substrate. 第１の実施の形態に係る半導体装置を例示する断面図である。1 is a cross-sectional view illustrating a semiconductor device according to a first embodiment. 図３のＡ部を拡大して例示する斜視透視図である。FIG. 4 is a perspective perspective view illustrating an enlarged portion A of FIG. 3. 第１の実施の形態に係る半導体装置の製造工程を例示する図（その１）である。6 is a diagram (part 1) illustrating a manufacturing process of the semiconductor device according to the first embodiment; FIG. 第１の実施の形態に係る半導体装置の製造工程を例示する図（その２）である。FIG. 6 is a second diagram illustrating the manufacturing process of the semiconductor device according to the first embodiment; 第１の実施の形態に係る半導体装置の製造工程を例示する図（その３）である。FIG. 6 is a diagram (part 3) illustrating the manufacturing process of the semiconductor device according to the first embodiment; 第１の実施の形態に係る半導体装置の製造工程を例示する図（その４）である。FIG. 8 is a diagram (No. 4) for exemplifying the manufacturing process for the semiconductor device according to the first embodiment; 第１の実施の形態に係る半導体装置の製造工程を例示する図（その５）である。FIG. 8 is a diagram (No. 5) for exemplifying the manufacturing process for the semiconductor device according to the first embodiment; 第１の実施の形態に係る半導体装置の製造工程を例示する図（その６）である。FIG. 10 is a diagram (No. 6) for exemplifying the manufacturing process for the semiconductor device according to the first embodiment; 第１の実施の形態に係る半導体装置の製造工程を例示する図（その７）である。FIG. 7 is a diagram (No. 7) for exemplifying the manufacturing process for the semiconductor device according to the first embodiment; 第１の実施の形態に係る半導体装置の製造工程を例示する図（その８）である。FIG. 8 is a diagram (No. 8) for exemplifying the manufacturing process for the semiconductor device according to the first embodiment; 第１の実施の形態の変形例に係る半導体装置の一部を例示する図である。It is a figure which illustrates a part of semiconductor device which concerns on the modification of 1st Embodiment. 第２の実施の形態に係る半導体装置を例示する断面図である。6 is a cross-sectional view illustrating a semiconductor device according to a second embodiment; FIG.

以下、図面を参照して、実施の形態の説明を行う。   Hereinafter, embodiments will be described with reference to the drawings.

〈第１の実施の形態〉
［第１の実施の形態に係る半導体装置の構造］
始めに、第１の実施の形態に係る半導体装置の構造について説明する。図３は、第１の実施の形態に係る半導体装置を例示する断面図である。図４は、図３のＡ部を拡大して例示する斜視透視図である。ただし、図４において、一部の構成要素は省略されている。図３及び図４において、Ｘ方向は後述する基板１３の一方の面１３ａと平行な方向、Ｙ方向はＸ方向に垂直な方向（紙面奥行き方向）、Ｚ方向はＸ方向及びＹ方向に垂直な方向（基板１３の厚さ方向）をそれぞれ示している。 <First Embodiment>
[Structure of Semiconductor Device According to First Embodiment]
First, the structure of the semiconductor device according to the first embodiment will be described. FIG. 3 is a cross-sectional view illustrating the semiconductor device according to the first embodiment. FIG. 4 is a perspective perspective view illustrating the portion A of FIG. 3 in an enlarged manner. However, some components are omitted in FIG. 3 and 4, the X direction is a direction parallel to one surface 13a of the substrate 13 to be described later, the Y direction is a direction perpendicular to the X direction (paper depth direction), and the Z direction is perpendicular to the X direction and the Y direction. Each direction (thickness direction of the substrate 13) is shown.

図３及び図４を参照するに、第１の実施の形態に係る半導体装置１０は、基板１３と、半導体素子１４と、絶縁性樹脂１５と、第１絶縁層１６ａと、第２絶縁層１６ｂと、第１配線層１７ａと、第２配線層１７ｂと、第１ソルダーレジスト層１８ａと、第２ソルダーレジスト層１８ｂと、第１はんだバンプ１９ａと、第２はんだバンプ１９ｂとを有する。   3 and 4, the semiconductor device 10 according to the first embodiment includes a substrate 13, a semiconductor element 14, an insulating resin 15, a first insulating layer 16a, and a second insulating layer 16b. A first wiring layer 17a, a second wiring layer 17b, a first solder resist layer 18a, a second solder resist layer 18b, a first solder bump 19a, and a second solder bump 19b.

半導体装置１０において、基板１３は、例えば厚さ７０〜１００μｍ程度、大きさ１０×１０ｍｍ程度の基板であり、絶縁性基材１１全体に亘りそのＺ方向（厚さ方向）に形成された多数の貫通孔１１ｘに金属材料を充填して線状導体（ビア）１２が形成された基板である。絶縁性基材１１としては、例えばアルミナ（酸化アルミニウム）、ムライト、窒化アルミニウム、ガラスセラミックス（ガラスとセラミックスの複合材料）等を用いることができる。又、絶縁性基材１１の材料として、有機系の樹脂等（エポキシ系樹脂、ポリイミド系樹脂等）を用いても構わない。   In the semiconductor device 10, the substrate 13 is, for example, a substrate having a thickness of about 70 to 100 μm and a size of about 10 × 10 mm, and a large number of substrates formed in the Z direction (thickness direction) over the entire insulating base material 11. A substrate in which a linear conductor (via) 12 is formed by filling a through hole 11x with a metal material. As the insulating substrate 11, for example, alumina (aluminum oxide), mullite, aluminum nitride, glass ceramics (a composite material of glass and ceramics), or the like can be used. Further, as the material of the insulating base material 11, an organic resin or the like (epoxy resin, polyimide resin or the like) may be used.

基板１３に実装される半導体素子１４が例えばシリコンである場合、その熱膨張係数（ＣＴＥ）は３ｐｐｍ／℃程度である。又、基板１３に形成される第１配線層１７ａや第２配線層１７ｂが例えば銅（Ｃｕ）である場合、その熱膨張係数（ＣＴＥ）は１６〜１７ｐｐｍ／℃程度である。絶縁性基材１１の材料として例えば熱膨張係数（ＣＴＥ）が６〜７ｐｐｍ／℃程度のアルミナや熱膨張係数（ＣＴＥ）が４．５ｐｐｍ／℃程度のムライト等の半導体素子１４の熱膨張係数（ＣＴＥ）と第１配線層１７ａや第２配線層１７ｂの熱膨張係数（ＣＴＥ）との中間的な値の熱膨張係数（ＣＴＥ）を有するセラミックス等を用いることにより、半導体素子１４と第１配線層１７ａや第２配線層１７ｂとの熱膨張係数（ＣＴＥ）の差に起因する応力を緩和することができる。   When the semiconductor element 14 mounted on the substrate 13 is, for example, silicon, its coefficient of thermal expansion (CTE) is about 3 ppm / ° C. When the first wiring layer 17a and the second wiring layer 17b formed on the substrate 13 are, for example, copper (Cu), the coefficient of thermal expansion (CTE) is about 16 to 17 ppm / ° C. As the material of the insulating base material 11, for example, the thermal expansion coefficient (CTE) of the semiconductor element 14 such as alumina having a thermal expansion coefficient (CTE) of about 6 to 7 ppm / ° C. By using ceramics having a coefficient of thermal expansion (CTE) intermediate between the coefficient of thermal expansion (CTE) of the first wiring layer 17a and the second wiring layer 17b, the semiconductor element 14 and the first wiring The stress caused by the difference in coefficient of thermal expansion (CTE) between the layer 17a and the second wiring layer 17b can be relaxed.

絶縁性基材１１の材料として有機系の樹脂等（エポキシ系樹脂、ポリイミド系樹脂等）を用いる場合には、シリカ等の無機フィラーを高密度に混合させることにより、その熱膨張係数（ＣＴＥ）を半導体素子１４の熱膨張係数（ＣＴＥ）と第１配線層１７ａや第２配線層１７ｂの熱膨張係数（ＣＴＥ）との中間的な値にすることが可能となり、半導体素子１４と第１配線層１７ａや第２配線層１７ｂとの熱膨張係数（ＣＴＥ）の差に起因する応力を緩和することができる。   When an organic resin or the like (epoxy resin, polyimide resin, or the like) is used as the material of the insulating substrate 11, its thermal expansion coefficient (CTE) is obtained by mixing an inorganic filler such as silica at a high density. Can be set to an intermediate value between the thermal expansion coefficient (CTE) of the semiconductor element 14 and the thermal expansion coefficient (CTE) of the first wiring layer 17a and the second wiring layer 17b. The stress caused by the difference in coefficient of thermal expansion (CTE) between the layer 17a and the second wiring layer 17b can be relaxed.

線状導体１２は、その一端面が基板１３の一方の面１３ａから露出しており、その他端面が基板１３の他方の面１３ｂから露出している。線状導体１２は、例えば平面視円形に形成されており、その直径は例えば３０ｎｍ〜２０００ｎｍとすることができる。なお、平面視とは、対象物を図３のＺ方向から見た場合を指す。又、線状導体１２は、隣接する線状導体１２の間隔が線状導体１２の直径よりも小さくなる程度に密に形成されていることが好ましい。ただし、線状導体１２の配置形態については、特に限定されず、例えばヘキサゴナル状に配置されていてもよいし、グリッド状に配置されていてもよい。   One end surface of the linear conductor 12 is exposed from one surface 13 a of the substrate 13, and the other end surface is exposed from the other surface 13 b of the substrate 13. The linear conductor 12 is formed, for example, in a circular shape in plan view, and the diameter thereof can be set to, for example, 30 nm to 2000 nm. In addition, planar view refers to the case where the object is viewed from the Z direction in FIG. Further, the linear conductors 12 are preferably formed so densely that the interval between the adjacent linear conductors 12 is smaller than the diameter of the linear conductors 12. However, the arrangement form of the linear conductors 12 is not particularly limited, and may be arranged, for example, in a hexagonal form or in a grid form.

各線状導体１２は、基板１３の一方の面１３ａに形成された導体と他方の面１３ｂに形成された導体とを接続するビアとしての機能を有する。ただし、線状導体１２の一部は導体には接続されず、電気的に孤立（フローティング）した状態であっても構わない。線状導体（ビア）１２を形成する金属材料としては、例えば銀（Ａｇ）、銅（Ｃｕ）、ニッケル（Ｎｉ）等を用いることができる。   Each linear conductor 12 has a function as a via that connects a conductor formed on one surface 13a of the substrate 13 and a conductor formed on the other surface 13b. However, a part of the linear conductor 12 may not be connected to the conductor but may be electrically isolated (floating). As a metal material for forming the linear conductor (via) 12, for example, silver (Ag), copper (Cu), nickel (Ni) or the like can be used.

半導体素子１４は、基板１３の一方の面１３ａに絶縁性樹脂１５により固着されている。半導体素子１４は、シリコン等からなる薄板化された半導体基板（図示せず）上に半導体集積回路（図示せず）や電極パッド（図示せず）が形成されたものである。半導体素子１４の厚さは、例えば１０〜５０μｍとすることができる。絶縁性樹脂１５の材料としては、エポキシ系樹脂、ポリイミド系樹脂等を用いることができる。   The semiconductor element 14 is fixed to one surface 13 a of the substrate 13 with an insulating resin 15. The semiconductor element 14 is obtained by forming a semiconductor integrated circuit (not shown) and an electrode pad (not shown) on a thinned semiconductor substrate (not shown) made of silicon or the like. The thickness of the semiconductor element 14 can be set to, for example, 10 to 50 μm. As a material of the insulating resin 15, an epoxy resin, a polyimide resin, or the like can be used.

なお、半導体素子１４は、半導体集積回路（図示せず）や電極パッド（図示せず）が上側（基板１３の一方の面１３ａと接触しない側）に来るように配置されている。半導体素子１４の背面（基板１３の一方の面１３ａと接触する面）には、例えばＳｉＯ２等の絶縁膜を形成しても構わない。又、半導体素子１４の背面（基板１３の一方の面１３ａと接触する面）に絶縁膜を形成せずに、半導体素子１４の背面とその下に位置する線状導体１２の一端面とを導通させ、その線状導体１２を基準電位（ＧＮＤ）に接続しても構わない。このようにすると、半導体素子１４の背面は基準電位（ＧＮＤ）になるため、シールド効果を得ることができる。 The semiconductor element 14 is arranged such that a semiconductor integrated circuit (not shown) and an electrode pad (not shown) are on the upper side (the side not in contact with the one surface 13a of the substrate 13). An insulating film such as SiO 2 may be formed on the back surface of the semiconductor element 14 (the surface in contact with the one surface 13a of the substrate 13). Further, without forming an insulating film on the back surface of the semiconductor element 14 (the surface in contact with the one surface 13a of the substrate 13), the back surface of the semiconductor element 14 and one end surface of the linear conductor 12 positioned thereunder are electrically connected. The linear conductor 12 may be connected to a reference potential (GND). In this way, the back surface of the semiconductor element 14 is at the reference potential (GND), so that a shielding effect can be obtained.

第１絶縁層１６ａは、半導体素子１４及び絶縁性樹脂１５を覆うように基板１３の一方の面１３ａに形成されている。第１絶縁層１６ａの材料としては、エポキシ系樹脂、ポリイミド系樹脂などの樹脂材を用いることができる。   The first insulating layer 16 a is formed on one surface 13 a of the substrate 13 so as to cover the semiconductor element 14 and the insulating resin 15. As a material of the first insulating layer 16a, a resin material such as an epoxy resin or a polyimide resin can be used.

第１配線層１７ａは、第１絶縁層１６ａ上に形成されている。第１ビアホール１６ｘ内の第１配線層１７ａは、第１ビアホール１６ｘ内に露出した多数の線状導体１２の端面と電気的に接続されている。例えば第１ビアホール１６ｘの底部の直径を１００μｍ程度に選定すると、第１配線層１７ａは数千本の線状導体１２の端面と電気的に接続されることになる。第２ビアホール１６ｙ内の第１配線層１７ａは、第２ビアホール１６ｙ内に露出し半導体素子１４の電極パッド（図示せず）と電気的に接続されている。第１配線層１７ａの材料としては、例えば銅（Ｃｕ）等を用いることができる。   The first wiring layer 17a is formed on the first insulating layer 16a. The first wiring layer 17a in the first via hole 16x is electrically connected to the end faces of many linear conductors 12 exposed in the first via hole 16x. For example, if the diameter of the bottom of the first via hole 16x is selected to be about 100 μm, the first wiring layer 17a is electrically connected to the end faces of several thousand linear conductors 12. The first wiring layer 17a in the second via hole 16y is exposed in the second via hole 16y and is electrically connected to an electrode pad (not shown) of the semiconductor element 14. As a material of the first wiring layer 17a, for example, copper (Cu) or the like can be used.

第１ソルダーレジスト層１８ａは、第１配線層１７ａを覆うように第１絶縁層１６ａ上に形成されている。第１ソルダーレジスト層１８ａは開口部１８ｘを有し、開口部１８ｘ内には第１配線層１７ａの一部が露出している。   The first solder resist layer 18a is formed on the first insulating layer 16a so as to cover the first wiring layer 17a. The first solder resist layer 18a has an opening 18x, and a part of the first wiring layer 17a is exposed in the opening 18x.

第１はんだバンプ１９ａは、第１ソルダーレジスト層１８ａの開口部１８ｘ内に露出する第１配線層１７ａ上に形成されている。第１はんだバンプ１９ａの材料としては、例えばＰｂを含む合金、ＳｎとＣｕの合金、ＳｎとＡｇの合金、ＳｎとＡｇとＣｕの合金等を用いることができる。第１はんだバンプ１９ａは、例えばマザーボード等と接続される外部接続端子として機能する。   The first solder bump 19a is formed on the first wiring layer 17a exposed in the opening 18x of the first solder resist layer 18a. As the material of the first solder bump 19a, for example, an alloy containing Pb, an alloy of Sn and Cu, an alloy of Sn and Ag, an alloy of Sn, Ag, and Cu can be used. The first solder bump 19a functions as an external connection terminal connected to, for example, a mother board.

なお、外部接続端子として、第１はんだバンプ１９ａに代えて金属ピン等を用いても構わない。又、第１はんだバンプ１９ａや金属ピン等の外部接続端子は、設けなくても構わない。この場合には、必要なときに開口部１８ｘ内に露出する第１配線層１７ａ上に外部接続端子を形成すればよい。   A metal pin or the like may be used as the external connection terminal instead of the first solder bump 19a. Further, the external connection terminals such as the first solder bumps 19a and the metal pins may not be provided. In this case, an external connection terminal may be formed on the first wiring layer 17a exposed in the opening 18x when necessary.

第２絶縁層１６ｂは、基板１３の他方の面１３ｂに形成されている。第２絶縁層１６ｂの材料としては、エポキシ系樹脂、ポリイミド系樹脂などの樹脂材を用いることができる。   The second insulating layer 16 b is formed on the other surface 13 b of the substrate 13. As a material of the second insulating layer 16b, a resin material such as an epoxy resin or a polyimide resin can be used.

第２配線層１７ｂは、第２絶縁層１６ｂ上に形成されている。第３ビアホール１６ｚ内の第２配線層１７ｂは、第３ビアホール１６ｚ内に露出した多数の線状導体１２の端面と電気的に接続されている。例えば第３ビアホール１６ｚの底部の直径を１００μｍ程度に選定すると、第２配線層１７ｂは数千本の線状導体１２の端面と電気的に接続されることになる。この場合、第２配線層１７ｂは、数千本の線状導体１２により第１配線層１７ａと電気的に接続される。第２配線層１７ｂの材料としては、例えば銅（Ｃｕ）等を用いることができる。   The second wiring layer 17b is formed on the second insulating layer 16b. The second wiring layer 17b in the third via hole 16z is electrically connected to the end faces of the numerous linear conductors 12 exposed in the third via hole 16z. For example, if the diameter of the bottom of the third via hole 16z is selected to be about 100 μm, the second wiring layer 17b is electrically connected to the end faces of several thousand linear conductors 12. In this case, the second wiring layer 17 b is electrically connected to the first wiring layer 17 a by several thousand linear conductors 12. As a material of the second wiring layer 17b, for example, copper (Cu) or the like can be used.

第２ソルダーレジスト層１８ｂは、第２配線層１７ｂを覆うように第２絶縁層１６ｂ上に形成されている。第２ソルダーレジスト層１８ｂは開口部１８ｙを有し、開口部１８ｙ内には第２配線層１７ｂの一部が露出している。   The second solder resist layer 18b is formed on the second insulating layer 16b so as to cover the second wiring layer 17b. The second solder resist layer 18b has an opening 18y, and a part of the second wiring layer 17b is exposed in the opening 18y.

第２はんだバンプ１９ｂは、第２ソルダーレジスト層１８ｂの開口部１８ｙ内に露出する第２配線層１７ｂ上に形成されている。第２はんだバンプ１９ｂの材料としては、例えばＰｂを含む合金、ＳｎとＣｕの合金、ＳｎとＡｇの合金、ＳｎとＡｇとＣｕの合金等を用いることができる。第２はんだバンプ１９ｂは、例えばマザーボード等と接続される外部接続端子として機能する。   The second solder bump 19b is formed on the second wiring layer 17b exposed in the opening 18y of the second solder resist layer 18b. As a material of the second solder bump 19b, for example, an alloy containing Pb, an alloy of Sn and Cu, an alloy of Sn and Ag, an alloy of Sn, Ag, and Cu can be used. The second solder bump 19b functions as an external connection terminal connected to, for example, a motherboard.

なお、外部接続端子として、第２はんだバンプ１９ｂに代えて金属ピン等を用いても構わない。又、第２はんだバンプ１９ｂや金属ピン等の外部接続端子は、設けなくても構わない。この場合には、必要なときに開口部１８ｙ内に露出する第２配線層１７ｂ上に外部接続端子を形成すればよい。以上が、第１の実施の形態に係る半導体装置の構造である。   A metal pin or the like may be used as the external connection terminal instead of the second solder bump 19b. Also, the external connection terminals such as the second solder bumps 19b and the metal pins may not be provided. In this case, an external connection terminal may be formed on the second wiring layer 17b exposed in the opening 18y when necessary. The above is the structure of the semiconductor device according to the first embodiment.

［第１の実施の形態に係る半導体装置の製造方法］
続いて、第１の実施の形態に係る半導体装置の製造方法について説明する。図５〜図１２は、第１の実施の形態に係る半導体装置の製造工程を例示する図である。図５〜図１２において、図１に示す半導体装置１０と同一構成部分には同一符号を付し、その説明を省略する場合がある。 [Method of Manufacturing Semiconductor Device According to First Embodiment]
Next, a method for manufacturing the semiconductor device according to the first embodiment will be described. 5 to 12 are diagrams illustrating the manufacturing process of the semiconductor device according to the first embodiment. 5 to 12, the same components as those of the semiconductor device 10 shown in FIG. 1 are denoted by the same reference numerals, and the description thereof may be omitted.

始めに、図５に示す工程では、絶縁性基材１１を準備し、準備した絶縁性基材１１全体に亘りその厚さ方向に、多数の貫通孔１１ｘを形成する。絶縁性基材１１としては、例えば厚さ７０〜１００μｍ程度、大きさ１０×１０ｍｍ程度のアルミナ（酸化アルミニウム）のグリーンシート等を用いることができる。貫通孔１１ｘは、例えば平面視円形とすることができ、その場合の直径φ１は例えば３０ｎｍ〜２０００ｎｍとすることができる。又、貫通孔１１ｘは、隣接する貫通孔１１ｘの間隔Ｐが貫通孔１１ｘの直径φ１よりも小さくなる程度に密に形成することが好ましい。ただし、貫通孔１１ｘの配置形態については、特に限定されず、例えばヘキサゴナル状に配置してもよいし、グリッド状に配置してもよい。 First, in the step shown in FIG. 5, the insulating base 11 is prepared, and a large number of through holes 11 x are formed in the thickness direction over the prepared insulating base 11. As the insulating substrate 11, for example, a green sheet of alumina (aluminum oxide) having a thickness of about 70 to 100 μm and a size of about 10 × 10 mm can be used. Through holes 11x may be, for example, a circular shape in plan view, the diameter phi 1 of the case may be, for example 30Nm～2000nm. The through-holes 11x are preferably the interval P of the adjacent through-holes 11x are densely formed approximately smaller than the diameter phi 1 of the through hole 11x. However, the arrangement form of the through holes 11x is not particularly limited, and may be arranged in a hexagonal shape or a grid shape, for example.

貫通孔１１ｘの形成方法の一例を以下に示す。貫通孔１１ｘは、例えば陽極酸化法を用いて形成することができる。具体的には、例えばアルミニウム（Ａｌ）の基板の一方の面を絶縁被膜したＡｌ基板、又はガラス基板上にスパッタリング等によりアルミニウム（Ａｌ）の電極層を形成したＡｌ電極層を用意し、用意したＡｌ基板又はＡｌ電極層の表面を洗浄後、電解液（好適には硫酸水溶液）中に浸漬し、浸漬したＡｌ基板又はＡｌ電極層を陽極とし、これに対向配置される白金（Ｐｄ）電極を陰極として通電（パルス電圧を印加）することで、Ａｌ基板又はＡｌ電極層の表面に多孔質金属酸化膜（微小径の孔が規則正しく形成された酸化アルミニウムの膜）を形成することができる。   An example of a method for forming the through hole 11x is shown below. The through hole 11x can be formed using, for example, an anodic oxidation method. Specifically, for example, an Al substrate obtained by insulatingly coating one surface of an aluminum (Al) substrate or an Al electrode layer in which an aluminum (Al) electrode layer is formed on a glass substrate by sputtering or the like was prepared. After the surface of the Al substrate or Al electrode layer is washed, it is immersed in an electrolytic solution (preferably an aqueous sulfuric acid solution), and the immersed Al substrate or Al electrode layer is used as an anode, and a platinum (Pd) electrode disposed opposite thereto is used. By energizing as the cathode (applying a pulse voltage), a porous metal oxide film (aluminum oxide film in which fine pores are regularly formed) can be formed on the surface of the Al substrate or Al electrode layer.

この後、陽極酸化とは逆電位の電圧を各電極に印加（Ａｌ基板又はＡｌ電極層を陰極とし、白金（Ｐｄ）電極を陽極として通電）することで、多孔質金属酸化膜をＡｌ基板又はＡｌ電極層から分離する。これによって、所望の微小径（例えば３０ｎｍ〜２０００ｎｍ）の貫通孔１１ｘが高密度に形成された絶縁性基材１１が得られる。   Thereafter, a voltage having a reverse potential to that of anodic oxidation is applied to each electrode (the Al substrate or the Al electrode layer is used as a cathode, and a platinum (Pd) electrode is used as an anode) to thereby form the porous metal oxide film on the Al substrate or Separate from the Al electrode layer. Thereby, the insulating base material 11 in which the through holes 11x having a desired minute diameter (for example, 30 nm to 2000 nm) are formed at a high density is obtained.

なお、絶縁性基材１１の材料としては、アルミナ（酸化アルミニウム）以外に、ムライト、窒化アルミニウム、ガラスセラミックス（ガラスとセラミックスの複合材料）等を用いてもよい。又、絶縁性基材１１の材料はセラミックス（無機材料）には限定されず、有機系の樹脂等（エポキシ系樹脂、ポリイミド系樹脂等）を用いても構わない。   In addition to alumina (aluminum oxide), mullite, aluminum nitride, glass ceramics (a composite material of glass and ceramics), or the like may be used as the material for the insulating substrate 11. The material of the insulating substrate 11 is not limited to ceramics (inorganic material), and organic resins or the like (epoxy resins, polyimide resins, etc.) may be used.

ただし、有機系の樹脂（エポキシ系樹脂、ポリイミド系樹脂等）を用いる場合、シリカ等の無機フィラーを高密度に混合させたものを使用することが望ましい。第１絶縁層１６ａや第２絶縁層１６ｂも同等の樹脂を使用し、熱膨張係数（ＣＴＥ）も近似しているため、シリカ等の無機フィラーを高密度に混合させることにより絶縁性基材１１に使用する樹脂の熱膨張係数（ＣＴＥ）を下げて、半導体素子１４の熱膨張係数（ＣＴＥ）と第１配線層１７ａや第２配線層１７ｂの熱膨張係数（ＣＴＥ）との中間的な値の熱膨張係数（ＣＴＥ）を確保するためである。   However, when an organic resin (epoxy resin, polyimide resin, or the like) is used, it is desirable to use a material in which an inorganic filler such as silica is mixed at a high density. Since the first insulating layer 16a and the second insulating layer 16b use the same resin and have a similar coefficient of thermal expansion (CTE), the insulating base material 11 can be obtained by mixing an inorganic filler such as silica at a high density. An intermediate value between the thermal expansion coefficient (CTE) of the semiconductor element 14 and the thermal expansion coefficient (CTE) of the first wiring layer 17a and the second wiring layer 17b by lowering the thermal expansion coefficient (CTE) of the resin used for This is to ensure the coefficient of thermal expansion (CTE).

絶縁性基材１１に有機系の樹脂（エポキシ系樹脂、ポリイミド系樹脂等）を用いる場合、貫通孔１１ｘは炭酸ガスレーザ、エキシマレーザ等を用いた穴明け加工により形成することができる。   When an organic resin (epoxy resin, polyimide resin, or the like) is used for the insulating substrate 11, the through hole 11x can be formed by drilling using a carbon dioxide laser, an excimer laser, or the like.

次いで、図６に示す工程では、絶縁性基材１１に形成された貫通孔１１ｘに金属材料を充填して線状導体（ビア）１２を形成する。以降、線状導体１２を有する絶縁性基材１１を基板１３と称する場合がある。線状導体１２は、例えばスクリーン印刷法やインクジェット法等を用いて、例えば銀（Ａｇ）や銅（Ｃｕ）等の導電性ペーストを貫通孔１１ｘに充填することにより形成することができる。又、絶縁性基材１１として有機系の樹脂等（エポキシ系樹脂、ポリイミド系樹脂等）を用いた場合には、めっき法を用いて貫通孔１１ｘに銅（Ｃｕ）やニッケル（Ｎｉ）等の金属材料を充填することができる。   Next, in a step shown in FIG. 6, the linear conductor (via) 12 is formed by filling the through hole 11 x formed in the insulating base material 11 with a metal material. Hereinafter, the insulating base material 11 having the linear conductor 12 may be referred to as a substrate 13. The linear conductor 12 can be formed by, for example, filling the through hole 11x with a conductive paste such as silver (Ag) or copper (Cu) using, for example, a screen printing method or an inkjet method. In addition, when an organic resin or the like (epoxy resin, polyimide resin, or the like) is used as the insulating substrate 11, copper (Cu), nickel (Ni), or the like is formed in the through hole 11x using a plating method. Metal materials can be filled.

例えば金属材料として銅（Ｃｕ）を用いる場合には、絶縁性基材１１の表面（貫通孔１１ｘの内壁面を含む）に、無電解銅（Ｃｕ）めっき法によりシード層を形成し、形成したシード層を給電層として利用した電解銅（Ｃｕ）めっき法により、貫通孔１１ｘに銅（Ｃｕ）を充填することができる。又、無電解銅（Ｃｕ）めっき法のみにより、銅（Ｃｕ）を貫通孔１１ｘに充填しても構わない。   For example, when copper (Cu) is used as the metal material, a seed layer is formed on the surface of the insulating base material 11 (including the inner wall surface of the through hole 11x) by an electroless copper (Cu) plating method. The through hole 11x can be filled with copper (Cu) by electrolytic copper (Cu) plating using the seed layer as a power feeding layer. Alternatively, the through hole 11x may be filled with copper (Cu) only by electroless copper (Cu) plating.

更に、必要に応じて機械研磨、化学機械研磨（ＣＭＰ）等により両面を研磨して平坦化し、線状導体１２の両端を絶縁性基材１１の両面に露出させることができる。このようにして、絶縁性基材１１に、絶縁性基材１１の厚さ方向に貫通する微小径の線状導体１２が高密度に設けられた構造体（図６参照）を形成することができる。   Furthermore, if necessary, both surfaces can be polished and flattened by mechanical polishing, chemical mechanical polishing (CMP) or the like, and both ends of the linear conductor 12 can be exposed on both surfaces of the insulating substrate 11. In this way, a structure (see FIG. 6) in which the minute-diameter linear conductors 12 penetrating in the thickness direction of the insulating base material 11 are formed at a high density on the insulating base material 11 can be formed. it can.

次いで、図７に示す工程では、図６において形成した基板１３の一方の面１３ａに、半導体素子１４を配置する。半導体素子１４は、シリコン等からなる薄板化された半導体基板（図示せず）上に半導体集積回路（図示せず）や電極パッド（図示せず）が形成されたものである。半導体素子１４の厚さは、例えば１０〜５０μｍとすることができる。なお、半導体素子１４は、半導体集積回路（図示せず）や電極パッド（図示せず）が上側（基板１３の一方の面１３ａと接触しない側）に来るように配置する。   Next, in the process shown in FIG. 7, the semiconductor element 14 is disposed on one surface 13 a of the substrate 13 formed in FIG. 6. The semiconductor element 14 is obtained by forming a semiconductor integrated circuit (not shown) and an electrode pad (not shown) on a thinned semiconductor substrate (not shown) made of silicon or the like. The thickness of the semiconductor element 14 can be set to, for example, 10 to 50 μm. The semiconductor element 14 is arranged such that a semiconductor integrated circuit (not shown) and an electrode pad (not shown) are on the upper side (the side not in contact with the one surface 13a of the substrate 13).

次いで、図８に示す工程では、基板１３の一方の面１３ａに配置された半導体素子１４の側面に絶縁性樹脂１５（エポキシ系樹脂、ポリイミド系樹脂等）を塗布し、硬化させて半導体素子１４を基板１３の一方の面１３ａに固着する。   Next, in the process shown in FIG. 8, an insulating resin 15 (epoxy resin, polyimide resin, or the like) is applied to the side surface of the semiconductor element 14 disposed on the one surface 13 a of the substrate 13 and cured to cure the semiconductor element 14. Is fixed to one surface 13 a of the substrate 13.

次いで、図９に示す工程では、半導体素子１４及び絶縁性樹脂１５を覆うように基板１３の一方の面１３ａに第１絶縁層１６ａを形成する。これにより、半導体素子１４を内蔵する第１絶縁層１６ａが形成される。又、基板１３の他方の面１３ｂに第２絶縁層１６ｂを形成する。第１絶縁層１６ａ及び第２絶縁層１６ｂの材料としては、エポキシ系樹脂、ポリイミド系樹脂などの樹脂材を用いることができる。第１絶縁層１６ａは、一例として、半導体素子１４及び絶縁性樹脂１５を覆うように基板１３の一方の面１３ａに樹脂フィルムをラミネートした後、樹脂フィルムをプレス（押圧）し、その後、１９０℃程度の温度で熱処理して硬化させることにより形成することができる。第２絶縁層１６ｂも同様の方法により形成することができる。   Next, in a step shown in FIG. 9, a first insulating layer 16 a is formed on one surface 13 a of the substrate 13 so as to cover the semiconductor element 14 and the insulating resin 15. As a result, the first insulating layer 16a containing the semiconductor element 14 is formed. Further, the second insulating layer 16 b is formed on the other surface 13 b of the substrate 13. As the material of the first insulating layer 16a and the second insulating layer 16b, a resin material such as an epoxy resin or a polyimide resin can be used. As an example, the first insulating layer 16a is formed by laminating a resin film on one surface 13a of the substrate 13 so as to cover the semiconductor element 14 and the insulating resin 15, and then pressing (pressing) the resin film. It can be formed by heat treatment at a moderate temperature and curing. The second insulating layer 16b can also be formed by a similar method.

次いで、図１０に示す工程では、第１絶縁層１６ａに、レーザ加工法等を用いて、基板１３の一方の面１３ａが露出するように第１絶縁層１６ａを貫通する第１ビアホール１６ｘを形成し、半導体素子１４の電極パッド（図示せず）が露出するように第１絶縁層１６ａを貫通する第２ビアホール１６ｙを形成する。又、第２絶縁層１６ｂに、レーザ加工法等を用いて、基板１３の他方の面１３ｂが露出するように第２絶縁層１６ｂを貫通する第３ビアホール１６ｚを形成する。第１ビアホール１６ｘ内及び第３ビアホール１６ｚ内には、多数の線状導体１２の端面が露出する（前述の図４参照）。   Next, in the step shown in FIG. 10, the first via hole 16x penetrating the first insulating layer 16a is formed in the first insulating layer 16a by using a laser processing method or the like so that the one surface 13a of the substrate 13 is exposed. Then, a second via hole 16y penetrating the first insulating layer 16a is formed so that an electrode pad (not shown) of the semiconductor element 14 is exposed. A third via hole 16z that penetrates the second insulating layer 16b is formed in the second insulating layer 16b by using a laser processing method or the like so that the other surface 13b of the substrate 13 is exposed. In the first via hole 16x and the third via hole 16z, the end faces of many linear conductors 12 are exposed (see FIG. 4 described above).

なお、第１絶縁層１６ａとして感光性樹脂膜を用い、フォトリソグラフィによりパターニングして第１ビアホール１６ｘ等を形成する方法を用いてもよいし、スクリーン印刷により開口部が設けられた樹脂膜をパターニングして第１ビアホール１６ｘ等を形成する方法を用いてもよい。   Alternatively, a method may be used in which a photosensitive resin film is used as the first insulating layer 16a and patterned by photolithography to form the first via hole 16x or the like, or a resin film provided with an opening is patterned by screen printing. Then, a method of forming the first via hole 16x or the like may be used.

次いで、図１１に示す工程では、第１絶縁層１６ａ上に、第１ビアホール１６ｘ内に露出した多数の線状導体１２の端面、及び第２ビアホール１６ｙ内に露出した半導体素子１４の電極パッド（図示せず）と電気的に接続される第１配線層１７ａを形成する。又、第２絶縁層１６ｂ上に、第３ビアホール１６ｚ内に露出した多数の線状導体１２の端面と電気的に接続される第２配線層１７ｂを形成する。これにより、第１配線層１７ａと第２配線層１７ｂとは、多数の線状導体１２により電気的に接続される。第１配線層１７ａ及び第２配線層１７ｂの材料としては、例えば銅（Ｃｕ）等を用いることができる。第１配線層１７ａ及び第２配線層１７ｂは、例えばセミアディティブ法により形成される。   Next, in the step shown in FIG. 11, on the first insulating layer 16a, the end faces of the numerous linear conductors 12 exposed in the first via holes 16x and the electrode pads (semiconductor elements 14 exposed in the second via holes 16y) ( A first wiring layer 17a that is electrically connected to the first wiring layer 17a is formed. A second wiring layer 17b is formed on the second insulating layer 16b. The second wiring layer 17b is electrically connected to the end faces of the numerous linear conductors 12 exposed in the third via hole 16z. Thereby, the first wiring layer 17a and the second wiring layer 17b are electrically connected by the large number of linear conductors 12. As a material of the first wiring layer 17a and the second wiring layer 17b, for example, copper (Cu) or the like can be used. The first wiring layer 17a and the second wiring layer 17b are formed by, for example, a semi-additive method.

第１配線層１７ａを、セミアディティブ法により形成する例を、より詳しく説明すると、先ず、無電解めっき法又はスパッタ法により、第１ビアホール１６ｘ内、第２ビアホール１６ｙ内、基板１３の一方の面１３ａ、及び半導体素子１４の電極パッド（図示せず）上に銅（Ｃｕ）シード層（図示せず）を形成した後に、第１配線層１７ａに対応する開口部を備えたレジスト層（図示せず）を形成する。次いで、銅（Ｃｕ）シード層をめっき給電層に利用した電解めっき法により、レジスト層の開口部に銅（Ｃｕ）層パターン（図示せず）を形成する。   An example in which the first wiring layer 17a is formed by a semi-additive method will be described in more detail. First, in the first via hole 16x, the second via hole 16y, and one surface of the substrate 13 by an electroless plating method or a sputtering method. After a copper (Cu) seed layer (not shown) is formed on the electrode pad (not shown) of 13a and the semiconductor element 14, a resist layer (not shown) having an opening corresponding to the first wiring layer 17a is formed. Z). Next, a copper (Cu) layer pattern (not shown) is formed in the opening of the resist layer by an electrolytic plating method using the copper (Cu) seed layer as a plating power feeding layer.

続いて、レジスト層を除去した後に、銅（Ｃｕ）層パターンをマスクにして銅（Ｃｕ）シード層をエッチングすることにより、第１配線層１７ａを得ることができる。なお、第１配線層１７ａの形成方法としては、上述したセミアディティブ法の他にサブトラクティブ法などの各種の配線形成方法を用いることができる。第２配線層１７ｂも同様の方法により形成することができる。   Subsequently, after removing the resist layer, the first wiring layer 17a can be obtained by etching the copper (Cu) seed layer using the copper (Cu) layer pattern as a mask. In addition, as a formation method of the 1st wiring layer 17a, various wiring formation methods, such as a subtractive method other than the semi-additive method mentioned above, can be used. The second wiring layer 17b can also be formed by a similar method.

なお、上記と同様な工程を繰り返すことにより、第１配線層１７ａ及び第２配線層１７ｂ上に絶縁層及び配線層を積層し、ｎ層（ｎは１以上の整数）のビルドアップ配線層を形成してもよい。   By repeating the same process as described above, an insulating layer and a wiring layer are stacked on the first wiring layer 17a and the second wiring layer 17b, and an n-layer (n is an integer of 1 or more) build-up wiring layer is formed. It may be formed.

次いで、図１２に示す工程では、第１配線層１７ａを被覆するように第１絶縁層１６ａ上に開口部１８ｘを有する第１ソルダーレジスト層１８ａを形成する。又、第２配線層１７ｂを被覆するように第２絶縁層１６ｂ上に開口部１８ｙを有する第２ソルダーレジスト層１８ｂを形成する。開口部１８ｘを有する第１ソルダーレジスト層１８ａは、例えば第１配線層１７ａを被覆するようにソルダーレジスト液を塗布し、塗布したソルダーレジスト液を露光、現像することで形成することができる。開口部１８ｙを有する第２ソルダーレジスト層１８ｂも同様の方法により形成することができる。第１ソルダーレジスト層１８ａ及び第２ソルダーレジスト層１８ｂの材料としては、例えばエポキシ系樹脂やイミド系樹脂等を含む感光性樹脂組成物を用いることができる。   Next, in a step shown in FIG. 12, a first solder resist layer 18a having an opening 18x is formed on the first insulating layer 16a so as to cover the first wiring layer 17a. In addition, a second solder resist layer 18b having an opening 18y is formed on the second insulating layer 16b so as to cover the second wiring layer 17b. The first solder resist layer 18a having the opening 18x can be formed, for example, by applying a solder resist solution so as to cover the first wiring layer 17a, and exposing and developing the applied solder resist solution. The second solder resist layer 18b having the opening 18y can also be formed by the same method. As a material of the first solder resist layer 18a and the second solder resist layer 18b, for example, a photosensitive resin composition containing an epoxy resin, an imide resin, or the like can be used.

第１配線層１７ａの一部は、第１ソルダーレジスト層１８ａの開口部１８ｘ内に露出する。又、第２配線層１７ｂの一部は、第２ソルダーレジスト層１８ｂの開口部１８ｙ内に露出する。第１ソルダーレジスト層１８ａの開口部１８ｘ内に露出する第１配線層１７ａ上、及び第２ソルダーレジスト層１８ｂの開口部１８ｙ内に露出する第２配線層１７ｂ上に、例えば無電解めっき法により金属層（図示せず）を形成しても構わない。   A part of the first wiring layer 17a is exposed in the opening 18x of the first solder resist layer 18a. A part of the second wiring layer 17b is exposed in the opening 18y of the second solder resist layer 18b. On the first wiring layer 17a exposed in the opening 18x of the first solder resist layer 18a and on the second wiring layer 17b exposed in the opening 18y of the second solder resist layer 18b, for example, by electroless plating. A metal layer (not shown) may be formed.

金属層（図示せず）の例としては、Ａｕ層、Ｎｉ層／Ａｕ層をこの順番で積層したＮｉ／Ａｕ層や、Ｎｉ層／Ｐｄ層／Ａｕ層をこの順番で積層したＮｉ／Ｐｄ／Ａｕ層等を挙げることができる。又、金属層（図示せず）に代えて、第１ソルダーレジスト層１８ａの開口部１８ｘ内に露出する第１配線層１７ａ上、及び第２ソルダーレジスト層１８ｂの開口部１８ｙ内に露出する第２配線層１７ｂ上にＯＳＰ（Ｏｒｇａｎｉｃ Ｓｏｌｄｅｒａｂｉｌｉｔｙ Ｐｒｅｓｅｒｖａｔｉｖｅ）処理を施しても構わない。   Examples of metal layers (not shown) include an Au layer, a Ni / Au layer in which Ni layers / Au layers are laminated in this order, and a Ni / Pd / layer in which Ni layers / Pd layers / Au layers are laminated in this order. An Au layer can be used. In place of the metal layer (not shown), the first wiring layer 17a exposed in the opening 18x of the first solder resist layer 18a and the first wiring layer 17a exposed in the opening 18y of the second solder resist layer 18b are exposed. OSP (Organic Solderability Preservative) processing may be performed on the two wiring layers 17b.

次いで、第１ソルダーレジスト層１８ａの開口部１８ｘ内に露出する第１配線層１７ａ上、及び第２ソルダーレジスト層１８ｂの開口部１８ｙ内に露出する第２配線層１７ｂ上に、第１はんだバンプ１９ａ及び第２はんだバンプ１９ｂを形成することにより、図３に示す半導体装置１０が製造される。第１はんだバンプ１９ａは、例えば第１ソルダーレジスト層１８ａの開口部１８ｘ内に露出する第１配線層１７ａを覆うように、はんだペーストを印刷し、リフローすることにより形成することができる。第２はんだバンプ１９ｂも同様の方法により形成することができる。第１はんだバンプ１９ａ及び第２はんだバンプ１９ｂの材料としては、例えばＰｂを含む合金、ＳｎとＣｕの合金、ＳｎとＡｇの合金、ＳｎとＡｇとＣｕの合金等を用いることができる。第１はんだバンプ１９ａ及び第２はんだバンプ１９ｂは、例えばマザーボード等と接続される外部接続端子として機能する。   Next, the first solder bumps are formed on the first wiring layer 17a exposed in the opening 18x of the first solder resist layer 18a and on the second wiring layer 17b exposed in the opening 18y of the second solder resist layer 18b. The semiconductor device 10 shown in FIG. 3 is manufactured by forming 19a and the second solder bump 19b. The first solder bump 19a can be formed, for example, by printing a solder paste and reflowing so as to cover the first wiring layer 17a exposed in the opening 18x of the first solder resist layer 18a. The second solder bump 19b can also be formed by a similar method. As a material of the first solder bump 19a and the second solder bump 19b, for example, an alloy containing Pb, an alloy of Sn and Cu, an alloy of Sn and Ag, an alloy of Sn, Ag, and Cu can be used. The 1st solder bump 19a and the 2nd solder bump 19b function as an external connection terminal connected with a motherboard etc., for example.

なお、外部接続端子として、第１はんだバンプ１９ａ及び／又は第２はんだバンプ１９ｂに代えて金属ピン等を用いても構わない。又、第１はんだバンプ１９ａ及び／又は第２はんだバンプ１９ｂや金属ピン等の外部接続端子は、設けなくても構わない。この場合には、必要なとき（例えば半導体装置１０の出荷時等）に、開口部１８ｘ内に露出する第１配線層１７ａ上、及び／又は第２ソルダーレジスト層１８ｂの開口部１８ｙ内に露出する第２配線層１７ｂ上に外部接続端子を形成すればよい。   As external connection terminals, metal pins or the like may be used instead of the first solder bumps 19a and / or the second solder bumps 19b. Further, the external connection terminals such as the first solder bump 19a and / or the second solder bump 19b and the metal pin may not be provided. In this case, when necessary (for example, when the semiconductor device 10 is shipped), it is exposed on the first wiring layer 17a exposed in the opening 18x and / or in the opening 18y of the second solder resist layer 18b. An external connection terminal may be formed on the second wiring layer 17b.

このように、第１の実施の形態によれば、基板（線状導体を有する絶縁性基材）の一方の面に半導体素子を内蔵する第１絶縁層を形成し、第１絶縁層上に、第１絶縁層に設けられた貫通孔（ビアホール）を介して基板の一方の面から露出する複数の線状導体の一部及び半導体素子の電極パッドと電気的に接続された第１配線層を形成する。又、基板（線状導体を有する絶縁性基材）の他方の面（半導体素子の背面側）に第２絶縁層を形成し、第２絶縁層上に、第２絶縁層に設けられた貫通孔（ビアホール）を介して基板の他方の面から露出する複数の線状導体の一部と電気的に接続された第２配線層を形成する。   Thus, according to the first embodiment, the first insulating layer containing the semiconductor element is formed on one surface of the substrate (insulating base material having a linear conductor), and the first insulating layer is formed on the first insulating layer. The first wiring layer electrically connected to a part of the plurality of linear conductors exposed from one surface of the substrate and the electrode pad of the semiconductor element through a through hole (via hole) provided in the first insulating layer Form. In addition, a second insulating layer is formed on the other surface (the back side of the semiconductor element) of the substrate (insulating base material having a linear conductor), and the second insulating layer is provided on the second insulating layer. A second wiring layer electrically connected to a part of the plurality of linear conductors exposed from the other surface of the substrate through the hole (via hole) is formed.

その結果、基板（線状導体を有する絶縁性基材）の一方の面上に形成された第１配線層と、基板（線状導体を有する絶縁性基材）の他方の面上に形成された第２配線層とを、線状導体により電気的に接続することができる。   As a result, the first wiring layer formed on one surface of the substrate (insulating base material having a linear conductor) and the other surface of the substrate (insulating base material having a linear conductor) are formed. The second wiring layer can be electrically connected by a linear conductor.

すなわち、第１の実施の形態に係る半導体装置では、相互に接続された配線層（第１配線層及び第２配線層）を半導体素子の表裏両面に形成することができるため、実装密度を高めることができる。   That is, in the semiconductor device according to the first embodiment, the interconnect layers (the first interconnect layer and the second interconnect layer) that are connected to each other can be formed on both the front and back surfaces of the semiconductor element, thereby increasing the mounting density. be able to.

又、第１の実施の形態に係る半導体装置では、半導体素子と配線層（第１配線層及び第２配線層）との電気的接続にバンプを用いていないため、半導体素子と配線層（第１配線層及び第２配線層）との熱膨脹係数の違いに起因する応力破壊や、エレクトロマイグレーションに起因する断線等の発生を防止することが可能となり、半導体素子と配線層（第１配線層及び第２配線層）との接続信頼性を向上することができる。   In the semiconductor device according to the first embodiment, no bumps are used for electrical connection between the semiconductor element and the wiring layer (first wiring layer and second wiring layer). It is possible to prevent the occurrence of stress breakdown due to the difference in thermal expansion coefficient from the first wiring layer and the second wiring layer, and the occurrence of disconnection due to electromigration. The semiconductor element and the wiring layer (first wiring layer and Connection reliability with the second wiring layer) can be improved.

〈第１の実施の形態の変形例〉
図１３は、第１の実施の形態の変形例に係る半導体装置の一部を例示する図である。図１３（ａ）は断面図であり、図１３（ｂ）は基板１３の一方の面１３ａ（基板１３の他方の面１３ｂ）に接する導体を模式的に示す平面図である。図１３において、図３に示す半導体装置１０と同一構成部分には同一符号を付し、その説明を省略する場合がある。図１３において、Ｘ方向は基板１３の一方の面１３ａと平行な方向、Ｙ方向はＸ方向に垂直な方向（紙面奥行き方向）、Ｚ方向はＸ方向及びＹ方向に垂直な方向（基板１３の厚さ方向）をそれぞれ示している。 <Modification of First Embodiment>
FIG. 13 is a diagram illustrating a part of the semiconductor device according to the modification of the first embodiment. FIG. 13A is a cross-sectional view, and FIG. 13B is a plan view schematically showing a conductor in contact with one surface 13a of the substrate 13 (the other surface 13b of the substrate 13). In FIG. 13, the same components as those of the semiconductor device 10 shown in FIG. 3 are denoted by the same reference numerals, and the description thereof may be omitted. In FIG. 13, the X direction is a direction parallel to one surface 13 a of the substrate 13, the Y direction is a direction perpendicular to the X direction (depth direction in the drawing), and the Z direction is a direction perpendicular to the X direction and the Y direction (of the substrate 13. (Thickness direction) is shown respectively.

図１３を参照するに、第１の実施の形態の変形例に係る半導体装置１０Ａは、基板１３の一方の面１３ａ及び他方の面１３ｂに、対向配置された一対のＧＮＤパターン１７ｇ１及び１７ｇ２が設けられている点、並びに、ＧＮＤパターン１７ｇ１が第４ビアホール１６ｇを介して第１絶縁層１６ａ上に形成されたＧＮＤパターン１７ｇ３と接続されている点、を除いて第１の実施の形態に係る半導体装置１０と同一構造である。以下、半導体装置１０Ａについて、半導体装置１０と同一構造の部分についてはその説明を省略し、半導体装置１０と異なる部分を中心に説明する。 Referring to FIG. 13, a semiconductor device 10A according to a modification of the first embodiment, on the one surface 13a and the other surface 13b of the substrate 13, a pair of GND pattern arranged opposite 17 g 1 and 17 g 2 that are provided, as well, that the GND pattern 17 g 1 is connected to the GND pattern 17 g 3 formed on the first insulating layer 16a through the fourth via hole 16g, the first embodiment except for the The structure is the same as that of the semiconductor device 10 according to the embodiment. Hereinafter, the description of the semiconductor device 10 </ b> A will be omitted with respect to portions having the same structure as the semiconductor device 10, and portions different from the semiconductor device 10 will be mainly described.

半導体装置１０Ａにおいて、第１ビアホール１６ｘ内の第１配線層１７ａ、第３ビアホール１６ｚ内の第２配線層１７ｂ、及びそれらを接続する複数の線状導体１２には、所定の信号電流が流れる。又、図１３（ｂ）に示すように、ＧＮＤパターン１７ｇ１及び１７ｇ２は、第１ビアホール１６ｘ内の第１配線層１７ａ、及び第３ビアホール１６ｚ内の第２配線層１７ｂが基板１３の一方の面１３ａ及び他方の面１３ｂに接する部分の周囲に、所定の間隔を空けて形成されている。又、ＧＮＤパターン１７ｇ１と１７ｇ２とは、複数の線状導体１２を介して電気的に接続されている。 In the semiconductor device 10A, a predetermined signal current flows through the first wiring layer 17a in the first via hole 16x, the second wiring layer 17b in the third via hole 16z, and the plurality of linear conductors 12 connecting them. Further, as shown in FIG. 13 (b), GND pattern 17 g 1 and 17 g 2 are the first wiring layer 17a within the first via hole 16x, and a third second wiring layer 17b in the via hole 16z one substrate 13 Is formed around the portion in contact with the surface 13a and the other surface 13b with a predetermined interval. Further, the GND pattern 17 g 1 and 17 g 2, are electrically connected through a plurality of linear conductors 12.

ＧＮＤパターン１７ｇ１は、第４ビアホール１６ｇを介して第１絶縁層１６ａ上に形成されたＧＮＤパターン１７ｇ３と接続されている。すなわち、ＧＮＤパターン１７ｇ１〜１７ｇ３は、何れもＧＮＤ（基準電位）に接続されたパタ−ンである。なお、ＧＮＤパターン１７ｇ１は、第１配線層１７ａの一部である。 GND pattern 17 g 1 is connected to the GND pattern 17 g 3 formed on the first insulating layer 16a through the fourth via hole 16g. That is, the GND patterns 17g 1 to 17g 3 are all patterns connected to GND (reference potential). Incidentally, GND pattern 17 g 1 are part of the first wiring layer 17a.

ＧＮＤパターン１７ｇ１及び１７ｇ２は、例えばスパッタ法やめっき法により、基板１３の一方の面１３ａ及び他方の面１３ｂに形成することができる。ＧＮＤパターン１７ｇ１及び１７ｇ２の材料としては、例えば銅（Ｃｕ）等を用いることができる。 GND pattern 17 g 1 and 17 g 2, for example by sputtering or plating, can be formed on the one surface 13a and the other surface 13b of the substrate 13. As a material of the GND pattern 17 g 1 and 17 g 2, may be copper (Cu) or the like.

このように、基板１３において、信号電流が流れる複数の線状導体１２の周囲には、所定の間隔を空けてＧＮＤに接続された複数の線状導体１２が配置されている。この構造は、同軸線路と同等の構造であるため、シールド（遮蔽）効果を奏することができる。又、隣接して配置される信号電流が流れる複数の線状導体間には、ＧＮＤに接続された複数の線状導体が配置されることになるため、隣接して配置される信号電流が流れる複数の線状導体間に生じる電気的結合（容量結合）を低減することが可能となり、信号電流が流れる複数の線状導体自体がノイズ源となることを防止することができる。   As described above, on the substrate 13, the plurality of linear conductors 12 connected to the GND at predetermined intervals are arranged around the plurality of linear conductors 12 through which the signal current flows. Since this structure is equivalent to a coaxial line, a shielding (shielding) effect can be achieved. Further, since a plurality of linear conductors connected to GND are arranged between a plurality of linear conductors through which signal currents arranged adjacently flow, signal currents arranged adjacently flow. It is possible to reduce electrical coupling (capacitive coupling) generated between the plurality of linear conductors, and it is possible to prevent the plurality of linear conductors themselves through which a signal current flows from becoming a noise source.

なお、第１絶縁層１６ａの第１ビアホール１６ｘの周囲、及び第２絶縁層１６ｂの第３ビアホール１６ｚの周囲に、円環状の貫通孔を形成して導体を充填し、ＧＮＤパターン１７ｇ１〜１７ｇ３と接続しても構わない。これにより、第１絶縁層１６ａ及び第２絶縁層１６ｂにも、基板１３に形成した同軸線路と同等の構造が形成されるため、同等の効果が得られる。 An annular through hole is formed around the first via hole 16x of the first insulating layer 16a and the third via hole 16z of the second insulating layer 16b to fill the conductor, and the GND patterns 17g 1 to 17g 3 may be connected. Thereby, since the structure equivalent to the coaxial line formed in the board | substrate 13 is formed also in the 1st insulating layer 16a and the 2nd insulating layer 16b, an equivalent effect is acquired.

このように、第１の実施の形態の変形例によれば、第１の実施の形態と同様の効果を奏するが、更に以下の効果を奏する。   As described above, according to the modification of the first embodiment, the same effects as those of the first embodiment are obtained, but the following effects are further obtained.

すなわち、第１の実施の形態の変形例に係る半導体装置では、基板内に同軸線路と同等の構造を形成することにより、シールド（遮蔽）効果を奏することができる。又、隣接して配置される信号電流が流れる複数の線状導体との間に生じる電気的結合（容量結合）を低減することが可能となり、信号電流が流れる複数の線状導体自体がノイズ源となることを防止することができる。   That is, in the semiconductor device according to the modification of the first embodiment, a shield (shielding) effect can be achieved by forming a structure equivalent to the coaxial line in the substrate. In addition, it is possible to reduce electrical coupling (capacitive coupling) generated between a plurality of linear conductors through which signal currents flow adjacently, and the plurality of linear conductors through which signal currents flow are themselves noise sources. Can be prevented.

〈第２の実施の形態〉
図１４は、第２の実施の形態に係る半導体装置を例示する断面図である。図１４において、図３に示す半導体装置１０と同一構成部分には同一符号を付し、その説明を省略する場合がある。図１４において、Ｘ方向は基板１３の一方の面１３ａと平行な方向、Ｙ方向はＸ方向に垂直な方向（紙面奥行き方向）、Ｚ方向はＸ方向及びＹ方向に垂直な方向（基板１３の厚さ方向）をそれぞれ示している。 <Second Embodiment>
FIG. 14 is a cross-sectional view illustrating a semiconductor device according to the second embodiment. 14, the same components as those of the semiconductor device 10 shown in FIG. 3 are denoted by the same reference numerals, and the description thereof may be omitted. In FIG. 14, the X direction is a direction parallel to one surface 13 a of the substrate 13, the Y direction is a direction perpendicular to the X direction (depth direction on the paper surface), and the Z direction is a direction perpendicular to the X direction and the Y direction (of the substrate 13. (Thickness direction) is shown respectively.

図１４を参照するに、第２の実施の形態に係る半導体装置２０は、半導体素子２４及び絶縁性樹脂２５が追加された点を除いて第１の実施の形態に係る半導体装置１０と同一構造である。このように、本発明に係る半導体装置は、複数の半導体素子を有していても構わない。   Referring to FIG. 14, the semiconductor device 20 according to the second embodiment has the same structure as the semiconductor device 10 according to the first embodiment except that a semiconductor element 24 and an insulating resin 25 are added. It is. Thus, the semiconductor device according to the present invention may have a plurality of semiconductor elements.

なお、第２の実施の形態に係る半導体装置２０の製造方法は、第１の実施の形態に係る半導体装置１０の製造方法と同一である。   The method for manufacturing the semiconductor device 20 according to the second embodiment is the same as the method for manufacturing the semiconductor device 10 according to the first embodiment.

このように、第２の実施の形態によれば、第１の実施の形態と同様の効果を奏するが、更に以下の効果を奏する。   As described above, according to the second embodiment, the same effects as those of the first embodiment are obtained, but the following effects are further obtained.

すなわち、第２の実施の形態に係る半導体装置では、複数の半導体素子を内蔵するため、実装密度を更に高めることができる。   That is, since the semiconductor device according to the second embodiment includes a plurality of semiconductor elements, the mounting density can be further increased.

以上、好ましい実施の形態について詳説したが、上述した実施の形態に制限されることはなく、特許請求の範囲に記載された範囲を逸脱することなく、上述した実施の形態に種々の変形及び置換を加えることができる。   The preferred embodiment has been described in detail above. However, the present invention is not limited to the above-described embodiment, and various modifications and replacements are made to the above-described embodiment without departing from the scope described in the claims. Can be added.

例えば、第２の実施の形態に、第１の実施の形態の変形例と同様の変形を加えても構わない。   For example, the same modification as the modification of the first embodiment may be added to the second embodiment.

１０、２０ 半導体装置
１１ 絶縁性基材
１１ｘ 貫通孔
１２ 線状導体
１３ 基板
１３ａ 基板１３の一方の面
１３ｂ 基板１３の他方の面
１４、２４ 半導体素子
１５、２５ 絶縁性樹脂
１６ａ 第１絶縁層
１６ｂ 第２絶縁層
１６ｘ 第１ビアホール
１６ｙ 第２ビアホール
１６ｚ 第３ビアホール
１７ａ 第１配線層
１７ｂ 第２配線層
１７ｇ１、１７ｇ２、１７ｇ３ ＧＮＤパターン
１８ａ 第１ソルダーレジスト層
１８ｂ 第２ソルダーレジスト層
１８ｘ、１８ｙ 開口部
１９ａ 第１はんだバンプ
１９ｂ 第２はんだバンプ
Ｐ 間隔
φ１ 直径 DESCRIPTION OF SYMBOLS 10, 20 Semiconductor device 11 Insulating base material 11x Through-hole 12 Linear conductor 13 Substrate 13a One side 13b of substrate 13 The other side of substrate 13 14, 24 Semiconductor element 15, 25 Insulating resin 16a First insulating layer 16b Second insulating layer 16x First via hole 16y Second via hole 16z Third via hole 17a First wiring layer 17b Second wiring layer 17g 1 , 17g 2 , 17g 3 GND pattern 18a First solder resist layer 18b Second solder resist layer 18x, 18y opening 19a first solder bump 19b second solder bump P interval φ 1 diameter

Claims (10)

一方の面から他方の面に貫通する複数の導体を有する基板と、
前記基板の前記一方の面に形成された、半導体素子を内蔵する第１絶縁層と、
前記第１絶縁層上に形成され、かつ、前記第１絶縁層に設けられた貫通孔を介して前記基板の前記一方の面から露出する複数の導体の一部及び前記半導体素子と電気的に接続された第１配線層と、
前記基板の前記他方の面に形成された第２絶縁層と、
前記第２絶縁層上に形成され、かつ、前記第２絶縁層に設けられた貫通孔を介して前記基板の前記他方の面から露出する前記複数の導体の一部と電気的に接続された第２配線層と、を有する半導体装置。 A substrate having a plurality of conductors penetrating from one surface to the other surface;
A first insulating layer containing a semiconductor element formed on the one surface of the substrate;
A part of the plurality of conductors formed on the first insulating layer and exposed from the one surface of the substrate through a through hole provided in the first insulating layer, and electrically with the semiconductor element A connected first wiring layer;
A second insulating layer formed on the other surface of the substrate;
Formed on the second insulating layer and electrically connected to a part of the plurality of conductors exposed from the other surface of the substrate through a through hole provided in the second insulating layer And a second wiring layer. 前記導体は線状導体である請求項１記載の半導体装置。   The semiconductor device according to claim 1, wherein the conductor is a linear conductor. 前記導体は、隣接する前記導体間の距離が、前記導体の径よりも小さくなるように配置されている請求項１又は２記載の半導体装置。   The semiconductor device according to claim 1, wherein the conductor is disposed such that a distance between adjacent conductors is smaller than a diameter of the conductor. 前記導体は、電気的に孤立した導体を含む請求項１乃至３の何れか一項記載の半導体装置。   The semiconductor device according to claim 1, wherein the conductor includes an electrically isolated conductor. 前記導体は、信号配線と接続されている導体と、前記信号配線と接続されている導体の周囲に位置する導体と、を有し、
前記周囲に位置する導体は、グランド配線と接続されている請求項１乃至４の何れか一項記載の半導体装置。 The conductor has a conductor connected to the signal wiring, and a conductor located around the conductor connected to the signal wiring,
The semiconductor device according to claim 1, wherein the conductor located around is connected to a ground wiring. 前記信号配線と接続されている導体と前記周囲に位置する導体との間には、電気的に孤立した導体が配置されている請求項５記載の半導体装置。   The semiconductor device according to claim 5, wherein an electrically isolated conductor is disposed between a conductor connected to the signal wiring and a conductor located around the conductor. 前記半導体素子が複数個内蔵されている請求項１乃至６の何れか一項記載の半導体装置。   The semiconductor device according to claim 1, wherein a plurality of the semiconductor elements are incorporated. 前記導体の径は、３０ｎｍ〜２０００ｎｍである請求項１乃至７の何れか一項記載の半導体装置。   The semiconductor device according to claim 1, wherein the conductor has a diameter of 30 nm to 2000 nm. 前記基板は、酸化アルミニウムを含んでいる請求項１乃至８の何れか一項記載の半導体装置。   The semiconductor device according to claim 1, wherein the substrate contains aluminum oxide. 一方の面から他方の面に貫通する複数の導体を有する基板を準備する第１工程と、
前記基板の前記一方の面に半導体素子を固着する第２工程と、
前記基板の前記一方の面に、前記半導体素子を被覆する第１絶縁層を形成する第３工程と、
前記第１絶縁層上に、前記第１絶縁層に設けられた貫通孔を介して前記基板の前記一方の面から露出する複数の導体の一部及び前記半導体素子と電気的に接続された第１配線層を形成する第４工程と、
前記基板の前記他方の面に、第２絶縁層を形成する第５工程と、
前記第２絶縁層上に、前記第２絶縁層に設けられた貫通孔を介して前記基板の前記他方の面から露出する前記複数の導体の一部と電気的に接続された第２配線層を形成する第６工程と、を有する半導体装置の製造方法。 A first step of preparing a substrate having a plurality of conductors penetrating from one surface to the other;
A second step of fixing a semiconductor element to the one surface of the substrate;
A third step of forming a first insulating layer covering the semiconductor element on the one surface of the substrate;
On the first insulating layer, through a through hole provided in the first insulating layer, a plurality of conductors exposed from the one surface of the substrate and electrically connected to the semiconductor element A fourth step of forming one wiring layer;
A fifth step of forming a second insulating layer on the other surface of the substrate;
A second wiring layer electrically connected to a part of the plurality of conductors exposed from the other surface of the substrate through a through hole provided in the second insulating layer on the second insulating layer And a sixth step of forming the semiconductor device.
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JP2010283056A (en) * 2009-06-03 2010-12-16 Shinko Electric Ind Co Ltd Wiring board
JP2013033894A (en) * 2011-06-27 2013-02-14 Shinko Electric Ind Co Ltd Wiring board, manufacturing method of the same and semiconductor device

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JP2007080928A (en) * 2005-09-12 2007-03-29 Sumitomo Bakelite Co Ltd Circuit board with built-in semiconductor element and semiconductor device
JP2009147241A (en) * 2007-12-18 2009-07-02 Taiyo Yuden Co Ltd Circuit board, its manufacturing method and circuit module

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JP2007080928A (en) * 2005-09-12 2007-03-29 Sumitomo Bakelite Co Ltd Circuit board with built-in semiconductor element and semiconductor device
JP2009147241A (en) * 2007-12-18 2009-07-02 Taiyo Yuden Co Ltd Circuit board, its manufacturing method and circuit module

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010283056A (en) * 2009-06-03 2010-12-16 Shinko Electric Ind Co Ltd Wiring board
JP2013033894A (en) * 2011-06-27 2013-02-14 Shinko Electric Ind Co Ltd Wiring board, manufacturing method of the same and semiconductor device

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