JP2010177710A - 半導体装置 - Google Patents
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- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
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- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
- H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
- H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
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- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
- H01L2924/13055—Insulated gate bipolar transistor [IGBT]
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Abstract
【解決手段】絶縁基板4の主面に半導体チップ(IGBT6a,FWD6b)をマウントし、該半導体チップの上面電極とその電極に対応して絶縁基板に形成した配線用パターンとの間をワイヤ7で配線した半導体装置において、配線用パターンをパターン4c〜4f分けた上で、半導体チップをマウントする主面導体パターン4a,4bの上面周域に積層したセラミック絶縁層11を介して2階建て式に層設する。これにより、配線用パターンに規制されることなく主面導体パターンの投影面積を拡張し、半導体チップからの熱流束を基板の面方向に広く分散させて絶縁基板の熱抵抗低化が図れる。
【選択図】 図1
Description
(1)前記の配線用パターンをセラミック絶縁層の上面に形成し、該セラミック絶縁層の裏面をメタライズした上で絶縁基板の主面導体パターンにろう付けする。
(2)前記の配線用パターンをセラミック絶縁層の上面に形成し、該セラミック絶縁層を絶縁基板の主面導体パターンに接着剤で固着する(請求項1)。
(3)前記の配線用パターンを、噴射成膜法により絶縁基板の主面導体パターン上に成膜したセラミック絶縁層の上面に形成する(請求項2)。
(4)また、前記各項の半導体装置において、絶縁基板の主面側導体パターンと導電接続する配線用パターンについては、その絶縁層に形成したスルーホールを介して絶縁基板の主面導体パターンに接続する(請求項3)、あるいはワイヤもしくはリボン状リードを介して絶縁基板の主面導体パターンに接続する(請求項4)。
(5)さらに、前記の配線用パターンを導体箔として絶縁層の上面からはみ出すように延長して形成し、その導体箔の延長部をパッケージ外方に引き出して外部端子として使用する(請求項5)。
さらに、前記の配線用パターンを導体箔として絶縁層の上面からはみ出すように延長して形成し、この延長部分を外部端子として使用するようにしたことで、外囲ケースの外部端子が不要となって部品点数の削減とともに、パッケージをコンパクトに構成できる。
図4(a),(b)において、絶縁基板2に対してその主面側にはセラミック基板3の面域に主面導体パターン(銅箔)4aが形成され、その導体パターン4aの中央には半導体チップとしてIGBT6aがマウントされている。また、導体パターン4aの周縁部には半導体チップの上面電極(半導体チップがIGBTの場合はエミッタ電極,ゲート電極、半導体チップがFWDである場合にはカソード)に対応する配線用パターン4d,4eがセラミック絶縁層11を介して層設されている。ここで、配線用パターン4d,4eはIGBT6aを中央にしてその左右両側に対向する辺に振り分けて平行に設けられており、外部端子10(E,C,G)は配線用パターン4d,4eのパターンエンドと対向する絶縁基板2の上辺側に一列に並べて設けられている。そして、各配線用パターン4d,4eとIGBT6aの上面電極(エミッタ電極,ゲート電極)との間にワイヤリード7を配線している。
2 絶縁基板
3 セラミック板
4 主面側導体パターン
4a,4b 主面導体パターン
4c〜4f 配線用パターン
6 半導体チップ
6a IGBT
6b FWD
7 リードワイヤ
8 外囲ケース
10 外部端子
11 セラミック絶縁層
12 スルーホール
13 リボン状リード
Claims (5)
- 絶縁基板の主面に半導体チップをマウントし、該半導体チップの上面電極とその電極に対応して絶縁基板の主面側に形成した配線用パターンとの間をリード配線した半導体装置において、
前記の配線用パターンを、絶縁基板の主面側に形成して半導体チップをマウントする主面導体パターンの上に絶縁層を介して層設し、さらに、
前記の配線用パターンをセラミック絶縁層の上面に形成し、該セラミック絶縁層を絶縁基板の主面導体パターンに接着して固着したことを特徴とする半導体装置。 - 絶縁基板の主面に半導体チップをマウントし、該半導体チップの上面電極とその電極に対応して絶縁基板の主面側に形成した配線用パターンとの間をリード配線した半導体装置において、
前記の配線用パターンを、絶縁基板の主面側に形成して半導体チップをマウントする主面導体パターンの上に絶縁層を介して層設し、さらに、
前記の配線用パターンを、噴射成膜法により絶縁基板の主面導体パターン上に成膜したセラミック絶縁層の上面に形成したことを特徴とする半導体装置。 - 請求項1または2記載の半導体装置において、絶縁基板の主面側導体パターンと導電接続する配線用パターンについては、その絶縁層に形成したスルーホールを介して絶縁基板の主面導体パターンに接続したことを特徴とする半導体装置。
- 請求項1または2記載の半導体装置において、絶縁基板の主面側導体パターンと導電接続する配線用パターンについては、ワイヤもしくはリボン状のリードを介して絶縁基板の主面導体パターンに接続したことを特徴とする半導体装置。
- 請求項1または2記載の半導体装置において、配線用パターンを導体箔として絶縁層の上面からはみ出すように延長して形成し、その延長部分をパッケージの外方に引き出して外部端子としたことを特徴とする半導体装置。
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Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
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CN103295980A (zh) * | 2012-03-05 | 2013-09-11 | 上海沪通企业集团有限公司 | 单管igbt封装全桥模块及其封装方法 |
JP2013251875A (ja) * | 2012-06-04 | 2013-12-12 | Olympus Medical Systems Corp | 制御信号変換装置、コントローラ、被制御機器、機器制御システム、及び状態検出方法 |
CN111987091A (zh) * | 2019-05-21 | 2020-11-24 | 三菱电机株式会社 | 半导体装置 |
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Publication number | Priority date | Publication date | Assignee | Title |
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JP6915890B2 (ja) | 2019-03-14 | 2021-08-04 | 株式会社タムラ製作所 | 駆動回路装置 |
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JPH09283700A (ja) * | 1996-04-16 | 1997-10-31 | Kyocera Corp | 高周波用電力増幅器 |
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JP2003218269A (ja) * | 2001-04-03 | 2003-07-31 | National Institute Of Advanced Industrial & Technology | 回路基板とその作製方法 |
JP2003309211A (ja) * | 2002-04-18 | 2003-10-31 | Anritsu Corp | 高周波用半導体装置 |
JP2003347705A (ja) * | 2002-05-28 | 2003-12-05 | Matsushita Electric Ind Co Ltd | 回路部品モジュールおよびその製造方法 |
JP2004095795A (ja) * | 2002-08-30 | 2004-03-25 | Toto Ltd | 回路素子内蔵型基板およびその製造方法 |
JP2004146818A (ja) * | 2002-10-01 | 2004-05-20 | Hitachi Metals Ltd | セラミック積層基板および高周波電子部品 |
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CN111987091B (zh) * | 2019-05-21 | 2024-06-07 | 三菱电机株式会社 | 半导体装置 |
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