JP2009501432A - 非対称性誘電領域を備える半導体装置の形成方法及びその半導体装置の構造 - Google Patents
非対称性誘電領域を備える半導体装置の形成方法及びその半導体装置の構造 Download PDFInfo
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Abstract
Description
図中の要素は、簡単さ、明確さのために例示されており、必ずしも実寸に従い図示されていないことは、当業者にとって明白である。例えば、図中の幾つかの要素の寸法は、他の要素と比べて誇張されており、それにより、本発明の実施形態の理解を容易にしている。
しかも、説明及び請求項において、用語「後ろ」、「上端」、「底」、「上方」、「下方」等は、存在する場合、説明目的で使用され、必ずしも永久的な相対位置を述べるためではない。当然のことながら、そのように用いられる用語は、本明細書に記載された本発明の実施形態が、例えば、本明細書に例示されるか、そうでなければ、説明にはない方向への動作を実現すべく、適切な状況の下で置換することができる。
Claims (20)
- 半導体装置を形成する方法であって、
半導体基板を形成するステップ、
前記半導体基板の上方に、第一側面及び第二側面を備えたゲート電極を形成するステップ、及び
前記ゲート電極の下方にゲート誘電体を形成するステップであって、前記ゲート誘電体は、前記ゲート電極の下方で前記ゲート電極の前記第一側面に隣接した第一領域と、前記ゲート電極の下方で前記ゲート電極の前記第二側面に隣接した第二領域と、前記ゲート電極の下方で前記第一領域及び前記第二領域間にある第三領域とからなるステップを備え、
前記第一領域は前記第二領域よりも薄く、前記第三領域は前記第一領域よりも薄く、更に前記第二領域よりも薄い方法。 - 請求項1記載の方法において、
前記ゲート電極の下方に前記ゲート誘電体を形成するステップは、更に、
第一誘電体層を形成するステップ、
前記半導体基板内に酸化促進種を注入して酸化促進領域を形成するステップ、及び前記酸化促進領域を酸化するステップ
を備える方法。 - 請求項2記載の方法において、
前記酸化促進種を注入するステップは、更に、前記酸化促進種を前記ゲート電極内に注入して酸化促進領域を形成するステップを備える方法。 - 請求項2記載の方法において、
前記注入は斜めに行われる方法。 - 請求項1記載の方法において、
前記ゲート電極の下方に前記ゲート誘電体を形成するステップは、更に、
第一誘電体層を形成するステップ、
酸化低減種を前記半導体基板内に注入して酸化低減領域を形成するステップ、及び
前記半導体基板を酸化するステップ
を備える方法。 - 請求項5記載の方法において、
前記酸化促進種を注入するステップは、更に、前記酸化低減種を前記ゲート電極内に注入して酸化低減領域を形成するステップを備える方法。 - 請求項5記載の方法において、
前記注入は斜めに行われる方法。 - 請求項1記載の方法において、
前記ゲート電極の下方に前記ゲート誘電体を形成するステップは、更に、
第一誘電体層を形成するステップ、
酸化促進種を前記半導体基板内に注入して酸化促進領域を形成するステップ、
酸化低減種を前記半導体基板内に注入して酸化低減領域を形成するステップ、及び
前記半導体基板を酸化するステップであって、前記酸化は前記酸化促進領域に誘電体を形成するステップ
を備える方法。 - 請求項1記載の方法は、更に
前記ゲート誘電体を形成した後にソース・エクステンション領域及びドレイン・エクステンション領域を形成するステップを備え、前記ソース・エクステンション領域は、前記ドレイン・エクステンション領域よりも深い方法。 - 請求項1記載の方法は、更に、前記ゲート誘電体を形成した後に前記ゲート電極の前記第一側面に隣接する第一スペーサと、前記ゲート電極の前記第二側面に隣接する第二スペーサとを形成するステップを備える方法。
- 半導体装置の形成方法であって、
半導体基板を提供するステップ、
前記半導体基板の上方に誘電体層を形成するステップ、
前記誘電体層の上方に、第一側面及び前記第一側面と対向する第二側面を備えるゲート電極を形成するステップ、
酸化促進種を前記ゲート電極の前記第一側面及び前記半導体基板の第一領域内に注入するステップであって、前記第一領域は、前記ゲート電極の下方で前記ゲート電極の前記第一側面に隣接するステップ、及び
前記第一領域を第一誘電体に変換し、かつ前記半導体基板の第二領域を第二誘電体に変換するステップであって、前記第二領域は、前記ゲート電極の下方で前記ゲート電極の前記第二側面に隣接し、前記第一誘電体の前記厚さは、前記第二誘電体の前記厚さよりも大きいステップ
を備える方法。 - 請求項11記載の方法において、
前記変換するステップは、前記半導体基板をアニーリングするステップからなる方法。 - 請求項11記載の方法において、
前記注入するステップは、ゲルマニウム、酸素、フッ素及び塩素からなる群より選択された少なくとも一つの種を注入するステップからなる方法。 - 請求項11記載の方法は、更に、酸化低減種を前記第二領域内に注入するステップを備える方法。
- 請求項14記載の方法において、
前記酸化低減種を注入するステップは窒素を注入するステップからなる方法。 - 請求項11記載の方法は、更に、前記第一領域及び前記第二領域の前記変換後にソース・エクステンション領域とドレイン・エクステンション領域とを形成するステップであって、前記ソース・エクステンション領域は、前記ドレイン・エクステンション領域よりも深いステップを備える方法。
- 請求項11記載の方法は、更に、前記変換後、前記ゲート電極の前記第一側面に隣接した第一スペーサと、前記ゲート電極の前記第二側面に隣接した第二スペーサとを形成するステップを備える方法。
- 請求項11記載の方法において、
前記注入は斜めに行われる方法。 - 半導体基板と、
前記半導体基板の上方に、第一側面と第二側面を備えるゲート電極と、
前記ゲート電極の下方のゲート誘電体であって、前記ゲート誘電体は、前記ゲート電極の下方で前記ゲート電極の前記第一側面に隣接した第一領域、前記ゲート電極の下方で前記ゲート電極の前記第二側面に隣接した第二領域、及び前記ゲート電極の下方で前記第一領域及び前記第二領域間にある第三領域とを備え、
前記第一領域は前記第二領域よりも薄く、前記第三領域は前記第一領域よりも薄く、更に前記第二領域よりも薄い半導体装置。 - 請求項19記載の半導体装置において、
前記ゲート電極の前記第一側面は第一誘電体を備え、前記第二側面は第二誘電体を備え、前記第二誘電体は前記第一誘電体よりも厚い半導体装置。
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PCT/US2006/003528 WO2006104562A2 (en) | 2005-03-29 | 2006-02-01 | Method of forming a semiconductor device having asymmetric dielectric regions and structure thereof |
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US6921691B1 (en) * | 2004-03-18 | 2005-07-26 | Infineon Technologies Ag | Transistor with dopant-bearing metal in source and drain |
US8399934B2 (en) | 2004-12-20 | 2013-03-19 | Infineon Technologies Ag | Transistor device |
US8178902B2 (en) | 2004-06-17 | 2012-05-15 | Infineon Technologies Ag | CMOS transistor with dual high-k gate dielectric and method of manufacture thereof |
US7344934B2 (en) | 2004-12-06 | 2008-03-18 | Infineon Technologies Ag | CMOS transistor and method of manufacture thereof |
US7160781B2 (en) | 2005-03-21 | 2007-01-09 | Infineon Technologies Ag | Transistor device and methods of manufacture thereof |
US7361538B2 (en) * | 2005-04-14 | 2008-04-22 | Infineon Technologies Ag | Transistors and methods of manufacture thereof |
US8188551B2 (en) | 2005-09-30 | 2012-05-29 | Infineon Technologies Ag | Semiconductor devices and methods of manufacture thereof |
US20070052037A1 (en) * | 2005-09-02 | 2007-03-08 | Hongfa Luan | Semiconductor devices and methods of manufacture thereof |
US20070052036A1 (en) * | 2005-09-02 | 2007-03-08 | Hongfa Luan | Transistors and methods of manufacture thereof |
US7462538B2 (en) * | 2005-11-15 | 2008-12-09 | Infineon Technologies Ag | Methods of manufacturing multiple gate CMOS transistors having different gate dielectric materials |
US7510943B2 (en) * | 2005-12-16 | 2009-03-31 | Infineon Technologies Ag | Semiconductor devices and methods of manufacture thereof |
US20080050898A1 (en) * | 2006-08-23 | 2008-02-28 | Hongfa Luan | Semiconductor devices and methods of manufacture thereof |
US8999786B1 (en) | 2007-03-20 | 2015-04-07 | Marvell International Ltd. | Reducing source contact to gate spacing to decrease transistor pitch |
KR100950473B1 (ko) * | 2007-12-28 | 2010-03-31 | 주식회사 하이닉스반도체 | 균일한 두께의 게이트스페이서막을 갖는 반도체소자의제조방법 |
KR100997290B1 (ko) * | 2008-07-25 | 2010-11-29 | 주식회사 동부하이텍 | 반도체 소자 및 반도체 소자의 제조 방법 |
WO2011112574A1 (en) * | 2010-03-08 | 2011-09-15 | Mears Technologies, Inc | Semiconductor device including a superlattice and dopant diffusion retarding implants and related methods |
US9397217B2 (en) * | 2012-12-28 | 2016-07-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Contact structure of non-planar semiconductor device |
CN107039522B (zh) * | 2016-02-04 | 2019-12-31 | 中芯国际集成电路制造(上海)有限公司 | 半导体结构及其形成方法 |
WO2018182627A1 (en) * | 2017-03-30 | 2018-10-04 | Intel Corporation | Transistors including asymmetric gate spacers |
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WO2006104562A2 (en) | 2006-10-05 |
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