JP2009231836A - ヘテロエピタキシャル層を備えた半導体ウェハ及び前記ウェハの製造方法 - Google Patents
ヘテロエピタキシャル層を備えた半導体ウェハ及び前記ウェハの製造方法 Download PDFInfo
- Publication number
- JP2009231836A JP2009231836A JP2009064263A JP2009064263A JP2009231836A JP 2009231836 A JP2009231836 A JP 2009231836A JP 2009064263 A JP2009064263 A JP 2009064263A JP 2009064263 A JP2009064263 A JP 2009064263A JP 2009231836 A JP2009231836 A JP 2009231836A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- substrate
- wafer
- stress
- sige
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 7
- 238000004519 manufacturing process Methods 0.000 title claims description 3
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims abstract description 55
- 239000000758 substrate Substances 0.000 claims abstract description 49
- 239000000203 mixture Substances 0.000 claims description 32
- 238000000151 deposition Methods 0.000 claims description 31
- 230000008021 deposition Effects 0.000 claims description 19
- 238000000034 method Methods 0.000 claims description 12
- 238000001816 cooling Methods 0.000 claims description 7
- 230000003746 surface roughness Effects 0.000 abstract description 7
- 230000009467 reduction Effects 0.000 abstract description 3
- 235000012431 wafers Nutrition 0.000 description 42
- 239000013078 crystal Substances 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 3
- 230000000052 comparative effect Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 239000007789 gas Substances 0.000 description 3
- 229910052732 germanium Inorganic materials 0.000 description 3
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 3
- 230000007704 transition Effects 0.000 description 3
- 230000002411 adverse Effects 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000012159 carrier gas Substances 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 230000001627 detrimental effect Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 230000000116 mitigating effect Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02532—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/02373—Group 14 semiconducting materials
- H01L21/02381—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02439—Materials
- H01L21/02441—Group 14 semiconducting materials
- H01L21/0245—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02494—Structure
- H01L21/02496—Layer structure
- H01L21/0251—Graded layers
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Recrystallisation Techniques (AREA)
- Chemical Vapour Deposition (AREA)
Abstract
【解決手段】第1の面及び第2の面を有する基板10、前記基板の第1の面に堆積された完全に又は部分的に緩和されたヘテロエピタキシャル層20、及び前記基板の第2の面に堆積された応力相殺層30を有する、半導体ウェハ。
【選択図】図2
Description
Claims (11)
- 第1の面及び第2の面を有する基板、
前記基板の第1の面に堆積された完全に又は部分的に緩和されたヘテロエピタキシャル層、及び
前記基板の第2の面に堆積された応力相殺層を有する、半導体ウェハ。 - ヘテロエピタキシャル層の厚さ及び組成は、応力相殺層の厚さ及び組成と同じ又は同等である、請求項1記載のウェハ。
- 応力相殺層は、基板に堆積された勾配したSiGe層と、前記勾配したSiGe層に堆積された一定の組成のSiGe層とを有する、請求項1記載のウェハ。
- 応力相殺層は、基板に堆積されかつ組成Si(1-x)Gexを有する一定の組成のSiGe層を有する、請求項1記載のウェハ。
- 一定の組成のSiGe層中のGeの濃度は、10〜80%である、請求項4記載のウェハ。
- 基板の第1の面に完全に又は部分的に緩和されたヘテロエピタキシャル層を所定の堆積温度で堆積させ、かつ
前記ウェハを前記堆積温度から冷却する前に、前記基板の第2の面に応力相殺層を提供することを有する、半導体ウェハの製造方法。 - 基板の第1の面に完全に又は部分的に緩和されたヘテロエピタキシャル層を堆積させる前に、前記基板の第2の面に応力相殺層を堆積させることにより、応力相殺層を提供する、請求項6記載の方法。
- 基板の第1の面に完全に又は部分的に緩和されたヘテロエピタキシャル層を堆積させる間に、前記基板の第2の面に応力相殺層を堆積させることにより、応力相殺を提供する、請求項6記載の方法。
- 応力相殺層として、完全に又は部分的に緩和されたヘテロエピタキシャル層と同じ又は同等の厚さ及び組成を有する層を提供する、請求項6記載の方法。
- 基板の第2の面に勾配したSiGe層を堆積させ、前記勾配したSiGe層上に一定の組成のSiGe層を堆積させることを有する、請求項6記載の方法。
- 基板の第2の面に組成Si(1-x)Gexを有する一定の組成のSiGe層を堆積させることを有する、請求項6記載の方法。
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP08005334.1A EP2104135B1 (en) | 2008-03-20 | 2008-03-20 | A semiconductor wafer with a heteroepitaxial layer and a method for producing the wafer |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2012175158A Division JP5656936B2 (ja) | 2008-03-20 | 2012-08-07 | ヘテロエピタキシャル層を備えた半導体ウェハ及び前記ウェハの製造方法 |
Publications (1)
Publication Number | Publication Date |
---|---|
JP2009231836A true JP2009231836A (ja) | 2009-10-08 |
Family
ID=39637658
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2009064263A Pending JP2009231836A (ja) | 2008-03-20 | 2009-03-17 | ヘテロエピタキシャル層を備えた半導体ウェハ及び前記ウェハの製造方法 |
JP2012175158A Active JP5656936B2 (ja) | 2008-03-20 | 2012-08-07 | ヘテロエピタキシャル層を備えた半導体ウェハ及び前記ウェハの製造方法 |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2012175158A Active JP5656936B2 (ja) | 2008-03-20 | 2012-08-07 | ヘテロエピタキシャル層を備えた半導体ウェハ及び前記ウェハの製造方法 |
Country Status (7)
Country | Link |
---|---|
US (1) | US20090236695A1 (ja) |
EP (1) | EP2104135B1 (ja) |
JP (2) | JP2009231836A (ja) |
KR (1) | KR101037636B1 (ja) |
CN (1) | CN101552271B (ja) |
SG (1) | SG155840A1 (ja) |
TW (1) | TWI398909B (ja) |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2013012750A (ja) * | 2008-03-20 | 2013-01-17 | Siltronic Ag | ヘテロエピタキシャル層を備えた半導体ウェハ及び前記ウェハの製造方法 |
JP2013149733A (ja) * | 2012-01-18 | 2013-08-01 | Seiko Epson Corp | 半導体基板及び半導体基板の製造方法 |
KR20160029664A (ko) | 2014-09-05 | 2016-03-15 | 도쿄엘렉트론가부시키가이샤 | 성막 방법 및 성막 장치 |
KR20160052329A (ko) | 2014-10-29 | 2016-05-12 | 도쿄엘렉트론가부시키가이샤 | 선택 성장 방법 및 기판 처리 장치 |
KR20180111537A (ko) | 2017-03-30 | 2018-10-11 | 도쿄엘렉트론가부시키가이샤 | 선택 성장 방법 |
CN111094620A (zh) * | 2017-08-31 | 2020-05-01 | 朗姆研究公司 | 用于在衬底选择侧上沉积的pecvd沉积*** |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI470831B (zh) * | 2011-06-30 | 2015-01-21 | Siltronic Ag | 分層半導體基材及其製造方法 |
EP2541589B1 (en) | 2011-06-30 | 2013-08-28 | Siltronic AG | Layered semiconductor substrate and method for manufacturing it |
CN103523738B (zh) | 2012-07-06 | 2016-07-06 | 无锡华润上华半导体有限公司 | 微机电***薄片及其制备方法 |
US9558943B1 (en) * | 2015-07-13 | 2017-01-31 | Globalfoundries Inc. | Stress relaxed buffer layer on textured silicon surface |
CN107845569A (zh) * | 2017-11-02 | 2018-03-27 | 江苏华功半导体有限公司 | 一种复合衬底及其制备方法 |
CN113948391B (zh) * | 2021-08-30 | 2023-11-21 | 西安电子科技大学 | 一种硅基AlGaN/GaN HEMT器件及制备方法 |
CN114815130B (zh) * | 2022-03-11 | 2023-12-01 | 中国科学院上海光学精密机械研究所 | 基于离子束的光学薄膜元件的面形控制方法 |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05144727A (ja) * | 1991-11-19 | 1993-06-11 | Nippon Steel Corp | ヘテロエピタキシヤルウエーハの製造方法 |
WO2008014079A1 (en) * | 2006-07-24 | 2008-01-31 | Asm America, Inc. | Strained layers within semiconductor buffer structures |
Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE3761349D1 (de) * | 1987-06-10 | 1990-02-08 | Degussa | Verwendung einer edelmetallhaltigen paste zur herstellung von braeunungsgeschirr fuer mikrowellenoefen. |
US4830984A (en) | 1987-08-19 | 1989-05-16 | Texas Instruments Incorporated | Method for heteroepitaxial growth using tensioning layer on rear substrate surface |
JPH05275332A (ja) * | 1992-03-26 | 1993-10-22 | Shimadzu Corp | ヘテロエピタキシャル膜の製膜方法 |
US5562770A (en) | 1994-11-22 | 1996-10-08 | International Business Machines Corporation | Semiconductor manufacturing process for low dislocation defects |
WO1998059365A1 (en) * | 1997-06-24 | 1998-12-30 | Massachusetts Institute Of Technology | CONTROLLING THREADING DISLOCATION DENSITIES IN Ge ON Si USING GRADED GeSi LAYERS AND PLANARIZATION |
EP1214735A1 (en) * | 1999-09-20 | 2002-06-19 | Amberwave Systems Corporation | Method of producing relaxed silicon germanium layers |
JP2003158075A (ja) * | 2001-08-23 | 2003-05-30 | Sumitomo Mitsubishi Silicon Corp | 半導体基板の製造方法及び電界効果型トランジスタの製造方法並びに半導体基板及び電界効果型トランジスタ |
GB2369490A (en) * | 2000-11-25 | 2002-05-29 | Mitel Corp | Prevention of wafer distortion when annealing thin films |
US7198671B2 (en) | 2001-07-11 | 2007-04-03 | Matsushita Electric Industrial Co., Ltd. | Layered substrates for epitaxial processing, and device |
JP2003113000A (ja) * | 2001-10-05 | 2003-04-18 | Hitachi Cable Ltd | 半導体エピタキシャルウェハ及びその製造方法 |
JP2006173323A (ja) * | 2004-12-15 | 2006-06-29 | Toshiba Ceramics Co Ltd | 歪みシリコンウェーハの製造方法 |
FR2921515B1 (fr) | 2007-09-25 | 2010-07-30 | Commissariat Energie Atomique | Procede de fabrication de structures semiconductrices utiles pour la realisation de substrats semiconducteur- sur-isolant, et ses applications. |
EP2104135B1 (en) * | 2008-03-20 | 2013-06-12 | Siltronic AG | A semiconductor wafer with a heteroepitaxial layer and a method for producing the wafer |
-
2008
- 2008-03-20 EP EP08005334.1A patent/EP2104135B1/en active Active
-
2009
- 2009-02-20 SG SG200901228-7A patent/SG155840A1/en unknown
- 2009-02-26 US US12/393,143 patent/US20090236695A1/en not_active Abandoned
- 2009-03-17 JP JP2009064263A patent/JP2009231836A/ja active Pending
- 2009-03-18 KR KR1020090023112A patent/KR101037636B1/ko active IP Right Grant
- 2009-03-20 TW TW098109104A patent/TWI398909B/zh active
- 2009-03-20 CN CN2009101289643A patent/CN101552271B/zh active Active
-
2012
- 2012-08-07 JP JP2012175158A patent/JP5656936B2/ja active Active
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05144727A (ja) * | 1991-11-19 | 1993-06-11 | Nippon Steel Corp | ヘテロエピタキシヤルウエーハの製造方法 |
WO2008014079A1 (en) * | 2006-07-24 | 2008-01-31 | Asm America, Inc. | Strained layers within semiconductor buffer structures |
Cited By (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2013012750A (ja) * | 2008-03-20 | 2013-01-17 | Siltronic Ag | ヘテロエピタキシャル層を備えた半導体ウェハ及び前記ウェハの製造方法 |
JP2013149733A (ja) * | 2012-01-18 | 2013-08-01 | Seiko Epson Corp | 半導体基板及び半導体基板の製造方法 |
KR20160029664A (ko) | 2014-09-05 | 2016-03-15 | 도쿄엘렉트론가부시키가이샤 | 성막 방법 및 성막 장치 |
US9966256B2 (en) | 2014-09-05 | 2018-05-08 | Tokyo Electron Limited | Film forming method and film forming apparatus |
KR20160052329A (ko) | 2014-10-29 | 2016-05-12 | 도쿄엘렉트론가부시키가이샤 | 선택 성장 방법 및 기판 처리 장치 |
US9512541B2 (en) | 2014-10-29 | 2016-12-06 | Tokyo Electron Limited | Selective growth method and substrate processing apparatus |
KR20180111537A (ko) | 2017-03-30 | 2018-10-11 | 도쿄엘렉트론가부시키가이샤 | 선택 성장 방법 |
US10546741B2 (en) | 2017-03-30 | 2020-01-28 | Tokyo Electron Limited | Selective growth method |
CN111094620A (zh) * | 2017-08-31 | 2020-05-01 | 朗姆研究公司 | 用于在衬底选择侧上沉积的pecvd沉积*** |
CN111094620B (zh) * | 2017-08-31 | 2022-09-09 | 朗姆研究公司 | 用于在衬底选择侧上沉积的pecvd沉积*** |
Also Published As
Publication number | Publication date |
---|---|
US20090236695A1 (en) | 2009-09-24 |
CN101552271B (zh) | 2012-07-11 |
KR20090101103A (ko) | 2009-09-24 |
JP5656936B2 (ja) | 2015-01-21 |
KR101037636B1 (ko) | 2011-05-30 |
SG155840A1 (en) | 2009-10-29 |
TWI398909B (zh) | 2013-06-11 |
EP2104135A1 (en) | 2009-09-23 |
JP2013012750A (ja) | 2013-01-17 |
CN101552271A (zh) | 2009-10-07 |
EP2104135B1 (en) | 2013-06-12 |
TW200943393A (en) | 2009-10-16 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP5656936B2 (ja) | ヘテロエピタキシャル層を備えた半導体ウェハ及び前記ウェハの製造方法 | |
US8093143B2 (en) | Method for producing a wafer comprising a silicon single crystal substrate having a front and a back side and a layer of SiGe deposited on the front side | |
KR101971597B1 (ko) | 웨이퍼 및 박막 제조 방법 | |
JP2008290898A (ja) | 低抵抗率炭化珪素単結晶基板 | |
EP2064730A2 (en) | Nitride semiconductor structures with interlayer structures and methods of fabricating nitride semiconductor structures with interlayer structures | |
JP2011219297A (ja) | 炭化珪素単結晶基板、炭化珪素エピタキシャルウェハ、及び薄膜エピタキシャルウェハ | |
JP2006080278A (ja) | 歪みシリコンウエハおよびその製造方法 | |
JP2004175658A (ja) | シリコンウェーハおよびエピタキシャルシリコンウェーハ | |
JP6052465B2 (ja) | エピタキシャル炭化珪素ウエハの製造方法 | |
US8115195B2 (en) | Semiconductor wafer with a heteroepitaxial layer and a method for producing the wafer | |
JP2004363510A (ja) | 半導体基板の製造方法 | |
JP2004349522A (ja) | 半導体基板の製造方法 | |
WO2013150587A1 (ja) | 単結晶SiCエピタキシャル基板の製造方法および単結晶SiCエピタキシャル基板 | |
CN101540317A (zh) | 具有异质外延层的半导体晶片以及制造该晶片的方法 | |
JP6636239B2 (ja) | 単結晶ダイヤモンドの製造方法、単結晶ダイヤモンド、単結晶ダイヤモンド基板の製造方法、単結晶ダイヤモンド基板及び半導体デバイス | |
JP2006173323A (ja) | 歪みシリコンウェーハの製造方法 | |
KR102128495B1 (ko) | 에피택셜 웨이퍼 | |
JP2004349374A (ja) | 歪みシリコン基板ウエハの製造方法 | |
KR101905860B1 (ko) | 웨이퍼 제조 방법 | |
Nitta et al. | Carbon doping effect on strain relaxation during Si1− x− yGexCy epitaxial growth on Si (1 0 0) at 500° C | |
KR20130045493A (ko) | 웨이퍼 및 박막 제조 방법 | |
KR20130000297A (ko) | 웨이퍼 제조 방법 | |
KR20130000302A (ko) | 웨이퍼 제조 방법 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
RD04 | Notification of resignation of power of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7424 Effective date: 20101227 |
|
RD04 | Notification of resignation of power of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7424 Effective date: 20101228 |
|
RD02 | Notification of acceptance of power of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7422 Effective date: 20111024 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A821 Effective date: 20111117 |
|
RD04 | Notification of resignation of power of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7424 Effective date: 20111117 |
|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20120312 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20120426 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20120508 |
|
A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 20121009 |