JP2009231296A - Heat radiation type multiple hole semiconductor package - Google Patents

Heat radiation type multiple hole semiconductor package Download PDF

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JP2009231296A
JP2009231296A JP2008070841A JP2008070841A JP2009231296A JP 2009231296 A JP2009231296 A JP 2009231296A JP 2008070841 A JP2008070841 A JP 2008070841A JP 2008070841 A JP2008070841 A JP 2008070841A JP 2009231296 A JP2009231296 A JP 2009231296A
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semiconductor package
substrate
type multi
chip
group
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JP4647673B2 (en
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Bing-Shun Yu
秉▲勲▼ 余
Jinwei Hong
菁蔚 洪
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Powertech Technology Inc
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Powertech Technology Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73215—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

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  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a heat radiation type multiple hole semiconductor package for preventing a built-in heat sink from being separated by reinforcing heat radiation properties and reducing the warpage of a substrate. <P>SOLUTION: The heat radiation type multiple hole semiconductor package includes: the substrate 210; a chip 220; the built-in type heat sink 230; and a sealed body 240. The substrate 210 includes: an upper surface 211, a lower surface 212, and a plurality of positioning holes 213; the chip 220 is installed on the upper surface 211; and the built-in type heat sink 230 is stuck to the chip 220. The built-in type heat sink 230 includes a plurality of support leads 231 and a heat radiation surface 232, and the group of support leads 231 is inserted into the group of positioning holes 213. Since the group of positioning holes 213 is not fully filled into the group of support leads 231, a plurality of mold flow passages 241 are formed. The sealed body 240 is formed on the upper surface 211 to seal the chip 220 and the built-in type heat sink 230. By exposing the heat radiation surface 232 and filling the mold flow passage 241, the group of support leads 231 is covered. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

本発明は半導体パッケージに関し、特に放熱型多穿孔半導体パッケージに関する。   The present invention relates to a semiconductor package, and more particularly to a heat radiation type multi-perforated semiconductor package.

通常、チップを基板の上に設置し、外部からの汚染を避けるために封止体で密封している。近年、半導体実装技術の進歩とチップ機能の向上によってチップ演算の速度はますます速くなるとともに、チップの温度もより高温に上昇する。該半導体素子（例えば、チップと封止体）本体表面には熱を発散する作用があるとは言っても、チップの周波数或はパワーが大きくなればなるほど、演算の際のチップの発熱量はより大きくなり、電子素子本体のみの放熱効率では最早熱を発散させることができない。故に、チップから発生した熱を外部へ効率的に発散することができなくなると、チップ温度が高くなって、チップ損傷、パッケージの反り、基板からの半導体素子の剥離などの問題が容易に起きる。   Usually, a chip is placed on a substrate and sealed with a sealing body in order to avoid external contamination. In recent years, with the progress of semiconductor mounting technology and the improvement of chip function, the speed of chip calculation becomes higher and the temperature of the chip also rises to a higher temperature. Although the surface of the semiconductor element (eg, chip and sealing body) has a function of dissipating heat, the higher the frequency or power of the chip, the greater the amount of heat generated by the chip during computation. It becomes larger and heat can no longer be dissipated with the heat dissipation efficiency of the electronic element body alone. Therefore, if the heat generated from the chip cannot be efficiently dissipated to the outside, the chip temperature becomes high, and problems such as chip damage, package warpage, and peeling of the semiconductor element from the substrate easily occur.

図１に示すように、従来の半導体パッケージ１００は基板１１０、チップ１２０、封止体１４０及び複数の外接端子１６０を備える。基板１１０は上表面１１１、下表面１１２及び基板１１０を貫通するスロット１１４を有し、チップ１２０は主面１２１、背面１２２及び主面１２１に形成される複数のボンディングパッド１２３を有する。ダイアタッチング層１７０を用いてチップ１２０の主面１２１を基板１１０の上表面１１１に貼付し、かつボンディングパッド１２３をスロット１１４内に照準させる。複数の電気接続素子１５０、例えばボンディングワイヤはスロット１１４を通過してボンディングパッド１２３群を基板１１０に電気接続している。封止体１４０は基板１１０の上表面１１１に形成されてチップ１２０を密封し、外接端子１６０は基板１１０の下表面１１２に設置されている。   As shown in FIG. 1, the conventional semiconductor package 100 includes a substrate 110, a chip 120, a sealing body 140, and a plurality of external terminals 160. The substrate 110 has an upper surface 111, a lower surface 112, and a slot 114 that penetrates the substrate 110, and the chip 120 has a main surface 121, a back surface 122, and a plurality of bonding pads 123 formed on the main surface 121. The main surface 121 of the chip 120 is affixed to the upper surface 111 of the substrate 110 using the die attaching layer 170, and the bonding pad 123 is aimed in the slot 114. A plurality of electrical connection elements 150, for example, bonding wires, pass through the slots 114 to electrically connect the bonding pads 123 to the substrate 110. The sealing body 140 is formed on the upper surface 111 of the substrate 110 to seal the chip 120, and the external terminal 160 is installed on the lower surface 112 of the substrate 110.

一般には、高温によるチップ損傷を避けるため、半導体パッケージの露出表面、例えば封止体の上面に外置き型放熱板を設置するが、チップと封止体との間に熱抵抗が依然残留し、かつ製品の厚みと重さとが増加すると、熱の発散効果も限られるので、半導体パッケージの内に内蔵型放熱板を設置して放熱効果を向上させる。周知の内蔵型放熱板の設置方式は２種類があり、第一種はチップの背面に貼付されるが、内蔵型放熱板は、通常、封止体の形成前に設置され、モールド流れの圧迫に影響されることより、位置ズレが容易に起き、チップに対して内応力を生じかつ剥離問題などがある。放熱板の固定を増強させるため、他種の設置方式が利用され、それは内蔵型放熱板の周辺を接着剤や錫鉛で基板に結合させるのだが、接着剤の熱硬化後或は錫鉛のリフロー後に、封止体の上面と面一にするように放熱板の放熱表面を修正することは最早できないので、モールド樹脂は放熱板の表面に溢れ易くなり、また、放熱板とチップとの間にも封止体が流れ込んで熱抵抗の問題を生じる。   Generally, in order to avoid chip damage due to high temperature, an external heat sink is installed on the exposed surface of the semiconductor package, for example, the upper surface of the sealing body, but the thermal resistance still remains between the chip and the sealing body, As the thickness and weight of the product increase, the heat dissipation effect is also limited. Therefore, a built-in heat sink is installed in the semiconductor package to improve the heat dissipation effect. There are two types of well-known built-in heat sink installation methods. The first type is affixed to the back of the chip, but the built-in heat sink is usually installed before the sealing body is formed and compresses the mold flow. As a result, the positional deviation easily occurs, an internal stress is generated on the chip, and there is a peeling problem. In order to enhance the fixing of the heat sink, another kind of installation method is used, which is to bond the periphery of the built-in heat sink to the substrate with adhesive or tin lead, but after heat curing of the adhesive or tin lead After reflow, it is no longer possible to modify the heat radiating surface of the heat sink so that it is flush with the top surface of the sealing body, so the mold resin tends to overflow the surface of the heat sink, and between the heat sink and the chip. In addition, the sealing body flows in, causing a problem of thermal resistance.

本発明の主な目的は、一種の放熱型多穿孔半導体パッケージを提供することである。   The main object of the present invention is to provide a kind of heat radiation type multi-perforated semiconductor package.

本発明の他の目的は、内蔵型放熱板の設置による放熱板の位置ズレ、チップの内応力、封止体の熱抵抗などの問題を解決することができる一種の放熱型多穿孔半導体パッケージを提供することである。
本発明の他の目的は、モールディングプロセスにおいて封止体の上面と面一にさせるように放熱板の放熱表面を修正可能でモールド樹脂が放熱板の露出する放熱表面に溢れることを減少する一種の放熱型多穿孔半導体パッケージを提供することである。 Another object of the present invention is to provide a type of heat-dissipating multi-perforated semiconductor package that can solve problems such as positional deviation of a heat sink due to installation of a built-in heat sink, internal stress of a chip, and thermal resistance of a sealing body. Is to provide.
Another object of the present invention is a kind of modification in which the heat radiating surface of the heat radiating plate can be modified so as to be flush with the upper surface of the sealing body in the molding process, and mold resin is prevented from overflowing the heat radiating surface exposed by the heat radiating plate. A heat dissipation type multi-perforated semiconductor package is provided.

本発明の他の目的は、支持リードの端部は封止体に完全密封されることにより基板の底部に強力な剛性と固着性とを備える絶縁支持体がある一種の放熱型多穿孔半導体パッケージを提供することである。
本発明の他の目的は、内蔵型放熱板が完全にチップの背面に貼付可能で放熱効率を向上させる一種の放熱型多穿孔半導体パッケージを提供することである。
本発明の他の目的は、チップと基板との間に応力緩和効果がある一種の放熱型多穿孔半導体パッケージを提供することである。
本発明の他の目的は、チップと基板との間が剥離しないように緩和層の応力緩和効果を増加する一種の放熱型多穿孔半導体パッケージを提供することである。 Another object of the present invention is a kind of heat-dissipating multi-perforated semiconductor package having an insulating support having strong rigidity and adhesion at the bottom of the substrate by completely sealing the end of the support lead to the sealing body. Is to provide.
Another object of the present invention is to provide a kind of heat radiation type multi-perforated semiconductor package in which a built-in heat radiation plate can be completely attached to the back surface of a chip to improve heat radiation efficiency.
Another object of the present invention is to provide a kind of heat radiation type multi-perforated semiconductor package having a stress relaxation effect between a chip and a substrate.
Another object of the present invention is to provide a kind of heat radiation type multi-perforated semiconductor package that increases the stress relaxation effect of the relaxation layer so that the chip and the substrate are not separated.

上述目的を達成するため、本発明に係る放熱型多穿孔半導体パッケージは、主に基板、チップ、内蔵型放熱板及び封止体を備える。該基板は、上表面、下表面及び複数の位置決め孔を有し、該チップは該基板の上表面に設置され、該内蔵型放熱板は該チップに貼付されている。該内蔵型放熱板は複数の支持リードと放熱表面を有し、該支持リード群は該位置決め孔群に挿入され、該位置決め孔群は該支持リード群に十分に充填されないため複数のモールド流れ通路ができる。該封止体は該基板の上表面に形成されて該チップと該内蔵型放熱板を密封するが、該放熱表面を露出させ、更に該モールド流れ通路を充填することより該支持リード群を覆っている。
本発明の放熱型多穿孔半導体パッケージによると、内蔵型放熱板の支持リード群を基板の位置決め孔群に照準させ、少量接着剤のみを使用するか、あるいは接着剤を使用せずに、該内蔵型放熱板を該基板に固定することができ、更に実装完成後にチップと基板と一体結合して放熱性を増強したり、基板の反りを減らしたりする効果がある以外に、内蔵型放熱板の剥離現象を防止することもできる。 In order to achieve the above-described object, a heat radiation type multi-perforated semiconductor package according to the present invention mainly includes a substrate, a chip, a built-in heat radiation plate, and a sealing body. The substrate has an upper surface, a lower surface, and a plurality of positioning holes, the chip is disposed on the upper surface of the substrate, and the built-in heat sink is attached to the chip. The built-in heat dissipation plate has a plurality of support leads and a heat dissipation surface, the support lead group is inserted into the positioning hole group, and the positioning hole group is not sufficiently filled in the support lead group, so that a plurality of mold flow passages are provided. Can do. The sealing body is formed on the upper surface of the substrate and seals the chip and the built-in heat dissipation plate, but covers the support lead group by exposing the heat dissipation surface and filling the mold flow passage. ing.
According to the heat radiation type multi-perforated semiconductor package of the present invention, the supporting lead group of the built-in heat radiation plate is aimed at the positioning hole group of the substrate, and the built-in heat radiation plate is used without using a small amount of adhesive or without using the adhesive. The mold heat sink can be fixed to the board, and after the completion of mounting, the chip and the board are combined together to enhance heat dissipation and reduce the warpage of the board. The peeling phenomenon can also be prevented.

上述放熱型多穿孔半導体パッケージにおいて、該支持リード群は複数の端部を有し、該端部群は該基板の下表面に突出する第一高度を具し、該封止体は該基板の下表面に突出する第二高度を具し、該第二高度は該第一高度よりも高くなる。
上述放熱型多穿孔半導体パッケージにおいて、該位置決め孔群は４個の隅部貫通穴を有し、該隅部貫通穴群は該基板の４個の隅部の近くに位置している。 In the above-described heat dissipation type multi-perforated semiconductor package, the support lead group has a plurality of end portions, the end group includes a first height protruding on a lower surface of the substrate, and the sealing body is formed on the substrate. A second height projecting from the lower surface is provided, the second height being higher than the first height.
In the heat dissipation type multi-perforated semiconductor package, the positioning hole group has four corner through holes, and the corner through hole group is located near the four corners of the substrate.

上述放熱型多穿孔半導体パッケージにおいて、該位置決め孔群は少なくとも２個の側辺貫通穴を有し、該両側辺貫通穴は該基板の両反対側辺の近くに位置している。
上述放熱型多穿孔半導体パッケージにおいて、該チップは主面と背面とを有し、該主面には複数のボンディングパッドが設置され、更に複数の電気接続素子を有し、該電気接続素子群は該ボンディングパッド群を該基板に電気接続している。 In the above heat dissipation type multi-perforated semiconductor package, the positioning hole group has at least two side-side through holes, and the both-side side through-holes are located near both opposite sides of the substrate.
In the heat dissipation type multi-perforated semiconductor package, the chip has a main surface and a back surface, a plurality of bonding pads are installed on the main surface, and a plurality of electric connection elements are further included. The bonding pad group is electrically connected to the substrate.

上述放熱型多穿孔半導体パッケージにおいて、該チップの主面は該基板に向かいあってもよく、該内蔵型放熱板は該チップの背面に完全貼付されている。
上述放熱型多穿孔半導体パッケージにおいて、該基板は該電気接続素子群の通過用として更にスロットを有してもよい。
上述放熱型多穿孔半導体パッケージにおいて、該電気接続素子群は複数のボンディングワイヤを有してもよい。 In the heat dissipation type multi-perforated semiconductor package, the main surface of the chip may face the substrate, and the built-in heat dissipation plate is completely attached to the back surface of the chip.
In the above-described heat dissipation type multi-perforated semiconductor package, the substrate may further have a slot for passing through the electrical connection element group.
In the heat dissipation type multi-perforated semiconductor package, the electrical connection element group may have a plurality of bonding wires.

上述放熱型多穿孔半導体パッケージにおいて、該位置決め孔群を円形穿孔にすればよく、該支持リード群は非円形柱にしてもよい。
上述放熱型多穿孔半導体パッケージにおいて、更に該基板の下表面に設置される複数の外接端子を有してもよい。
上述放熱型多穿孔半導体パッケージにおいて、該外接端子群は複数のはんだボールを有してもよい。 In the above-described heat radiation type multi-perforated semiconductor package, the positioning hole group may be a circular perforation, and the support lead group may be a non-circular column.
The above-described heat radiation type multi-perforated semiconductor package may further include a plurality of external terminals installed on the lower surface of the substrate.
In the above heat dissipation type multi-perforated semiconductor package, the external terminal group may have a plurality of solder balls.

上述放熱型多穿孔半導体パッケージにおいて、該外接端子群の設置高さは該第一高度よりも高くなる。
上述放熱型多穿孔半導体パッケージにおいて、更に該チップと該基板との間に形成される緩和層を有してもよい。
上述放熱型多穿孔半導体パッケージにおいて、該緩和層を低粘着性弾性体にしてもよい。
上述放熱型多穿孔半導体パッケージにおいて、更に該チップと該内蔵型放熱板との間に形成される接着層を有してもよい。
上述放熱型多穿孔半導体パッケージにおいて、該緩和層は該接着層よりも粘着強度が小さくなってもよい。 In the heat radiation type multi-perforated semiconductor package, the installation height of the external terminal group is higher than the first height.
The heat dissipation type multi-perforated semiconductor package may further include a relaxation layer formed between the chip and the substrate.
In the above heat dissipation type multi-perforated semiconductor package, the relaxation layer may be a low-adhesive elastic body.
The above-mentioned heat radiation type multi-perforated semiconductor package may further include an adhesive layer formed between the chip and the built-in heat radiation plate.
In the above heat dissipation type multi-perforated semiconductor package, the relaxation layer may have a lower adhesive strength than the adhesive layer.

（第１実施形態）
図２は、本発明の第１実施形態による放熱型多穿孔半導体パッケージを示す。放熱型多穿孔半導体パッケージ２００は主に、基板２１０、チップ２２０、内蔵型放熱板２３０及び封止体２４０を備える。基板２１０は上表面２１１、下表面２１２及び複数の位置決め孔２１３を有し、位置決め孔２１３群は上表面２１１と下表面２１２とを貫通している。本実施形態において、位置決め孔２１３群は基板２１０の４箇所の隅部（図３参照）の近くに位置する４個の隅部貫通穴を有することができる。基板２１０は更にスロット２１４を有し、スロット２１４は基板２１０のセンターラインに位置し、かつ基板２１０を貫通して後続の電気接続作業中に複数の電気接続素子２５０の通過用として利用される。 (First embodiment)
FIG. 2 shows a heat radiation type multi-perforated semiconductor package according to the first embodiment of the present invention. The heat radiation type multi-perforated semiconductor package 200 mainly includes a substrate 210, a chip 220, a built-in heat radiation plate 230, and a sealing body 240. The substrate 210 has an upper surface 211, a lower surface 212, and a plurality of positioning holes 213, and the positioning hole 213 group penetrates the upper surface 211 and the lower surface 212. In this embodiment, the positioning hole 213 group can have four corner through holes located near the four corners (see FIG. 3) of the substrate 210. The substrate 210 further has a slot 214, which is located at the center line of the substrate 210 and is used to pass through the plurality of electrical connection elements 250 through the substrate 210 during subsequent electrical connection operations.

チップ２２０は基板２１０の上表面２１１に設置され、図３に示すように、チップ２２０の設置後にスロット２１４の両端は、封止体２４０の熱硬化前封止材の流入用としてチップ２２０から露出する。再び図２に示すように、チップ２２０は主面２２１と背面２２２を有し、主面２２１は基板２１０に向かって複数のボンディングパッド２２３を設置している。ボンディングパッド２２３群はスロット２１４の内に照準し（図４参照）、更に電気接続素子２５０群はスロット２１４を通過しボンディングパッド２２３群を基板２１０のフィンガーに電気接続している。電気接続素子２５０群はワイヤボンディング方式で形成された複数のボンディングワイヤを有することができる。具体的に言えば、放熱型多穿孔半導体パッケージ２００は更に緩和層２７０を有し、緩和層２７０は、チップ２２０と基板２１０との間の応力緩和効果を提供するため、チップ２２０と基板２１０との間に形成される。本実施形態において、緩和層２７０は低粘着性弾性体にすればよく、それを利用してダイアッタチング層の使用の必要性がなくなってチップ２２０と基板２１０とを直接貼付することができるので製造コストの低減になる。   The chip 220 is installed on the upper surface 211 of the substrate 210. As shown in FIG. 3, both ends of the slot 214 are exposed from the chip 220 for inflow of the sealing material before thermosetting of the sealing body 240 after the chip 220 is installed. To do. As shown in FIG. 2 again, the chip 220 has a main surface 221 and a back surface 222, and the main surface 221 is provided with a plurality of bonding pads 223 toward the substrate 210. The bonding pads 223 are aimed in the slots 214 (see FIG. 4), and the electrical connection elements 250 pass through the slots 214 to electrically connect the bonding pads 223 to the fingers of the substrate 210. The electrical connection element 250 group can have a plurality of bonding wires formed by a wire bonding method. Specifically, the heat dissipation type multi-perforated semiconductor package 200 further includes a relaxation layer 270, which provides a stress relaxation effect between the chip 220 and the substrate 210. Formed between. In the present embodiment, the relaxation layer 270 may be a low-adhesive elastic body, which eliminates the need for the use of a detaching layer and allows the chip 220 and the substrate 210 to be directly attached. Manufacturing cost is reduced.

図２及び図４に示すように、内蔵型放熱板２３０はチップ２２０の背面２２２に貼着されて複数の支持リード２３１と放熱表面２３２とを有する。支持リード２３１群は位置決め孔２１３群に挿入されることにより、接着剤の使用の必要がなく内蔵型放熱板２３０は精確に基板２１０の上に固定されることができ、かつ位置決め孔２１３群は支持リード２３１群に十分に充填されないため複数のモールド流れ通路２４１ができる。例えば、位置決め孔２１３群を円形穿孔にしてもよく、支持リード２３１群は非円形柱にしてもよい。支持リード２３１群のピン数を位置決め孔２１３群の孔数と一致させてもよく、また、モールド流れ通路２４１群を介して封止体２４０の熱硬化前封止材が流入することにより、支持リード２３１群は封止体２４０に覆われて内蔵型放熱板２３０の安定性を改善することができる。再び図２に示すように、内蔵型放熱板２３０はチップ２２０の背面２２２に完全貼着されれば好ましく、それにより、内蔵型放熱板２３０とチップ２２０との間の隙間の封止体２４０の充填を避けて放熱効率を増加している。言い換えれば、内蔵型放熱板２３０はチップ２２０の背面２２２に平坦貼着されるとチップ２２０に良好な支持性を提供したり、チップ２２０の機械的強度を増大させたりすることができるので、チップ２２０が内応力の影響によって配線断裂にならないように確保している。故に、放熱型多穿孔半導体パッケージ２００にとって、厚みの薄いチップ２２０を使用することはパッケージの厚さを減少させ、チップ破裂問題を避けることができる。本実施形態において、放熱型多穿孔半導体パッケージ２００は更に接着層２８０を有し、接着層２８０は、チップ２２０と内蔵型放熱板２３０との間の粘着力の増強用としてチップ２２０と内蔵型放熱板２３０との間に形成されている。なお、緩和層２７０は、チップ内部応力の緩和に役立つとともに、チップ２２０と基板２１０との間の熱膨張係数が合わないことにより起こる問題を改善することが可能となる。緩和層２７０は接着層２８０よりも粘着強度が小さくなると好ましく、よって、緩和層２７０の応力緩和効果が増加され、チップ２２０と内蔵型放熱板２３０との剥離が発生しなくなる。   As shown in FIGS. 2 and 4, the built-in heat dissipation plate 230 is attached to the back surface 222 of the chip 220 and has a plurality of support leads 231 and a heat dissipation surface 232. By inserting the support leads 231 into the positioning holes 213, the built-in heat sink 230 can be accurately fixed on the substrate 210 without using an adhesive, and the positioning holes 213 are Since the support lead 231 group is not sufficiently filled, a plurality of mold flow passages 241 are formed. For example, the positioning holes 213 may be circular holes, and the support leads 231 may be non-circular columns. The number of pins of the support lead 231 group may be made to coincide with the number of holes of the positioning hole 213 group, and the sealing material 240 before thermosetting of the sealing body 240 flows through the mold flow passage 241 group, thereby supporting the support lead 231 group. The leads 231 can be covered with the sealing body 240 to improve the stability of the built-in heat sink 230. As shown in FIG. 2 again, it is preferable that the built-in type heat sink 230 is completely attached to the back surface 222 of the chip 220, and thereby the sealing body 240 of the gap between the built-in type heat sink 230 and the chip 220 is formed. The heat dissipation efficiency is increased by avoiding filling. In other words, the built-in heat sink 230 can provide good support to the chip 220 or increase the mechanical strength of the chip 220 when it is flatly attached to the back surface 222 of the chip 220. It is ensured that 220 does not break the wiring due to the influence of internal stress. Therefore, for the heat-dissipating multi-perforated semiconductor package 200, using a thin chip 220 can reduce the thickness of the package and avoid the chip burst problem. In the present embodiment, the heat radiation type multi-perforated semiconductor package 200 further includes an adhesive layer 280, and the adhesive layer 280 is used to enhance the adhesive force between the chip 220 and the built-in heat dissipation plate 230, and the chip 220 and the built-in heat dissipation. It is formed between the plate 230. The relaxing layer 270 helps to alleviate the internal stress of the chip, and can improve the problem caused by the thermal expansion coefficient between the chip 220 and the substrate 210 not matching. The relaxation layer 270 preferably has a lower adhesive strength than the adhesive layer 280. Therefore, the stress relaxation effect of the relaxation layer 270 is increased, and the chip 220 and the built-in heat sink 230 do not peel off.

図２に示すように、封止体２４０は基板２１０の上表面２１１に形成されてチップ２２０と内蔵型放熱板２３０とを密封するが、放熱表面２３２を露出させることにより有効に放熱することができる。なお、モールド流れ通路２４１群は更に封止体２４０に充填されて支持リード２３１群を覆うことにより、内蔵型放熱板２３０と基板２１０との固定性を増強して基板２１０の反り現象を防止している。図２及び図５に示すように、支持リード２３１群は複数の端部２３３を有し、端部２３３群は基板２１０の下表面２１２に突出する第一高度Ｈ１を具し、そして、封止体２４０も基板２１０の下表面２１２に突出する第二高度Ｈ２を具し、ここで、第二高度Ｈ２は第一高度Ｈ１よりも高くなるので、支持リード２３１群の端部２３３は封止体２４０に完全密封されることができ、強力な剛性と固着性を具する複合式絶縁支持体を形成し、かつ内蔵型放熱板２３０と封止体２４０との結合不良による剥離問題を避けることもできる。本実施形態において、放熱型多穿孔半導体パッケージ２００は更に複数の外接端子２６０、例えばはんだボールを有し、外接端子２６０群は基板２１０の下表面２１２に設置され、設置の高さは第二高度Ｈ２よりも高くなり、即ち、上述複合式絶縁支持体は基板２１０の下表面２１２に突出する高さとなる。   As shown in FIG. 2, the sealing body 240 is formed on the upper surface 211 of the substrate 210 and seals the chip 220 and the built-in heat dissipation plate 230, but can effectively dissipate heat by exposing the heat dissipation surface 232. it can. The mold flow passages 241 are further filled in the sealing body 240 to cover the support leads 231, thereby enhancing the fixing property between the built-in heat sink 230 and the substrate 210 and preventing the warp phenomenon of the substrate 210. ing. As shown in FIGS. 2 and 5, the group of support leads 231 has a plurality of ends 233, the ends 233 having a first height H1 protruding from the lower surface 212 of the substrate 210, and sealing. The body 240 also has a second height H2 protruding from the lower surface 212 of the substrate 210, where the second height H2 is higher than the first height H1, so that the end portion 233 of the support lead 231 group is sealed. 240 can be completely sealed, forming a composite insulating support having strong rigidity and adhesion, and avoiding a peeling problem due to poor connection between the built-in heat sink 230 and the sealing body 240 it can. In the present embodiment, the heat radiation type multi-perforated semiconductor package 200 further includes a plurality of external terminals 260, for example, solder balls. The external terminals 260 are installed on the lower surface 212 of the substrate 210, and the installation height is the second height. It becomes higher than H2, that is, the above-described composite insulating support has a height protruding from the lower surface 212 of the substrate 210.

上述のように、チップ２２０が運算中に出した熱は内蔵型放熱板２３０を介して外部へ迅速に発散され、かつ実装作業中、少量接着剤のみを使用するか、あるいは接着剤を使用せずに内蔵型放熱板２３０の支持リード２３１が固定されることにより、内蔵型放熱板２３０の位置決めを行うことができる。このような内蔵型放熱板２３０はモールド流れの圧迫を受けても水平方向のズレを発生しなく、実装後に支持リード２３１群は封止体２４０と基板２１０と一体結合されて内蔵型放熱板２３０の剥離及び基板２１０の反りなどの問題を防止することが可能となる。以上説明したように、本発実施形態によれば、内蔵型放熱板２３０は、有効な放熱手段の提供ができるだけではなく全体構造に良好な安定性を維持することも可能となり、更にチップ２２０を保護してチップ破裂が避けられる。従って、放熱型多穿孔半導体パッケージ２００は、周知の設置方式による内蔵型放熱板のズレ、チップの内応力及び封止体熱抵抗などの問題を解決することができるようになる。   As described above, the heat generated during the operation of the chip 220 is quickly dissipated to the outside through the built-in heat sink 230, and only a small amount of adhesive is used during the mounting operation, or an adhesive is used. Without fixing the support lead 231 of the built-in heat sink 230, the built-in heat sink 230 can be positioned. Such a built-in type heat sink 230 does not generate a horizontal shift even if it is subjected to compression of the mold flow. After mounting, the support leads 231 are integrally coupled with the sealing body 240 and the substrate 210 so that the built-in type heat sink 230 Problems such as peeling of the substrate and warping of the substrate 210 can be prevented. As described above, according to the present embodiment, the built-in heat dissipation plate 230 can not only provide effective heat dissipation means but also maintain good stability in the entire structure. Protect and avoid chip rupture. Therefore, the heat radiation type multi-perforated semiconductor package 200 can solve the problems such as the displacement of the built-in heat radiation plate, the internal stress of the chip, and the thermal resistance of the sealing body by a known installation method.

図３Ａから図３Ｃを参照しながら上述放熱型多穿孔半導体パッケージの形成方法を説明する。先ず、図２及び図３Ａに示すように、上述の基板２１０を提供し、基板２１０は上表面２１１、下表面２１２及び複数の位置決め孔２１３を有し、更にスロット２１４を有することができる。位置決め孔２１３群とスロット２１４とは上表面２１１と下表面２１２とを貫通している。また、図３Ｂに示すように、基板２１０の上表面２１１に上述のチップ２２０を設置し、図４に示すように、複数のボンディングパッド２２３はチップ２２０の主面２２１に設置され、スロット２１４により露出されて複数の電気接続素子２５０を介し基板２１０に電気接続される。また、再び図２及び図３Ｂに示すように、上述の内蔵型放熱板２３０をチップ２２０の背面２２２に貼付し、内蔵型放熱板２３０は複数の支持リード２３１と放熱表面２３２とを有する。支持リード２３１群は位置決め孔２１３群に挿入され、ここで、位置決め孔２１３群は支持リード２３１群に十分に充填されないため複数のモールド流れ通路２４１ができる。最後に、図２及び図３Ｃに示すように、基板２１０の上表面２１１に上述の封止体２４０を形成してチップ２２０と内蔵型放熱板２３０とを密封するが、放熱表面２３２は露出させる。なお、封止体２４０は更にモールド流れ通路２４１群を充填して支持リード２３１群を覆っている。故に、上述の作業において、内蔵型放熱板２３０は、少量接着剤のみを使用するか、或は接着剤を使用せずに基板２１０に水平方向に位置決めされることができ、作業過程の短縮が可能になって製造にかかる時間の減少或は製造コストの節約を実現している。しかしながら、モールディング方式で封止体２４０を形成する過程において、内蔵型放熱板２３０は垂直方向の微調整として移動して上金型のモールド穴の壁に密着されている。そして、封止体２４０の形成後に、封止体２４０の上面と面一にさせるように内蔵型放熱板２３０の放熱表面２３２は修正されるので、モールド樹脂が内蔵型放熱板２３０の放熱表面２３２に溢れる現象が低減され実質的及び明らかな効果がある。本実施形態において、チップ２２０は緩和層２７０に固定される必要がないため、内蔵型放熱板２３０は垂直方向の微調整で移動すると同時に、垂直方向にチップ２２０を移動している。   A method of forming the heat dissipation type multi-perforated semiconductor package will be described with reference to FIGS. 3A to 3C. First, as shown in FIGS. 2 and 3A, the above-described substrate 210 is provided. The substrate 210 has an upper surface 211, a lower surface 212, a plurality of positioning holes 213, and can further have a slot 214. The positioning holes 213 and the slots 214 pass through the upper surface 211 and the lower surface 212. 3B, the above-described chip 220 is installed on the upper surface 211 of the substrate 210. As shown in FIG. 4, a plurality of bonding pads 223 are installed on the main surface 221 of the chip 220. It is exposed and electrically connected to the substrate 210 via the plurality of electrical connection elements 250. As shown in FIGS. 2 and 3B again, the built-in heat sink 230 is attached to the back surface 222 of the chip 220, and the built-in heat sink 230 has a plurality of support leads 231 and a heat radiation surface 232. The support lead 231 group is inserted into the positioning hole 213 group. Here, since the positioning hole 213 group is not sufficiently filled in the support lead 231 group, a plurality of mold flow passages 241 are formed. Finally, as shown in FIGS. 2 and 3C, the sealing body 240 is formed on the upper surface 211 of the substrate 210 to seal the chip 220 and the built-in heat dissipation plate 230, but the heat dissipation surface 232 is exposed. . The sealing body 240 further fills the group of mold flow passages 241 and covers the group of support leads 231. Therefore, in the above-described operation, the built-in heat sink 230 can be positioned in the horizontal direction on the substrate 210 using only a small amount of adhesive or without using an adhesive, thereby shortening the work process. This has made it possible to reduce manufacturing time or save manufacturing costs. However, in the process of forming the sealing body 240 by the molding method, the built-in heat radiating plate 230 moves as fine adjustment in the vertical direction and is in close contact with the wall of the mold hole of the upper mold. Then, after the sealing body 240 is formed, the heat radiation surface 232 of the built-in heat sink 230 is modified so as to be flush with the upper surface of the seal body 240, so that the mold resin is the heat radiation surface 232 of the built-in heat sink 230. Phenomenon overflowing is reduced, and there is a substantial and obvious effect. In this embodiment, since the chip 220 does not need to be fixed to the relaxing layer 270, the built-in heat sink 230 moves with the fine adjustment in the vertical direction and simultaneously moves the chip 220 in the vertical direction.

（第２実施形態）
図６は、本発明の第２実施形態によれる放熱型多穿孔半導体パッケージを示す。放熱型多穿孔半導体パッケージ３００は主要に基板３１０、チップ３２０、内蔵型放熱板３３０及び封止体３４０を有する。基板３１０は上表面３１１、下表面３１２及び複数の位置決め孔３１３を有し、上表面３１１にチップ３２０が設置され、下表面３１２に複数の外接端子３６０、例えばはんだボールが設置され、放熱型多穿孔半導体パッケージ３００は外接端子３６０を介し外部印刷基板（図面に示せず）と接続している。位置決め孔３１３群は４個の隅部貫通穴を有し、該隅部貫通穴群は該基板の４個の隅部の近くに位置している。また、図７に示すように、本実施形態において、位置決め孔３１３群は少なくとも２個の側辺貫通穴を有し、該両側辺貫通穴は該基板の両反対側辺の近くに位置している。また、図８に示すように、チップ３２０は基板３１０の上表面３１１に設置されている。なお、図９に示すように、チップ３２０は複数のボンディングパッド３２３を有し、ボンディングパッド３２３群は基板３１０のスロット３１４の内に照準し、更に電気接続素子３５０群はスロット３１４を通過してボンディングパッド３２３群を基板３１０に電気接続する。 (Second Embodiment)
FIG. 6 shows a heat dissipation type multi-perforated semiconductor package according to a second embodiment of the present invention. The heat radiation type multi-perforated semiconductor package 300 mainly includes a substrate 310, a chip 320, a built-in heat radiation plate 330 and a sealing body 340. The substrate 310 has an upper surface 311, a lower surface 312, and a plurality of positioning holes 313, the chip 320 is installed on the upper surface 311, and a plurality of external terminals 360, for example, solder balls, are installed on the lower surface 312. The perforated semiconductor package 300 is connected to an external printed circuit board (not shown in the drawing) via the external terminals 360. The positioning hole 313 group has four corner through holes, and the corner through hole group is located near the four corners of the substrate. In addition, as shown in FIG. 7, in this embodiment, the positioning hole 313 group has at least two side through holes, and the both side through holes are located near both opposite sides of the substrate. Yes. Further, as shown in FIG. 8, the chip 320 is disposed on the upper surface 311 of the substrate 310. As shown in FIG. 9, the chip 320 has a plurality of bonding pads 323, the bonding pad 323 group is aimed in the slot 314 of the substrate 310, and the electrical connection element 350 group passes through the slot 314. The bonding pad 323 group is electrically connected to the substrate 310.

再び図６及び図８を参照すると、内蔵型放熱板３３０はチップ３２０に貼付されかつ複数の支持リード３３１と放熱表面３３２とを有する。支持リード３３１群は位置決め孔３１３群に挿入され、位置決め孔３１３群は支持リード３３１群に十分に充填されないため複数のモールド流れ通路３４１ができる。封止体３４０は基板３１０の上表面３１１に形成されてチップ３２０と内蔵型放熱板３３０とを密封するが、放熱表面３３２を露出させ、更にモールド流れ通路３４１を充填することより支持リード３３１群を覆っている。図６に示すように、支持リード３３１群は複数の端部３３３を有し、端部３３３群は基板３１０の下表面３１２に突出し、かつ封止体３４０も基板３１０の下表面３１２に突出して支持リード３３１群の端部３３３を完全密封し、それにより、基板３１０に強力な剛性と固着性を具する複合式絶縁支持体を形成してから内蔵型放熱板３３０、チップ３２０及び基板３１０は一体結合されるようにでき剥離問題が起きなくなる。
以上、本発明をその好適な実施形態に基づいて説明したが、本発明の保護範囲は特許請求の範囲の記載に基づいて定められ、この保護範囲を基準にして、本発明の精神と範囲内に触れるどんな変更や修正も本発明の保護範囲に属する。 Referring to FIGS. 6 and 8 again, the built-in heat dissipation plate 330 is attached to the chip 320 and has a plurality of support leads 331 and a heat dissipation surface 332. The support lead 331 group is inserted into the positioning hole 313 group. Since the positioning hole 313 group is not sufficiently filled in the support lead 331 group, a plurality of mold flow passages 341 are formed. The sealing body 340 is formed on the upper surface 311 of the substrate 310 to seal the chip 320 and the built-in heat dissipation plate 330, but exposes the heat dissipation surface 332 and further fills the mold flow passage 341 to support the group of support leads 331. Covering. As shown in FIG. 6, the support lead 331 group has a plurality of end portions 333, the end portion 333 group protrudes on the lower surface 312 of the substrate 310, and the sealing body 340 also protrudes on the lower surface 312 of the substrate 310. The end 333 of the support lead 331 group is completely sealed, thereby forming a composite insulating support having strong rigidity and adhesion to the substrate 310, and then the built-in heat sink 330, the chip 320, and the substrate 310 are It can be joined together so that the peeling problem does not occur.
Although the present invention has been described based on the preferred embodiments thereof, the protection scope of the present invention is determined based on the description of the scope of claims, and within the spirit and scope of the present invention based on this protection scope. Any changes or modifications touching the above are within the protection scope of the present invention.

従来の半導体パッケージを示す断面図である。It is sectional drawing which shows the conventional semiconductor package. 本発明の第一実施形態による放熱型多穿孔半導体パッケージを示す断面図である。1 is a cross-sectional view showing a heat dissipation type multi-perforated semiconductor package according to a first embodiment of the present invention. 本発明の第一実施形態による放熱型多穿孔半導体パッケージにおいて、製造作業中の基板の上表面を示す模式図である。FIG. 3 is a schematic diagram showing an upper surface of a substrate during a manufacturing operation in the heat dissipation type multi-perforated semiconductor package according to the first embodiment of the present invention. 本発明の第一実施形態による放熱型多穿孔半導体パッケージにおいて、製造作業中の基板の上表面を示す模式図である。FIG. 3 is a schematic diagram showing an upper surface of a substrate during a manufacturing operation in the heat dissipation type multi-perforated semiconductor package according to the first embodiment of the present invention. 本発明の第一実施形態による放熱型多穿孔半導体パッケージにおいて、製造作業中の基板の上表面を示す模式図である。FIG. 3 is a schematic diagram showing an upper surface of a substrate during a manufacturing operation in the heat dissipation type multi-perforated semiconductor package according to the first embodiment of the present invention. 本発明の第一実施形態による放熱型多穿孔半導体パッケージにおいて、封止作業前の基板の下表面を示す模式図である。FIG. 3 is a schematic diagram showing a lower surface of a substrate before a sealing operation in the heat dissipation type multi-perforated semiconductor package according to the first embodiment of the present invention. 本発明の第一実施形態による放熱型多穿孔半導体パッケージの位置決め孔を示す断面図である。It is sectional drawing which shows the positioning hole of the thermal radiation type | mold multi-perforated semiconductor package by 1st embodiment of this invention. 本発明の第二実施形態による放熱型多穿孔半導体パッケージの位置決め孔を示す断面図である。It is sectional drawing which shows the positioning hole of the thermal radiation type | mold multi-perforated semiconductor package by 2nd embodiment of this invention. 本発明の第二実施形態による放熱型多穿孔半導体パッケージの基板の上表面を示す模式図である。It is a schematic diagram which shows the upper surface of the board | substrate of the thermal radiation type perforated semiconductor package by 2nd embodiment of this invention. 本発明の第二実施形態による放熱型多穿孔半導体パッケージの封止作業前の基板の上表面を示す模式図である。It is a schematic diagram which shows the upper surface of the board | substrate before the sealing operation | work of the thermal radiation type perforated semiconductor package by 2nd embodiment of this invention. 本発明の第二実施形態による放熱型多穿孔半導体パッケージの封止作業前の基板の下表面を示す模式図である。It is a schematic diagram which shows the lower surface of the board | substrate before the sealing operation | work of the thermal radiation type perforated semiconductor package by 2nd embodiment of this invention.

符号の説明Explanation of symbols

２００：放熱型多穿孔半導体パッケージ、２１０：基板、２１１：上表面、２１２：下表面、２１３：位置決め孔、２１４：スロット、２２０：チップ、２２１：主面、２２２：背面、２２３：ボンディングパッド、２３０：内蔵型放熱板、２３１：支持リード、２３２：放熱表面、２３３：端部、２４０：封止体、２４１：モールド流れ通路、２５０：電気接続素子、２６０：基板、２７０：緩和層、２８０：接着層、３００：放熱型多穿孔半導体パッケージ、３１０：基板、３１１：上表面、３１２：下表面、３１３：位置決め孔、３１４：スロット、３２０：チップ、３２３：ボンディングパッド、３３０：内蔵型放熱板、３３１：支持リード、３３２：放熱表面、３３３：端部、３４０：封止体、３４１：モールド流れ通路、３５０：電気接続素子、３６０：外接端子、Ｈ１：第一高度、Ｈ２：第二高度   200: heat dissipation type multi-perforated semiconductor package, 210: substrate, 211: upper surface, 212: lower surface, 213: positioning hole, 214: slot, 220: chip, 221: main surface, 222: back surface, 223: bonding pad, 230: Built-in heat dissipation plate, 231: Support lead, 232: Heat dissipation surface, 233: End, 240: Sealed body, 241: Mold flow passage, 250: Electrical connection element, 260: Substrate, 270: Relaxation layer, 280 : Adhesive layer, 300: Heat radiation type multi-perforated semiconductor package, 310: Substrate, 311: Upper surface, 312: Lower surface, 313: Positioning hole, 314: Slot, 320: Chip, 323: Bonding pad, 330: Built-in heat dissipation Plate, 331: support lead, 332: heat dissipation surface, 333: end, 340: sealing body, 341: mold flow path, 350 Electrical connection device, 360: circumscribed terminal, H1: first altitude, H2: second altitude

Claims (16)

上表面、下表面及び複数の位置決め孔を有する基板と、
前記基板の上表面に設置されるチップと、
前記チップに貼付されかつ複数の支持リードと放熱表面とを有し、前記支持リード群は前記位置決め孔群に挿入され、かつ前記位置決め孔群は前記支持リード群に十分に充填されないため複数のモールド流れ通路ができる内蔵型放熱板と、
前記基板の前記上表面に形成されて、前記チップと前記内蔵型放熱板とを密封するとともに、前記放熱表面を露出し、かつ更に前記モールド流れ通路に充填されて前記支持リード群を覆う封止体と、
を備えることを特徴とする放熱型多穿孔半導体パッケージ。 A substrate having an upper surface, a lower surface and a plurality of positioning holes;
A chip installed on the upper surface of the substrate;
A plurality of molds are attached to the chip and have a plurality of support leads and a heat radiating surface, the support lead group is inserted into the positioning hole group, and the positioning hole group is not sufficiently filled in the support lead group. A built-in heat sink with a flow path;
A seal formed on the upper surface of the substrate for sealing the chip and the built-in heat dissipation plate, exposing the heat dissipation surface, and further filling the mold flow passage to cover the support lead group Body,
A heat dissipation type multi-perforated semiconductor package comprising: 前記支持リード群は複数の端部を有し、前記端部群は前記基板の前記下表面に突出する第一高度を有し、前記封止体も前記基板の前記下表面に突出する第二高度を有し、前記第二高度は前記第一高度よりも高くなることを特徴とする請求項１に記載の放熱型多穿孔半導体パッケージ。   The support lead group has a plurality of end portions, the end group has a first height protruding on the lower surface of the substrate, and the sealing body also protrudes on the lower surface of the substrate. 2. The heat dissipation type multi-perforated semiconductor package according to claim 1, wherein the second height is higher than the first height. 前記位置決め孔群は４個の隅部貫通穴を有し、前記隅部貫通穴群は前記基板の４個の隅部の近くに位置することを特徴とする請求項１に記載の放熱型多穿孔半導体パッケージ。   2. The heat radiation type multi-hole according to claim 1, wherein the positioning hole group has four corner through holes, and the corner through hole group is located near the four corners of the substrate. Perforated semiconductor package. 前記位置決め孔群は少なくとも２個の側辺貫通穴を有し、前記両側辺貫通穴は前記基板の両反対側辺に近く位置することを特徴とする請求項１または３に記載の放熱型多穿孔半導体パッケージ。   4. The heat radiation type multi-hole according to claim 1, wherein the positioning hole group has at least two side-side through holes, and the both-side side through-holes are located close to both opposite sides of the substrate. Perforated semiconductor package. 前記チップは主面と背面とを有し、前記主面には複数のボンディングパッドが設置され、更に複数の電気接続素子を有し、前記電気接続素子群は前記ボンディングパッド群を前記基板に電気接続することを特徴とする請求項１に記載の放熱型多穿孔半導体パッケージ。   The chip has a main surface and a back surface, a plurality of bonding pads are provided on the main surface, and further includes a plurality of electrical connection elements, and the electrical connection element group electrically connects the bonding pad group to the substrate. The heat radiation type multi-perforated semiconductor package according to claim 1, wherein the heat radiation type multi-hole semiconductor package is connected. 前記チップの主面は前記基板に向かい、前記内蔵型放熱板は前記チップの背面に完全貼付されることを特徴とする請求項５に記載の放熱型多穿孔半導体パッケージ。   6. The heat radiation type multi-perforated semiconductor package according to claim 5, wherein a main surface of the chip faces the substrate, and the built-in heat dissipation plate is completely attached to the back surface of the chip. 前記基板は前記電気接続素子群の通過用として更にスロットを有することを特徴とする請求項６に記載の放熱型多穿孔半導体パッケージ。   7. The heat radiation type multi-perforated semiconductor package according to claim 6, wherein the substrate further has a slot for passing through the electrical connection element group. 前記電気接続素子群は複数のボンディングワイヤを有することを特徴とする請求項５に記載の放熱型多穿孔半導体パッケージ。   6. The heat dissipation type multi-perforated semiconductor package according to claim 5, wherein the electrical connection element group includes a plurality of bonding wires. 前記位置決め孔群を円形穿孔にし、前記支持リード群は非円形柱にすることを特徴とする請求項１に記載の放熱型多穿孔半導体パッケージ。   2. The heat radiation type multi-perforated semiconductor package according to claim 1, wherein the positioning hole group is a circular perforation, and the support lead group is a non-circular column. 更に前記基板の前記下表面に設置される複数の外接端子を有することを特徴とする請求項１または２に記載の放熱型多穿孔半導体パッケージ。   The heat radiation type multi-perforated semiconductor package according to claim 1, further comprising a plurality of external terminals installed on the lower surface of the substrate. 前記外接端子群は複数のはんだボールを有することを特徴とする請求項１０に記載の放熱型多穿孔半導体パッケージ。   The heat dissipation type multi-perforated semiconductor package according to claim 10, wherein the external terminal group includes a plurality of solder balls. 前記外接端子群の設置高さは前記第一高度よりも高くなることを特徴とする請求項１０に記載の放熱型多穿孔半導体パッケージ。   The heat radiation type multi-perforated semiconductor package according to claim 10, wherein the installation height of the circumscribed terminal group is higher than the first altitude. 更に前記チップと前記基板との間に形成される緩和層を有することを特徴とする請求項１に記載の放熱型多穿孔半導体パッケージ。   2. The heat dissipation type multi-perforated semiconductor package according to claim 1, further comprising a relaxation layer formed between the chip and the substrate. 前記緩和層を低粘着性弾性体にすることを特徴とする請求項１３に記載の放熱型多穿孔半導体パッケージ。   The heat dissipation type multi-perforated semiconductor package according to claim 13, wherein the relaxation layer is made of a low-adhesive elastic body. 更に前記チップと前記内蔵型放熱板との間に形成される接着層を有することを特徴とする請求項１３に記載の放熱型多穿孔半導体パッケージ。   14. The heat radiation type multi-perforated semiconductor package according to claim 13, further comprising an adhesive layer formed between the chip and the built-in heat radiation plate. 前記緩和層は前記接着層よりも粘着強度が小さいことを特徴とする請求項１５に記載の放熱型多穿孔半導体パッケージ。   The heat dissipation type multi-perforated semiconductor package according to claim 15, wherein the relaxation layer has a lower adhesive strength than the adhesive layer.
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2014034411A1 (en) * 2012-08-27 2014-03-06 三菱電機株式会社 Electric power semiconductor device
JP2014528652A (en) * 2011-10-03 2014-10-27 インヴェンサス・コーポレイション Stub minimization by offsetting the terminal grid from the center of the package
EP3182449A1 (en) * 2015-12-17 2017-06-21 MediaTek Inc. Semiconductor package

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006245599A (en) * 2006-04-12 2006-09-14 Oki Electric Ind Co Ltd Electronic component and semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006245599A (en) * 2006-04-12 2006-09-14 Oki Electric Ind Co Ltd Electronic component and semiconductor device

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014528652A (en) * 2011-10-03 2014-10-27 インヴェンサス・コーポレイション Stub minimization by offsetting the terminal grid from the center of the package
WO2014034411A1 (en) * 2012-08-27 2014-03-06 三菱電機株式会社 Electric power semiconductor device
KR101614669B1 (en) 2012-08-27 2016-04-21 미쓰비시덴키 가부시키가이샤 Electric power semiconductor device
JPWO2014034411A1 (en) * 2012-08-27 2016-08-08 三菱電機株式会社 Power semiconductor device
US9433075B2 (en) 2012-08-27 2016-08-30 Mitsubishi Electric Corporation Electric power semiconductor device
EP3182449A1 (en) * 2015-12-17 2017-06-21 MediaTek Inc. Semiconductor package
CN107039390A (en) * 2015-12-17 2017-08-11 联发科技股份有限公司 Semiconductor packages
US10008441B2 (en) 2015-12-17 2018-06-26 Mediatek Inc. Semiconductor package

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