JP2009021366A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
JP2009021366A
JP2009021366A JP2007182499A JP2007182499A JP2009021366A JP 2009021366 A JP2009021366 A JP 2009021366A JP 2007182499 A JP2007182499 A JP 2007182499A JP 2007182499 A JP2007182499 A JP 2007182499A JP 2009021366 A JP2009021366 A JP 2009021366A
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electrode pad
semiconductor chip
wiring board
insulating film
electrode pads
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Yoshinori Miyaki
美典 宮木
Narihisa Sato
斉尚 佐藤
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Renesas Technology Corp
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Renesas Technology Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

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  • Wire Bonding (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To obtain a semiconductor package capable of improving heat radiation while securing mounting reliability. <P>SOLUTION: A semiconductor chip 16 is mounted on a principal surface of a wiring board 11. On the reverse surface of the wiring board 11, a plurality of first electrode pads 21 are disposed in a region inside the semiconductor chip 16 in plan view. On the reverse surface of the wiring board 11, a plurality of second electrode pads 22 are disposed outside the semiconductor chip 16 in plan view. The first and second electrode pads 21 and 22 are exposed in first and second opening portions 28 and 29 provided in the insulating film 23. Then peripheral edges of the first electrode pads 21 are covered with the insulating film 23, and external shapes of the second electrode pads 22 are smaller than the second opening portion 29. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

本発明は、ＢＧＡ（Ball Grid Array）タイプの半導体パッケージ（半導体装置）に関し、特に実装信頼性を確保しながら放熱性を向上することができる半導体パッケージに関するものである。   The present invention relates to a BGA (Ball Grid Array) type semiconductor package (semiconductor device), and more particularly to a semiconductor package capable of improving heat dissipation while ensuring mounting reliability.

ＢＧＡタイプの半導体パッケージは配線基板の一面に電極パッドが設けられ、この電極パッドに半田ボールが接合される。そして、この半田ボールを介して半導体パッケージ（半導体装置）は実装基板に実装される。このような半導体パッケージの電極パッド構造としてＳＭＤ(Solder Mask defined)構造とＮＳＭＤ(Non-Solder Mask defined)構造がある。   In the BGA type semiconductor package, an electrode pad is provided on one surface of a wiring board, and a solder ball is bonded to the electrode pad. Then, the semiconductor package (semiconductor device) is mounted on the mounting substrate via the solder balls. As an electrode pad structure of such a semiconductor package, there are an SMD (Solder Mask defined) structure and an NSMD (Non-Solder Mask defined) structure.

このようなＳＭＤ構造やＮＳＭＤ構造の電極パッドを適用した半導体パッケージは、例えば特開２００５−２５２０７４号公報（特許文献１参照）に開示されている。   A semiconductor package to which such an SMD structure or NSMD structure electrode pad is applied is disclosed in, for example, Japanese Patent Application Laid-Open No. 2005-252074 (see Patent Document 1).

また、ＳＭＤ構造とＮＳＭＤ構造のそれぞれの特徴を１つの電極パッドに対して適用する技術は、例えば特開２００１−２３０５１３号公報（特許文献２参照）に開示されている。   A technique for applying the features of the SMD structure and NSMD structure to one electrode pad is disclosed in, for example, Japanese Patent Application Laid-Open No. 2001-230513 (see Patent Document 2).

特開２００５−２５２０７４号公報JP 2005-252074 A 特開２００１−２３０５１３号公報JP 2001-230513 A

本願発明者の検討によれば、ＳＭＤ構造とＮＳＭＤ構造のそれぞれには、以下で説明する課題があることがわかった。   According to the study of the present inventor, it has been found that each of the SMD structure and the NSMD structure has the problems described below.

まず、図１４はＳＭＤ構造を示す断面図であり、図１５はその上面図である。配線基板１０１の裏面に電極パッド１０２が設けられている。この電極パッド１０２の一部は、絶縁膜１０３に設けられた開口部１０４から露出し、この露出面において半田ボール１０５と接合している。そして、電極パッド１０２の周縁は絶縁膜１０３で覆われている。このようなＳＭＤ構造では、電極パッド１０２を半田ボール１０５との接合面よりも大きくすることができるため、半導体チップから、配線基板の裏面の配線（配線パターン）、電極パッド１０２及び半田ボール１０５を介して実装基板へと続く放熱経路の幅を相対的に広く（太く）することができ、熱抵抗を下げることができる。しかし、電極パッド１０２の露出面（電極パッドの上面の一部）しか半田ボール１０５と接合されないため、半導体パッケージと実装基板の熱膨張係数の差に起因した平面方向（水平方向）の応力（温度サイクルストレス）に弱い。詳細に説明すると、半導体パッケージと実装基板のそれぞれの熱膨張係数は互いに異なるため、半導体パッケージを実装基板に実装する際のリフロー処理による熱の影響で、半導体パッケージと実装基板のそれぞれに膨張・収縮作用が働くが、熱膨張係数が異なることから、この膨張・収縮率が異なり、半田ボールに対して水平方向における応力が働く。しかし、図１４に示すようなＳＭＤ構造の場合、半田ボール１０５は電極パッド１０２の上面の一部としか接合していないため、水平方向の応力が半田ボール１０５に生じると、半田ボール１０５の接合部付近に応力が集中し、クラックが発生し易いことがわかった。   First, FIG. 14 is a sectional view showing an SMD structure, and FIG. 15 is a top view thereof. An electrode pad 102 is provided on the back surface of the wiring substrate 101. A part of the electrode pad 102 is exposed from the opening 104 provided in the insulating film 103, and is bonded to the solder ball 105 on the exposed surface. The periphery of the electrode pad 102 is covered with an insulating film 103. In such an SMD structure, since the electrode pad 102 can be made larger than the joint surface with the solder ball 105, the wiring (wiring pattern) on the back surface of the wiring board, the electrode pad 102 and the solder ball 105 can be formed from the semiconductor chip. Thus, the width of the heat dissipation path that continues to the mounting substrate can be made relatively wide (thick), and the thermal resistance can be lowered. However, since only the exposed surface of the electrode pad 102 (a part of the upper surface of the electrode pad) is bonded to the solder ball 105, the stress (temperature) in the planar direction (horizontal direction) due to the difference in the thermal expansion coefficient between the semiconductor package and the mounting substrate. It is vulnerable to cycle stress. More specifically, since the thermal expansion coefficients of the semiconductor package and the mounting board are different from each other, the expansion and contraction of the semiconductor package and the mounting board are caused by the influence of heat caused by reflow processing when the semiconductor package is mounted on the mounting board. Although the action works, since the thermal expansion coefficients are different, the expansion / contraction rate is different, and the stress in the horizontal direction acts on the solder ball. However, in the case of the SMD structure as shown in FIG. 14, since the solder ball 105 is bonded only to a part of the upper surface of the electrode pad 102, when horizontal stress is generated in the solder ball 105, the solder ball 105 is bonded. It was found that stress was concentrated near the part and cracks were likely to occur.

一方、図１６はＮＳＭＤ構造を示す断面図であり、図１７（図面が間違っている。引き出し配線がない。）はその上面図である。配線基板１０１の裏面に電極パッド１０６が設けられている。この電極パッド１０６の上面と側面は、絶縁膜１０３に設けられた開口部１０７から露出し、この露出面（上面および側面）において半田ボール１０５と接合している。そして、電極パッド１０６の外形は開口部１０７の径よりも小さい。このようなＮＳＭＤ構造では、半田ボール１０５が電極パッド１０６の上面だけでなく側面部にも回り込むため、平面方向の応力（温度サイクルストレス）に強く、実装信頼性を確保することができる。しかし、電極パッド１０６を絶縁膜１０３の開口部１０７の径よりも小さくするため、電極パッド１０６と配線基板の裏面に形成された配線（配線パターン）とを繋ぐ配線（連結部）１０８は、図１７に示すように、相対的に細く形成される。そのため、半導体チップから、配線基板の裏面の配線（配線パターン）、連結部１０８、電極パッド１０６及び半田ボール１０５を介して実装基板へと続く放熱経路の幅が、連結部１０８において相対的に狭く（細く）なり、熱抵抗が高くなってしまう。また、ＮＳＭＤ構造は、電極パッド１０６の周縁部が絶縁膜１０３で覆われていないため、上下方向（垂直方向）における応力への耐性は、ＳＭＤ構造に比べて低い。そのため、例えば半導体装置が落下した際に生じる垂直方向における応力には、ＳＭＤ構造に比べて弱いことがわかった。   On the other hand, FIG. 16 is a sectional view showing the NSMD structure, and FIG. 17 (the drawing is wrong. There is no lead wiring) is a top view thereof. An electrode pad 106 is provided on the back surface of the wiring substrate 101. The upper surface and side surfaces of the electrode pad 106 are exposed from an opening 107 provided in the insulating film 103, and are bonded to the solder balls 105 on the exposed surfaces (upper surface and side surfaces). The outer shape of the electrode pad 106 is smaller than the diameter of the opening 107. In such an NSMD structure, since the solder ball 105 goes around not only the upper surface of the electrode pad 106 but also the side surface portion, it is resistant to planar stress (temperature cycle stress), and mounting reliability can be ensured. However, in order to make the electrode pad 106 smaller than the diameter of the opening 107 of the insulating film 103, the wiring (connecting portion) 108 that connects the electrode pad 106 and the wiring (wiring pattern) formed on the back surface of the wiring substrate is shown in FIG. As shown in FIG. 17, it is formed relatively thin. Therefore, the width of the heat dissipation path from the semiconductor chip to the mounting substrate via the wiring (wiring pattern) on the back surface of the wiring board, the connecting portion 108, the electrode pad 106 and the solder ball 105 is relatively narrow in the connecting portion 108. (Thinning) and heat resistance becomes high. Further, in the NSMD structure, since the peripheral portion of the electrode pad 106 is not covered with the insulating film 103, resistance to stress in the vertical direction (vertical direction) is lower than that in the SMD structure. Therefore, for example, it was found that the stress in the vertical direction generated when the semiconductor device falls is weaker than that of the SMD structure.

高温領域と低温領域の差が大きい環境で使用される高信頼性の半導体パッケージの場合、垂直方向における耐応力性よりも、半導体パッケージと実装基板の熱膨張係数の差に起因した平面方向の応力に対する耐応力性が要求される。そこで、例えば前記特許文献１に示すように、半導体パッケージの電極パッド構造としては、ＮＳＭＤ構造を基準として採用し、さらに耐応力性も考慮して、半導体パッケージの外周部にはＳＭＤ構造を採用するという技術が提案されていた。   In the case of a highly reliable semiconductor package used in an environment where there is a large difference between the high temperature region and the low temperature region, the stress in the planar direction is due to the difference in the thermal expansion coefficient between the semiconductor package and the mounting substrate, rather than the stress resistance in the vertical direction. Stress resistance is required. Therefore, for example, as shown in Patent Document 1, the electrode pad structure of the semiconductor package is based on the NSMD structure, and in consideration of stress resistance, the SMD structure is employed on the outer periphery of the semiconductor package. The technology was proposed.

また、最外周列の電極パッドのみＳＭＤ構造とし、他の電極パッドをＮＳＭＤ構造とした半導体パッケージも提案されている（例えば、特許文献１参照）。   In addition, a semiconductor package has been proposed in which only the electrode pads in the outermost peripheral row have an SMD structure and other electrode pads have an NSMD structure (see, for example, Patent Document 1).

しかしながら、半導体装置の高機能化に伴って半導体チップの消費電力は１Ｗ以上に増加している。これにより、半導体チップからの発熱量も増大する。また、高温領域と低温領域の差が大きい環境で使用される高信頼性の半導体パッケージの場合、環境温度が頻繁に変動するため、実装時又は実装後の水平方向における耐応力性も要求される。そのため、前記特許文献１のように膨張・収縮作用に対する水平方向における耐応力性を向上するだけでなく、耐応力性も考慮しながら半導体チップから発生する熱を効率良く放熱できる半導体パッケージが要求されている。そのため、ＮＳＭＤ構造の電極パッドを基準とした前記特許文献１の技術では、半導体パッケージの放熱性が劣化するという問題がある。   However, the power consumption of the semiconductor chip has increased to 1 W or more as the functionality of the semiconductor device has increased. As a result, the amount of heat generated from the semiconductor chip also increases. In addition, in the case of a highly reliable semiconductor package used in an environment where the difference between the high temperature region and the low temperature region is large, the environmental temperature frequently fluctuates, so that the stress resistance in the horizontal direction during or after mounting is also required. . Therefore, there is a demand for a semiconductor package that not only improves the stress resistance in the horizontal direction against the expansion / contraction action as in Patent Document 1, but also can efficiently dissipate the heat generated from the semiconductor chip while considering the stress resistance. ing. For this reason, the technique disclosed in Patent Document 1 based on the electrode pad having the NSMD structure has a problem that heat dissipation of the semiconductor package is deteriorated.

また、半導体パッケージと実装基板の熱膨張係数の差に起因した平面方向の応力（温度サイクルストレス）は半導体パッケージの外周部に行くほど大きくなる。従って、特許文献１のように、最外周列の電極パッドを平面方向の応力に弱いＳＭＤ構造にすると、実装信頼性を確保することができない。   Further, the stress in the plane direction (temperature cycle stress) due to the difference in the thermal expansion coefficient between the semiconductor package and the mounting substrate increases as it goes to the outer peripheral portion of the semiconductor package. Therefore, if the electrode pads in the outermost circumferential row have an SMD structure that is weak against stress in the plane direction as in Patent Document 1, mounting reliability cannot be ensured.

また、上記したＳＭＤ構造とＮＳＭＤ構造のそれぞれの特徴を考慮して、前記特許文献２のように、１つの電極パッドに対してＳＭＤ構造とＮＳＭＤ構造のそれぞれの構成を適用することも考えられるが、この場合、電極パッドの周縁部は絶縁膜から露出される部分も存在させることになり、放熱経路の幅を十分に広く（太く）することは困難である。また、このような電極パッドを半導体パッケージに適用した場合、半導体パッケージの外周部に対しても適用されることになる。そのため、ＳＭＤ構造の特徴も考慮して電極パッドの周縁部の一部を絶縁膜で覆った構成では、半田ボールとの接合面積がＮＳＭＤ構造と比べ少なくなり、平面方向における耐応力性を向上させることが困難となり、実装信頼性を確保することができない。   In addition, in consideration of the characteristics of the SMD structure and NSMD structure described above, it is conceivable to apply the configurations of the SMD structure and NSMD structure to one electrode pad as in Patent Document 2. In this case, the peripheral portion of the electrode pad also has a portion exposed from the insulating film, and it is difficult to make the width of the heat dissipation path sufficiently wide (thick). Further, when such an electrode pad is applied to a semiconductor package, it is also applied to the outer peripheral portion of the semiconductor package. Therefore, in the configuration in which a part of the peripheral portion of the electrode pad is covered with an insulating film in consideration of the characteristics of the SMD structure, the bonding area with the solder ball is smaller than that of the NSMD structure, and the stress resistance in the planar direction is improved. This makes it difficult to ensure mounting reliability.

本発明は、上述のような課題を解決するためになされたもので、その目的は、実装信頼性を確保しながら放熱性を向上することができる半導体パッケージを得るものである。   The present invention has been made to solve the above-described problems, and an object of the present invention is to obtain a semiconductor package capable of improving heat dissipation while ensuring mounting reliability.

本発明の一実施例に係る半導体装置は、主面及び裏面を有する配線基板と、配線基板の主面に搭載された半導体チップと、配線基板の裏面において、半導体チップに対して平面的に内側の領域に配置された複数の第１電極パッドと、配線基板の裏面において、半導体チップに対して平面的に外側の領域に配置された複数の第２電極パッドと、配線基板の裏面に設けられた絶縁膜とを備える。第１，２電極パッドは、絶縁膜に設けられた第１，２開口部からそれぞれ露出する。第１電極パッドの周縁は絶縁膜で覆われている。第２電極パッドの外形は第２開口部よりも小さい。   A semiconductor device according to an embodiment of the present invention includes a wiring board having a main surface and a back surface, a semiconductor chip mounted on the main surface of the wiring board, and a planar inner surface with respect to the semiconductor chip on the back surface of the wiring board. A plurality of first electrode pads disposed in the region, a plurality of second electrode pads disposed in a region outside the semiconductor chip in a plane on the back surface of the wiring substrate, and a back surface of the wiring substrate. And an insulating film. The first and second electrode pads are exposed from first and second openings provided in the insulating film, respectively. The periphery of the first electrode pad is covered with an insulating film. The outer shape of the second electrode pad is smaller than the second opening.

この実施例によれば、半導体装置の実装信頼性を確保しながら放熱性を向上することができる。   According to this embodiment, the heat dissipation can be improved while ensuring the mounting reliability of the semiconductor device.

実施の形態１．
図１は、本発明の実施の形態１に係る半導体パッケージを示す断面図であり、図２は上面図、図３は下面図である。この半導体パッケージは、高温領域と低温領域の差が大きい環境で使用される高信頼性の半導体パッケージであり、その使用環境は−４０℃〜＋１２５℃である。 Embodiment 1 FIG.
1 is a cross-sectional view showing a semiconductor package according to Embodiment 1 of the present invention, FIG. 2 is a top view, and FIG. 3 is a bottom view. This semiconductor package is a highly reliable semiconductor package used in an environment where a difference between a high temperature region and a low temperature region is large, and the usage environment is −40 ° C. to + 125 ° C.

配線基板１１は、互いに反対側に位置する主面及び裏面を有する。配線基板１１としては、例えば、ガラス繊維にエポキシ系又はポリイミド系の樹脂を含浸させた樹脂基板からなるコア材が用いられている。樹脂基板からなるコア材を主体とする配線基板１１は、１５×１０−６／Ｋ程度の線膨張係数を有する。 The wiring substrate 11 has a main surface and a back surface located on opposite sides. As the wiring substrate 11, for example, a core material made of a resin substrate in which glass fiber is impregnated with an epoxy-based or polyimide-based resin is used. The wiring substrate 11 mainly composed of a core material made of a resin substrate has a linear expansion coefficient of about 15 × 10 −6 / K.

この配線基板１１の主面に、Ｃｕなどの金属膜で形成されたボンディングパッド１２及びベタパターン１３が設けられている。ボンディングパッド１２は絶縁膜（ソルダレジスト膜）１４に設けられた開口部１５から露出している。そして、配線基板１１の主面の中央部のベタパターン１３上に、平面形状が四角形の半導体チップ１６が搭載されている。半導体チップ１６は、シリコンからなる半導体基板を主体とし、３×１０−６／Ｋ程度の線膨張係数を有する。 A bonding pad 12 and a solid pattern 13 formed of a metal film such as Cu are provided on the main surface of the wiring substrate 11. The bonding pad 12 is exposed from an opening 15 provided in the insulating film (solder resist film) 14. A semiconductor chip 16 having a square planar shape is mounted on the solid pattern 13 at the center of the main surface of the wiring board 11. The semiconductor chip 16 is mainly composed of a semiconductor substrate made of silicon and has a linear expansion coefficient of about 3 × 10 −6 / K.

この半導体チップ１６とボンディングパッド１２はＡｕワイヤ１７により接続されている。これらの半導体チップ１６やＡｕワイヤ１７等はモールド樹脂１８で封止されている。モールド樹脂１８としては、低応力化を図る目的として、例えば、フェノール系硬化剤、シリコーンゴム及びフィラー等が添加されたビフェニール系の熱硬化性樹脂が用いられている。   The semiconductor chip 16 and the bonding pad 12 are connected by an Au wire 17. These semiconductor chip 16, Au wire 17 and the like are sealed with a mold resin 18. As the mold resin 18, for the purpose of reducing the stress, for example, a biphenyl thermosetting resin to which a phenolic curing agent, silicone rubber, filler, and the like are added is used.

配線基板１１の裏面において、半導体チップ１６に対して平面的に内側の領域に複数の第１電極パッド２１が配置され、半導体チップ１６に対して平面的に外側の領域に複数の第２電極パッド２２が配置されている。第１電極パッド２１と第２電極パッド２２の間隔は、図１に示すように、第１電極パッド２２、又は第２電極パッド２２のそれぞれの幅以上である。また、配線基板１１の裏面には、これら複数の電極パッド２１，２２と繋がる複数の配線（配線パターン）が形成されており、この複数の配線を保護するための絶縁膜（ソルダレジスト膜）２３が設けられている。また、絶縁膜２３の開口部から露出した第１，第２電極パッド２１，２２には半田ボール（外部端子）２４が接合されている。絶縁膜１４，２３としては、例えば、二液性アルカリ現像液型ソルダーレジストインキ、又は熱硬化型一液性ソルダーレジストインキからなる絶縁膜が用いられている。半田ボール２４は、Ｓｎ（錫）−Ｐｂ（鉛）組成や、環境汚染問題対策を考慮したＳｎ（錫）−Ａｇ（銀）−Ｃｕ（銅）組成等の半田材からなる。   On the back surface of the wiring substrate 11, a plurality of first electrode pads 21 are disposed in a region that is planarly inner with respect to the semiconductor chip 16, and a plurality of second electrode pads are disposed in a region that is planarly outer with respect to the semiconductor chip 16. 22 is arranged. As shown in FIG. 1, the distance between the first electrode pad 21 and the second electrode pad 22 is not less than the width of each of the first electrode pad 22 or the second electrode pad 22. In addition, a plurality of wirings (wiring patterns) connected to the plurality of electrode pads 21 and 22 are formed on the back surface of the wiring substrate 11, and an insulating film (solder resist film) 23 for protecting the plurality of wirings. Is provided. Solder balls (external terminals) 24 are joined to the first and second electrode pads 21 and 22 exposed from the opening of the insulating film 23. As the insulating films 14 and 23, for example, an insulating film made of a two-component alkaline developer solder resist ink or a thermosetting one-component solder resist ink is used. The solder ball 24 is made of a solder material such as a Sn (tin) -Pb (lead) composition or a Sn (tin) -Ag (silver) -Cu (copper) composition in consideration of measures against environmental pollution problems.

また、ベタパターン１３はスルーホール２５を介して第１電極パッド２１に接続されている。そして、ボンディングパッド１２は配線２６及びスルーホール２７および配線基板の裏面に形成された配線を介して第２電極パッド２２に接続されている。   The solid pattern 13 is connected to the first electrode pad 21 through the through hole 25. The bonding pad 12 is connected to the second electrode pad 22 through the wiring 26, the through hole 27, and the wiring formed on the back surface of the wiring board.

第１，第２電極パッド２１，２２は、絶縁膜２３に設けられた第１，第２開口部２８，２９からそれぞれ露出している。そして、第１電極パッド２１の周縁は絶縁膜２３で覆われている。従って、第１電極パッド２１はＳＭＤ構造である。一方、第２電極パッド２２の外形は第２開口部２９よりも小さい。従って、第２電極パッド２２はＮＳＭＤ構造である。このとき、図１ではＮＳＭＤ構造の第２電極パッド２２の周囲に形成された絶縁膜２３と表面の高さが同じように記載しているが、ＳＭＤ構造の第1電極パッド２１は、第1電極パッド２１の周縁部を絶縁膜２３が覆う構成のため、電極パッド部の詳細な構成としては、図示しないが絶縁膜２３がＮＳＭＤ構造側の絶縁膜２３よりも迫り出している。   The first and second electrode pads 21 and 22 are exposed from first and second openings 28 and 29 provided in the insulating film 23, respectively. The periphery of the first electrode pad 21 is covered with an insulating film 23. Therefore, the first electrode pad 21 has an SMD structure. On the other hand, the outer shape of the second electrode pad 22 is smaller than that of the second opening 29. Accordingly, the second electrode pad 22 has an NSMD structure. At this time, in FIG. 1, the surface height of the insulating film 23 formed around the second electrode pad 22 having the NSMD structure is the same as that of the first electrode pad 21 having the SMD structure. Since the insulating film 23 covers the periphery of the electrode pad 21, the detailed structure of the electrode pad portion is not shown, but the insulating film 23 protrudes more than the insulating film 23 on the NSMD structure side.

図４は、図３の点線で囲った領域Ａを拡大した図である。配線基板１１の中央部に４×４個の半田ボール２４が並べられている。このうち四隅の半田ボール２４と接続される第１電極パッド２１を電源Ｖｃｃに接続されたベタパターンとし、他の半田ボール２４と接続される第１電極パッド２１をＧＮＤに接続されたベタパターンとする。   FIG. 4 is an enlarged view of a region A surrounded by a dotted line in FIG. 4 × 4 solder balls 24 are arranged in the center of the wiring board 11. Of these, the first electrode pads 21 connected to the solder balls 24 at the four corners are solid patterns connected to the power supply Vcc, and the first electrode pads 21 connected to the other solder balls 24 are solid patterns connected to the GND. To do.

図５は、本発明の実施の形態１に係る半導体パッケージを実装基板に実装した状態を示す断面図である。実装基板３１は、コア材３２と、このコア材３２の主面に設けられたＣｕなどからなる電極パッド３３と、コア材３２の主面及び裏面に設けられた絶縁膜３４とを有する。コア材３２としては、例えば、ガラス繊維にエポキシ系又はポリイミド系の樹脂を含浸させた樹脂基板が用いられている。絶縁膜３４としては、例えば、二液性アルカリ現像液型ソルダーレジストインキ、又は熱硬化型一液性ソルダーレジストインキからなる絶縁膜が用いられている。   FIG. 5 is a cross-sectional view showing a state where the semiconductor package according to Embodiment 1 of the present invention is mounted on a mounting substrate. The mounting substrate 31 includes a core material 32, an electrode pad 33 made of Cu or the like provided on the main surface of the core material 32, and an insulating film 34 provided on the main surface and the back surface of the core material 32. As the core material 32, for example, a resin substrate in which glass fiber is impregnated with epoxy or polyimide resin is used. As the insulating film 34, for example, an insulating film made of a two-component alkaline developer solder resist ink or a thermosetting one-component solder resist ink is used.

電極パッド３３は絶縁膜３４に設けられた開口部３５から露出している。コア材３２として、例えば、ガラス繊維にエポキシ系又はポリイミド系の樹脂を含浸させた樹脂基板を用いる。絶縁膜３４として、例えば、二液性アルカリ現像液型ソルダーレジストインキ、又は熱硬化型一液性ソルダーレジストインキからなる絶縁膜を用いる。   The electrode pad 33 is exposed from an opening 35 provided in the insulating film 34. As the core material 32, for example, a resin substrate in which glass fiber is impregnated with epoxy or polyimide resin is used. As the insulating film 34, for example, an insulating film made of a two-component alkaline developer solder resist ink or a thermosetting one-component solder resist ink is used.

以上説明したように、本実施の形態では、半導体チップ１６に対して平面的に内側の領域において、複数の電極パッドを設けている。そのため、ベタパターン１３、スルーホール２５、第１電極パッド２１及び半田ボール２４を介すことで、半導体チップ１６から発生した熱を、半導体チップ１６の外周部に経由させるよりも短い距離で実装基板３１に伝搬させることができるため、放熱効果を向上することができる。また、半導体チップ１６と平面的に重なる領域内に設けられた複数の電極パッドの構造としてＳＭＤ構造を採用することで、半導体チップ１６からベタパターン１３、スルーホール２５、第１電極パッド２１及び半田ボール２４を介して実装基板３１へと続く放熱経路の熱抵抗を下げることができる。従って、半導体パッケージの放熱性を向上することができる。   As described above, in the present embodiment, a plurality of electrode pads are provided in a region that is planarly inner with respect to the semiconductor chip 16. Therefore, the mounting substrate can be mounted at a shorter distance than the heat generated from the semiconductor chip 16 through the solid pattern 13, the through hole 25, the first electrode pad 21, and the solder ball 24 via the outer periphery of the semiconductor chip 16. Therefore, the heat dissipation effect can be improved. Further, by adopting an SMD structure as a structure of a plurality of electrode pads provided in a region overlapping with the semiconductor chip 16 in plan view, the solid pattern 13, the through hole 25, the first electrode pad 21 and the solder are formed from the semiconductor chip 16. The thermal resistance of the heat dissipation path that continues to the mounting substrate 31 via the balls 24 can be lowered. Therefore, the heat dissipation of the semiconductor package can be improved.

また、高温領域と低温領域の差が大きい環境で使用される高信頼性の半導体パッケージの場合、半導体パッケージと実装基板の熱膨張係数の差に起因した平面方向の応力（温度サイクルストレス）が半田ボールに集中する。しかしながら、この平面方向の応力は半導体パッケージの外周部に行くほど大きくなるが、本実施の形態では、半導体チップ１６に対して平面的に外側の領域において電極パッド構造として平面方向の応力に強いＮＳＭＤ構造を採用している。すなわち、半導体パッケージの外周部に設けられた複数の電極パッドの構造としてＮＳＭＤ構造を採用している。このため、応力が半田ボールに集中したとしても、図６に示すように、半田ボール２４は電極パッド２２，３３に対してずれるように変動することが可能となるため、耐応力性を向上することができ、実装信頼性を確保することができる。   In the case of a highly reliable semiconductor package used in an environment where the difference between the high temperature region and the low temperature region is large, the stress in the plane direction (temperature cycle stress) caused by the difference in the thermal expansion coefficient between the semiconductor package and the mounting substrate is solder. Concentrate on the ball. However, the stress in the planar direction increases as it goes to the outer peripheral portion of the semiconductor package. However, in the present embodiment, NSMD which is strong against the stress in the planar direction as an electrode pad structure in a region outside the planar surface with respect to the semiconductor chip 16. The structure is adopted. That is, the NSMD structure is adopted as the structure of the plurality of electrode pads provided on the outer periphery of the semiconductor package. For this reason, even if the stress is concentrated on the solder ball, the solder ball 24 can fluctuate with respect to the electrode pads 22 and 33 as shown in FIG. And mounting reliability can be ensured.

また、実装基板３１の複数の電極パッド３３において、図５に示すように、半導体パッケージの中央部に設けられた第1電極パッド２１と対応する位置に設けられた電極パッド３３もＳＭＤ構造にすることで、半導体パッケージ内の半導体チップ１６から発生した熱を、実装基板３１に効率良く伝えるだけでなく、実装基板３１に放熱された熱を、半導体パッケージの直下に滞留させずに、半導体パッケージから離れた位置に効率良く放熱することが可能となる。   Further, in the plurality of electrode pads 33 of the mounting substrate 31, as shown in FIG. 5, the electrode pads 33 provided at positions corresponding to the first electrode pads 21 provided in the central portion of the semiconductor package are also formed in the SMD structure. Thus, not only the heat generated from the semiconductor chip 16 in the semiconductor package is efficiently transmitted to the mounting substrate 31 but also the heat radiated to the mounting substrate 31 is not accumulated in the semiconductor package directly from the semiconductor package. It is possible to efficiently dissipate heat at a distant position.

さらには、実装基板３１の複数の電極パッド３３において、図５に示すように、半導体パッケージの外周部に設けられた第２電極パッド２２と対応する位置に設けられた電極パッド３３もＮＳＭＤ構造にすることで、半導体パッケージと実装基板３１との間における実装強度をより向上することが可能である。   Further, in the plurality of electrode pads 33 of the mounting substrate 31, as shown in FIG. 5, the electrode pads 33 provided at positions corresponding to the second electrode pads 22 provided on the outer peripheral portion of the semiconductor package also have an NSMD structure. As a result, the mounting strength between the semiconductor package and the mounting substrate 31 can be further improved.

本発明の実施の形態１に係る半導体パッケージの製造方法について、図７に示すフローチャートを参照しながら説明する。   A method for manufacturing a semiconductor package according to the first embodiment of the present invention will be described with reference to the flowchart shown in FIG.

まず、図８に示すように、配線基板１１の主面の中央部のベタパターン１３上に、接着層（不図示）を用いて、平面形状が四角形の半導体チップ１６を搭載する（ステップＳ１）。   First, as shown in FIG. 8, a semiconductor chip 16 having a square planar shape is mounted on the solid pattern 13 at the center of the main surface of the wiring board 11 using an adhesive layer (not shown) (step S1). .

次に、図９に示すように、半導体チップ１６と配線基板１１の主面のボンディングパッド１２をＡｕワイヤ１７により接続する（ステップＳ２）。   Next, as shown in FIG. 9, the semiconductor chip 16 and the bonding pad 12 on the main surface of the wiring substrate 11 are connected by the Au wire 17 (step S2).

次に、図１０に示すように、半導体チップ１６やＡｕワイヤ１７等をモールド樹脂１８で封止する（ステップＳ３）。モールド樹脂１８の形成方法としては、大量生産に好適なトランスファ・モールディング法を用いている。トランスファ・モールディング法とは、ポット、ランナー、樹脂注入ゲート、及びキャビティ等を備えた成形金型（モールド金型）を使用し、ポットからランナー及び樹脂注入ゲートを通してキャビティの内部に熱硬化性樹脂を注入して樹脂封止体を形成する方法である。そして、複数の製品形成領域を有する多数個取り配線基板を使用し、各製品形成領域に搭載された半導体チップを一括して樹脂封止する一括方式のトランスファ・モールディング法が採用されている。   Next, as shown in FIG. 10, the semiconductor chip 16, the Au wire 17, and the like are sealed with a mold resin 18 (step S3). As a method for forming the mold resin 18, a transfer molding method suitable for mass production is used. The transfer molding method uses a mold (mold) with a pot, runner, resin injection gate, cavity, etc., and thermosetting resin is injected into the cavity from the pot through the runner and resin injection gate. This is a method of forming a resin sealing body by pouring. A collective transfer molding method is used in which a multi-chip wiring substrate having a plurality of product forming regions is used and semiconductor chips mounted in each product forming region are collectively sealed with resin.

次に、図１１に示すように、配線基板１１の裏面の第１，第２電極パッド２１，２２に半田ボール２４を接合する（ステップＳ４）。   Next, as shown in FIG. 11, solder balls 24 are joined to the first and second electrode pads 21 and 22 on the back surface of the wiring board 11 (step S4).

最後に、図１２に示すように、ダイシングによって個々の半導体パッケージごとに個片化する（ステップＳ５）。以上の工程により、本実施の形態１に係る半導体パッケージが製造される。   Finally, as shown in FIG. 12, the individual semiconductor packages are separated into individual pieces by dicing (step S5). Through the above steps, the semiconductor package according to the first embodiment is manufactured.

実施の形態２．
図１３は、本発明の実施の形態２に係る半導体パッケージを示す断面図である。配線基板１１の裏面において、半導体チップ１６の端部と平面的に重なる位置に、複数の第３電極パッド４１が配置されている。第３電極パッド４１は、絶縁膜に設けられた第３開口部４２から露出している。第３電極パッド４１の外形は第３開口部４２よりも小さい。従って、第３電極パッド４１はＮＳＭＤ構造である。その他の構成は実施の形態１と同様である。 Embodiment 2. FIG.
FIG. 13 is a cross-sectional view showing a semiconductor package according to Embodiment 2 of the present invention. On the back surface of the wiring substrate 11, a plurality of third electrode pads 41 are arranged at positions that overlap the end portions of the semiconductor chip 16 in a planar manner. The third electrode pad 41 is exposed from the third opening 42 provided in the insulating film. The outer shape of the third electrode pad 41 is smaller than that of the third opening 42. Therefore, the third electrode pad 41 has an NSMD structure. Other configurations are the same as those in the first embodiment.

半導体チップ１６の端部と平面的に重なる位置は応力が集中する。これは、上記したように、半導体チップ１６がシリコンで構成されているのに対し、配線基板１１は例えば、ガラス繊維にエポキシ系又はポリイミド系の樹脂を含浸させた樹脂基板からなるコア材が用いられている。そのため、半導体チップ１６と配線基板１１のそれぞれの熱膨張係数が異なる。また、半導体チップ１６は、その主面を上方に向けて配線基板の主面上に搭載されている。言い換えると、半導体チップ１６の裏面は、配線基板１１の主面と接着材を介して接合されている。そのため、環境温度の変動により、この熱膨張係数の差に起因して、半導体チップ１６の端部と平面的に重なる位置に応力が集中し易い。この結果、この位置に電極パッドが設けられた場合、電極パッドや、この電極パッドに接合される半田ボールにまで応力が伸展する。   Stress concentrates at a position overlapping the end of the semiconductor chip 16 in a plan view. This is because, as described above, the semiconductor chip 16 is made of silicon, while the wiring substrate 11 is made of a core material made of a resin substrate in which an epoxy resin or a polyimide resin is impregnated into glass fiber, for example. It has been. Therefore, the thermal expansion coefficients of the semiconductor chip 16 and the wiring board 11 are different. The semiconductor chip 16 is mounted on the main surface of the wiring board with its main surface facing upward. In other words, the back surface of the semiconductor chip 16 is bonded to the main surface of the wiring substrate 11 via the adhesive. For this reason, due to the variation in the environmental temperature, the stress tends to concentrate on the position overlapping the end of the semiconductor chip 16 in a planar manner due to the difference in the thermal expansion coefficient. As a result, when the electrode pad is provided at this position, the stress extends to the electrode pad and the solder ball bonded to the electrode pad.

このとき、前記実施の形態１のように、半導体チップ１６の端部と平面的に重なる領域に電極パッドが設けられていない場合、又は中央部に設けられた第1電極パッド２１と外周部に設けられた第２電極パッド２２との間隔が、第1電極パッド２１（又は、第２電極パッド２２）の幅以上となるように複数の電極パッドが配置されていれば、応力が電極パッドに集中し難くなるが、本実施の形態２のように、更なる半導体装置の小型化が進んだ場合、又は搭載する半導体チップ１６のサイズが変更された場合には、電極パッドが半導体チップ１６の端部と平面的に重なることがある。   At this time, as in the first embodiment, when the electrode pad is not provided in a region overlapping the end of the semiconductor chip 16 in a plan view, or in the outer periphery with the first electrode pad 21 provided in the central portion. If a plurality of electrode pads are arranged so that the distance from the provided second electrode pad 22 is equal to or larger than the width of the first electrode pad 21 (or the second electrode pad 22), stress is applied to the electrode pad. Although it becomes difficult to concentrate, when further downsizing of the semiconductor device is advanced as in the second embodiment, or when the size of the semiconductor chip 16 to be mounted is changed, the electrode pads are formed on the semiconductor chip 16. It may overlap with the end in a plane.

そこで、図１３に示すように、この位置に配置される第３電極パッド４１を応力に強いＮＳＭＤ構造にすることで、更に実装信頼性を確保することができる。   Therefore, as shown in FIG. 13, the mounting reliability can be further ensured by making the third electrode pad 41 arranged at this position into an NSMD structure resistant to stress.

以上、本発明者によってなされた発明を発明の実施の形態に基づき具体的に説明したが、本発明は前記発明の実施の形態に限定されるものではなく、その要旨を逸脱しない範囲で種々変更可能であることは言うまでもない。   As mentioned above, the invention made by the present inventor has been specifically described based on the embodiments of the invention. However, the present invention is not limited to the embodiments of the invention, and various modifications can be made without departing from the scope of the invention. It goes without saying that it is possible.

本発明の実施の形態１に係る半導体パッケージを示す断面図である。It is sectional drawing which shows the semiconductor package which concerns on Embodiment 1 of this invention. 本発明の実施の形態１に係る半導体パッケージを示す上面図である。It is a top view which shows the semiconductor package which concerns on Embodiment 1 of this invention. 本発明の実施の形態１に係る半導体パッケージを示す下面図である。It is a bottom view which shows the semiconductor package which concerns on Embodiment 1 of this invention. 図３の点線で囲った領域Ａを拡大した図である。It is the figure which expanded the area | region A enclosed with the dotted line of FIG. 本発明の実施の形態１に係る半導体パッケージを実装基板に実装した状態を示す断面図である。It is sectional drawing which shows the state which mounted the semiconductor package which concerns on Embodiment 1 of this invention on the mounting board | substrate. 膨張・収縮作用により半導体パッケージの電極パッドの位置と実装基板の電極パッドの位置とが平面的にずれた状態を示す断面図である。It is sectional drawing which shows the state which the position of the electrode pad of the semiconductor package and the position of the electrode pad of the mounting substrate shifted | deviated planarly by expansion / contraction action. 本発明の実施の形態１に係る半導体パッケージの製造方法を説明するためのフローチャートである。It is a flowchart for demonstrating the manufacturing method of the semiconductor package which concerns on Embodiment 1 of this invention. 本発明の実施の形態１に係る半導体パッケージの製造方法を説明するための断面図である。It is sectional drawing for demonstrating the manufacturing method of the semiconductor package which concerns on Embodiment 1 of this invention. 本発明の実施の形態１に係る半導体パッケージの製造方法を説明するための断面図である。It is sectional drawing for demonstrating the manufacturing method of the semiconductor package which concerns on Embodiment 1 of this invention. 本発明の実施の形態１に係る半導体パッケージの製造方法を説明するための断面図である。It is sectional drawing for demonstrating the manufacturing method of the semiconductor package which concerns on Embodiment 1 of this invention. 本発明の実施の形態１に係る半導体パッケージの製造方法を説明するための断面図である。It is sectional drawing for demonstrating the manufacturing method of the semiconductor package which concerns on Embodiment 1 of this invention. 本発明の実施の形態１に係る半導体パッケージの製造方法を説明するための断面図である。It is sectional drawing for demonstrating the manufacturing method of the semiconductor package which concerns on Embodiment 1 of this invention. 本発明の実施の形態２に係る半導体パッケージを示す断面図である。It is sectional drawing which shows the semiconductor package which concerns on Embodiment 2 of this invention. ＳＭＤ構造を示す断面図である。It is sectional drawing which shows a SMD structure. ＳＭＤ構造を示す上面図である。It is a top view which shows a SMD structure. ＮＳＭＤ構造を示す断面図である。It is sectional drawing which shows NSMD structure. ＮＳＭＤ構造を示す上面図である。It is a top view which shows NSMD structure.

符号の説明Explanation of symbols

１１ 配線基板
１６ 半導体チップ
２１ 第１電極パッド
２２ 第２電極パッド
２３ 絶縁膜
２８ 第１開口部
２９ 第２開口部
４１ 第３電極パッド
４２ 第３開口部 11 Wiring Board 16 Semiconductor Chip 21 First Electrode Pad 22 Second Electrode Pad 23 Insulating Film 28 First Opening 29 Second Opening 41 Third Electrode Pad 42 Third Opening

Claims (6)

主面と、前記主面と反対側の裏面を有する配線基板と、
前記配線基板の主面に搭載された半導体チップと、
前記配線基板の裏面において、前記半導体チップに対して平面的に内側の領域に配置された複数の第１電極パッドと、
前記配線基板の裏面において、前記半導体チップに対して平面的に外側の領域に配置された複数の第２電極パッドと、
前記配線基板の裏面に設けられた絶縁膜と、
前記第１電極パッドおよび前記第２電極パッドのそれぞれに接続される複数の外部端子とを備え、
前記第１，２電極パッドは、前記絶縁膜に設けられた第１，２開口部からそれぞれ露出し、
前記第１電極パッドの周縁は前記絶縁膜で覆われ、
前記第２電極パッドの外形は前記第２開口部よりも小さいことを特徴とする半導体装置。 A wiring board having a main surface and a back surface opposite to the main surface;
A semiconductor chip mounted on the main surface of the wiring board;
A plurality of first electrode pads disposed in a region planarly inside the semiconductor chip on the back surface of the wiring board;
A plurality of second electrode pads disposed in a region outside the plane in relation to the semiconductor chip on the back surface of the wiring board;
An insulating film provided on the back surface of the wiring board;
A plurality of external terminals connected to each of the first electrode pad and the second electrode pad;
The first and second electrode pads are respectively exposed from first and second openings provided in the insulating film,
The periphery of the first electrode pad is covered with the insulating film,
2. The semiconductor device according to claim 1, wherein an outer shape of the second electrode pad is smaller than the second opening. 前記半導体チップは、前記配線基板の主面の中央部に搭載されていることを特徴とする請求項１に記載の半導体装置。   The semiconductor device according to claim 1, wherein the semiconductor chip is mounted on a central portion of a main surface of the wiring board. 前記第１電極パッドと前記第２電極パッドの間隔は、前記第１電極パッド又は前記第２電極パッドの幅を有することを特徴とする請求項１又は２に記載の半導体装置。   3. The semiconductor device according to claim 1, wherein an interval between the first electrode pad and the second electrode pad has a width of the first electrode pad or the second electrode pad. 前記配線基板の裏面において、前記半導体チップの端部と平面的に重なる位置に配置された複数の第３電極パッドを更に備え、
前記第３電極パッドは、前記絶縁膜に設けられた第３開口部から露出し、
前記第３電極パッドの外形は前記第３開口部よりも小さいことを特徴とする請求項３に記載の半導体装置。 A plurality of third electrode pads disposed on the back surface of the wiring board at positions overlapping the end portions of the semiconductor chip in a plane;
The third electrode pad is exposed from a third opening provided in the insulating film,
The semiconductor device according to claim 3, wherein an outer shape of the third electrode pad is smaller than the third opening. 前記半導体チップの平面形状は四角形であることを特徴とする請求項４に記載の半導体装置。   The semiconductor device according to claim 4, wherein a planar shape of the semiconductor chip is a quadrangle. 前記複数の第１電極パッドは、電源又はＧＮＤ用の端子であることを特徴とする請求項１〜５の何れか１項に記載の半導体装置。
6. The semiconductor device according to claim 1, wherein the plurality of first electrode pads are terminals for power supply or GND.
JP2007182499A 2007-07-11 2007-07-11 Semiconductor device Pending JP2009021366A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2011021690A1 (en) * 2009-08-20 2011-02-24 日本電気株式会社 Semiconductor device having power supply-side metal reinforcing member and ground-side metal reinforcing member insulated from each other
US8963327B2 (en) 2012-05-11 2015-02-24 Renesas Electronics Corporation Semiconductor device including wiring board with semiconductor chip

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2011021690A1 (en) * 2009-08-20 2011-02-24 日本電気株式会社 Semiconductor device having power supply-side metal reinforcing member and ground-side metal reinforcing member insulated from each other
US8547705B2 (en) 2009-08-20 2013-10-01 Nec Corporation Semiconductor device having power supply-side and ground-side metal reinforcing members insulated from each other
US8963327B2 (en) 2012-05-11 2015-02-24 Renesas Electronics Corporation Semiconductor device including wiring board with semiconductor chip

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