JP2009158711A - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP2009158711A JP2009158711A JP2007334738A JP2007334738A JP2009158711A JP 2009158711 A JP2009158711 A JP 2009158711A JP 2007334738 A JP2007334738 A JP 2007334738A JP 2007334738 A JP2007334738 A JP 2007334738A JP 2009158711 A JP2009158711 A JP 2009158711A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 78
- 230000005611 electricity Effects 0.000 claims abstract description 5
- 230000015556 catabolic process Effects 0.000 abstract description 6
- 239000010410 layer Substances 0.000 description 24
- 239000000758 substrate Substances 0.000 description 23
- 229910052581 Si3N4 Inorganic materials 0.000 description 10
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 8
- 238000010586 diagram Methods 0.000 description 8
- 238000004519 manufacturing process Methods 0.000 description 8
- 238000000034 method Methods 0.000 description 8
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- 238000001020 plasma etching Methods 0.000 description 6
- 229910052814 silicon oxide Inorganic materials 0.000 description 6
- 230000008901 benefit Effects 0.000 description 5
- 239000012535 impurity Substances 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 239000011229 interlayer Substances 0.000 description 3
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- 238000002955 isolation Methods 0.000 description 3
- 230000008018 melting Effects 0.000 description 3
- 238000002844 melting Methods 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- 230000001133 acceleration Effects 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 238000000926 separation method Methods 0.000 description 2
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Abstract
【解決手段】半導体層からなる複数のフィン15a〜15fと、複数のフィン15a〜15fの側面上にゲート絶縁膜16を介して設けられたゲートG1〜G6が、互いに電気的に接続されたゲート電極17と、ゲート電極17を挟むように、複数のフィン15a〜15f内に設けられたソースS1〜S6およびドレインD1〜D6と、複数のソースS1〜S6を電気的に接続するソース電極19と、複数のドレインD1〜D6を電気的に接続するドレイン電極18と、ゲート電極17に外部から電気を供給するためのゲートコンタクト20と、を備え、複数のフィン15a〜15fのうち、ゲートコンタクト20との距離が小さい方にあるフィン15a、15bの幅W1、W2が、ゲートコンタクト20との距離が大きい方にあるフィン15c〜15fの幅W3〜W6よりも大きい。
【選択図】図1
Description
フィン15a〜15fは、例えば半導体基板14に対して垂直に形成され、FinFETM1〜M6のチャネル部となる。FinFETM1〜M6は、NチャネルMOSFETである。
ドレイン電極18は、ドレイン電極18のドレインD1側に形成されたドレインコンタクト22で、ワイヤ23を介して入力端子(図示せず)に接続されている。
ソース電極19は、ソース電極19のソースS1側に形成されたソースコンタクト24で、基準電位GNDに接続されている。
図2に示すように、半導体装置30は、内部回路31、例えばFinFETを有するロジック回路と、内部回路31に接続された入出力端子32と、入出力端子32と内部回路31の結線に接続された半導体装置10とを具備している。
これにより、入出力端子32にサージ電流が流れ込んだ場合、半導体装置10がオン状態になりサージ電流をバイバスするので、サージ電流が内部回路31に流れ込むのを阻止し、ESD保護素子として機能する。
サージではなく、しきい値以下の電圧が入出力端子32に印加された場合は、半導体装置10はオンしないので、入出力端子32を介して内部回路31との信号のやり取りが行なえる。
通常は、ゲートコンタクト20に一番近いFinFETM1が最初に動作し、一番遠いFinFETM6が最後に動作する。
このとき、最初にオンしたFinFETM1にサージ電流が集中し、短時間に大電流が流れて、FinFETM1が溶解する場合がある。
従って、サージ電流が集中しても、溶解することなく、ESD保護素子として機能させることが可能である。
次に、フォトリソグラフィ法により、SOI層13中のP型ウェル領域(図示せず)にFinFETM1〜M6のフィン15a〜15f、ドレイン電極18、ソース電極19に対応するパターンを有するレジスト膜42を形成する。
更に、シリコン酸化膜を、プラズマ窒化して誘電率を大きくする。これにより、フィン15a〜15fの側壁のシリコン酸化膜が、ゲート絶縁膜16となる(ドレイン電極18、ソース電極19の側壁膜は図示せず)。
次に、ポリシリコン膜上にハードマスクとなるシリコン窒化膜(図示せず)を形成し、シリコン窒化膜上に、フォトリソグラフィ法によりゲート電極17、ゲートコンタクトに対応するパターンを有するレジスト膜(図示せず)を形成し、レジスト膜をマスクとしてRIE法により、シリコン窒化膜をエッチングすることにより、ゲート電極17、ゲートコンタクト20に対応するパターンが転写されたシリコン窒化膜が得られる。
次に、斜め上方からn型不純物、例えば砒素(As)イオンを加速電圧10〜20keV、ドーズ量1×1013〜2×1015atoms/cm2程度イオン注入し、フィン15a〜15fのゲートG1〜G6を挟むように不純物領域を形成する。
これにより、FinFETM1〜M6のドレインD1〜D6およびS1〜S6が形成される。
FinFETM2とFinFETM3の間で、フィンの幅Wが変わる場合について説明したが、別のFinFETの間でフィンの幅Wを変えても構わない。
本実施例が実施例1と異なる点は、ゲートコンタクトをゲート電極の中央部に形成したことにある。
ゲートコンタクト52をゲート電極51の中央部に形成したことにより、ドレインコンタクト53がドレイン電極18の中央部に形成され、ソースコンタクト54がソース電極19の中央部に形成されている。
本実施例において、上記実施例1と同一の構成部分には同一符号を付してその説明は省略し、異なる部分についてのみ説明する。
本実施例が実施例1と異なる点は、ゲートコンタクトに近い方にあるFinFETのしきい値が、ゲートコンタクトから遠い方にあるFinFETのしきい値より高いことにある。
図10に示すように、フィンの幅とFinFETのしきい値との関係は、フィンの幅に応じて3つの領域、即ち領域I、領域II、領域IIIに分けられる。
フィン62a〜62fのキャリア濃度を変えるには、周知の方法により、キャリアとなる不純物イオンを、ドーズ量を調整して注入することにより行なう。
本実施例において、上記実施例3と同一の構成部分には同一符号を付してその説明は省略し、異なる部分についてのみ説明する。
本実施例が実施例3と異なる点は、ゲートコンタクトに近い方にあるFinFETを部分空乏型とし、ゲートコンタクトから遠い方にあるFinFETを完全空乏型としたことにある。
pn分離基板においてもウェル層の表面から分離層に至るまで掘り下げることにより、張り合わせ基板等と同様にFinFETを形成することができる。
ゲートコンタクト20から遠い方にあるフィンの幅は、全てW2で等しく形成されている。
11 支持体
12 絶縁層
13 SOI層
14 半導体基板
15a〜15f、55a〜55f、62a〜62f、72a〜72f フィン
16 ゲート絶縁膜
17、81a〜81d ゲート電極
18 ドレイン電極
19 ソース電極
20 ゲートコンタクト
21、23 ワイヤ
22 ドレインコンタクト
24 ソースコンタクト
30 半導体装置(LSI)
31 内部回路
32 入出力端子
41 シリコン窒化膜
42 レジスト膜
43 側壁膜
81 マルチフィンガーゲート電極
82 直列回路
G1〜G6 ゲート
D1〜D6、84、86 ドレイン
S1〜S6、83、85、87 ソース
M1〜M6、M1a〜M1d FinFET
Claims (5)
- 半導体層からなる複数のフィンと、
前記複数のフィンの側面上にゲート絶縁膜を介して設けられたゲートが、互いに電気的に接続されたゲート電極と、
前記ゲート電極を挟むように、前記複数のフィン内に設けられたソースおよびドレインと、
前記複数のソースを電気的に接続するソース電極と、
前記複数のドレインを電気的に接続するドレイン電極と、
前記ゲート電極に外部から電気を供給するためのゲートコンタクトと、
を備え、
前記複数のフィンのうち、前記ゲートコンタクトとの距離が小さい方にある前記フィンの幅が、前記ゲートコンタクトとの距離が大きい方にある前記フィンの幅よりも大きいことを特徴とする半導体装置。 - 前記複数のフィンのうち、前記ゲートコンタクトとの距離が一番小さい前記フィンの幅が、前記ゲートコンタクトとの距離が大きい方にある前記フィンの幅よりも大きいことを特徴とする半導体装置。
- 半導体層からなる複数のフィンと、
前記複数のフィンの側面上にゲート絶縁膜を介して設けられたゲートが、互いに電気的に接続されたゲート電極と、
前記ゲート電極を挟むように、前記複数のフィン内に設けられたソースおよびドレインと、
前記複数のソースを電気的に接続するソース電極と、
前記複数のドレインを電気的に接続するドレイン電極と、
前記ゲート電極に外部から電気を供給するためのゲートコンタクトと、
を備え、
前記複数のフィンに形成されたトランジスタのうち、前記ゲートコンタクトとの距離が小さい方にある前記トランジスタのしきい値が、前記ゲートコンタクトとの距離が大きい方にある前記トランジスタのしきい値よりも高いことを特徴とする半導体装置。 - 前記複数のフィンに形成されたトランジスタのうち、前記ゲートコンタクトとの距離が一番小さい前記トランジスタのしきい値が、前記ゲートコンタクトとの距離が大きい方にある前記トランジスタのしきい値よりも高いことを特徴とする請求項3に記載の半導体装置。
- 前記複数のフィンのうち、前記ゲートコンタクトとの距離が一番小さい前記フィンの幅が、前記ゲートコンタクトとの距離が大きい方にある前記フィンの幅よりも大きいことを特徴とする請求項3または請求項4に記載の半導体装置。
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Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2009260029A (ja) * | 2008-04-16 | 2009-11-05 | Sony Corp | 半導体装置、および、その製造方法 |
JP2016048761A (ja) * | 2014-08-28 | 2016-04-07 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
JP2018060592A (ja) * | 2017-12-25 | 2018-04-12 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
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US10102899B2 (en) | 2015-03-31 | 2018-10-16 | Renesas Electronics Corporation | Semiconductor device |
WO2019012839A1 (ja) * | 2017-07-12 | 2019-01-17 | ソニーセミコンダクタソリューションズ株式会社 | トランジスタ及び電子機器 |
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Families Citing this family (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2010225768A (ja) * | 2009-03-23 | 2010-10-07 | Toshiba Corp | 半導体装置 |
US8659072B2 (en) * | 2010-09-24 | 2014-02-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Series FinFET implementation schemes |
US8664729B2 (en) * | 2011-12-14 | 2014-03-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods and apparatus for reduced gate resistance finFET |
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Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001189429A (ja) * | 1999-10-20 | 2001-07-10 | Seiko Epson Corp | 半導体装置およびその製造方法並びに半導体集積回路装置 |
JP2004088101A (ja) * | 2002-08-26 | 2004-03-18 | Internatl Business Mach Corp <Ibm> | 集積回路チップおよびその製造方法 |
JP2007053316A (ja) * | 2005-08-19 | 2007-03-01 | Toshiba Corp | Esd保護素子 |
WO2007063988A1 (ja) * | 2005-12-02 | 2007-06-07 | Nec Corporation | 半導体装置およびその製造方法 |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5892262A (en) * | 1996-06-03 | 1999-04-06 | Winbond Electronics Corp. | Capacitor-triggered electrostatic discharge protection circuit |
US6633063B2 (en) * | 2001-05-04 | 2003-10-14 | Semiconductor Components Industries Llc | Low voltage transient voltage suppressor and method of making |
US20030202307A1 (en) | 2002-04-26 | 2003-10-30 | Kei-Kang Hung | Semiconductor device with ESD protection |
US7214991B2 (en) * | 2002-12-06 | 2007-05-08 | Taiwan Semiconductor Manufacturing Co., Ltd. | CMOS inverters configured using multiple-gate transistors |
DE102005022763B4 (de) * | 2005-05-18 | 2018-02-01 | Infineon Technologies Ag | Elektronische Schaltkreis-Anordnung und Verfahren zum Herstellen eines elektronischen Schaltkreises |
DE102005039365B4 (de) | 2005-08-19 | 2022-02-10 | Infineon Technologies Ag | Gate-gesteuertes Fin-Widerstandselement, welches als pinch - resistor arbeitet, zur Verwendung als ESD-Schutzelement in einem elektrischen Schaltkreis und Einrichtung zum Schutz vor elektrostatischen Entladungen in einem elektrischen Schaltkreis |
JP2007116049A (ja) | 2005-10-24 | 2007-05-10 | Toshiba Corp | 半導体装置 |
-
2007
- 2007-12-26 JP JP2007334738A patent/JP5086797B2/ja active Active
-
2008
- 2008-12-22 US US12/341,906 patent/US8823101B2/en active Active
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001189429A (ja) * | 1999-10-20 | 2001-07-10 | Seiko Epson Corp | 半導体装置およびその製造方法並びに半導体集積回路装置 |
JP2004088101A (ja) * | 2002-08-26 | 2004-03-18 | Internatl Business Mach Corp <Ibm> | 集積回路チップおよびその製造方法 |
JP2007053316A (ja) * | 2005-08-19 | 2007-03-01 | Toshiba Corp | Esd保護素子 |
WO2007063988A1 (ja) * | 2005-12-02 | 2007-06-07 | Nec Corporation | 半導体装置およびその製造方法 |
Cited By (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2009260029A (ja) * | 2008-04-16 | 2009-11-05 | Sony Corp | 半導体装置、および、その製造方法 |
JP4518180B2 (ja) * | 2008-04-16 | 2010-08-04 | ソニー株式会社 | 半導体装置、および、その製造方法 |
US7888751B2 (en) | 2008-04-16 | 2011-02-15 | Sony Corporation | Semiconductor device having a fin field effect transistor |
JP2016048761A (ja) * | 2014-08-28 | 2016-04-07 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
US10102899B2 (en) | 2015-03-31 | 2018-10-16 | Renesas Electronics Corporation | Semiconductor device |
US10453519B2 (en) | 2015-03-31 | 2019-10-22 | Renesas Electronics Corporation | Semiconductor device |
WO2019012839A1 (ja) * | 2017-07-12 | 2019-01-17 | ソニーセミコンダクタソリューションズ株式会社 | トランジスタ及び電子機器 |
JPWO2019012839A1 (ja) * | 2017-07-12 | 2020-05-07 | ソニーセミコンダクタソリューションズ株式会社 | トランジスタ及び電子機器 |
JP7071359B2 (ja) | 2017-07-12 | 2022-05-18 | ソニーセミコンダクタソリューションズ株式会社 | トランジスタ及び電子機器 |
US11476350B2 (en) | 2017-07-12 | 2022-10-18 | Sony Semiconductor Solutions Corporation | Transistor and electronic device |
WO2019031316A1 (ja) * | 2017-08-07 | 2019-02-14 | パナソニック・タワージャズセミコンダクター株式会社 | 半導体装置 |
JPWO2019031316A1 (ja) * | 2017-08-07 | 2020-07-09 | パナソニック・タワージャズセミコンダクター株式会社 | 半導体装置 |
US11217604B2 (en) | 2017-08-07 | 2022-01-04 | Tower Partners Semiconductor Co., Ltd. | Semiconductor device |
JP2018060592A (ja) * | 2017-12-25 | 2018-04-12 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
JP2018129544A (ja) * | 2018-04-24 | 2018-08-16 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
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