JP2008277696A - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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Abstract
【解決手段】半導体装置の製造方法は、半導体基板1上に、キャップ膜14を形成し、少なくとも前記半導体基板1の端部の上面1g上、ベベル面1c、1d上および側面1e上のキャップ膜14を選択的に除去し、少なくとも半導体基板1の端部の上面1g、ベベル面1c、1dおよび側面1eに形成された素子形成膜1bを選択的に除去し、素子形成膜1bを除去した後、0.1m秒〜100m秒のパルス幅の光を半導体基板1に照射することにより、半導体基板1を加熱処理することを含み、キャップ膜14は、光のピーク波長に対する反射率が半導体基板1よりも低い。
【選択図】図3I
Description
半導体基板を加熱処理する工程を含む半導体装置の製造方法において、
前記半導体基板上に、キャップ膜を形成し、
少なくとも前記半導体基板の端部の上面上、前記半導体基板の端部のベベル面上および前記半導体基板の端部の側面上の前記キャップ膜を選択的に除去し、
少なくとも前記半導体基板の端部の上面、前記半導体基板の端部のベベル面および前記半導体基板の端部の側面に形成された素子形成膜を選択的に除去し、
前記素子形成膜を除去した後、0.1m秒〜100m秒のパルス幅の光を前記半導体基板に照射することにより、前記半導体基板を加熱処理することを含み、
前記キャップ膜は、前記光のピーク波長に対する反射率が前記半導体基板よりも低いことを特徴とする。
前記ゲート絶縁膜上にゲート電極を形成し、
前記ゲート電極をマスクとして、前記半導体基板に不純物イオンを注入し、
前記ゲート電極および前記半導体基板の表面に、キャップ膜を形成し、
少なくとも前記半導体基板の端部の上面上、前記半導体基板の端部のベベル面上および前記半導体基板の端部の側面上の前記キャップ膜を選択的に除去し、
少なくとも前記半導体基板の端部の上面、前記半導体基板の端部のベベル面および前記半導体基板の端部の側面に形成された素子形成膜を選択的に除去し、
前記素子形成膜を除去した後、0.1m秒〜100m秒のパルス幅の光を前記半導体基板に照射することにより、前記半導体基板を加熱処理することを含み、
前記キャップ膜は、前記光のピーク波長に対する反射率が前記半導体基板よりも低いことを特徴とする。
の拡散長を5nm以下に抑制して、浅いpn接合の形成が可能になる。
ソース・ドレインエクステンションイオン注入→RTA→キャップ膜成膜→ベベル近傍のキャップ膜および素子形成膜をエッチング→高速昇降温アニール(フラッシュランプアニールまたはレーザアニール)
[比較例1]
ソース・ドレインエクステンションイオン注入→RTA→高速昇降温アニール(フラッシュランプアニールまたはレーザアニール)
[比較例2]
ソース・ドレインエクステンションイオン注入→RTA→キャップ膜成膜→高速昇降温アニール(フラッシュランプアニールまたはレーザアニール)
以上の実施例1、比較例1、2に示す製造方法により半導体装置を製造した。
高速昇降温アニール工程前に、FLA前工程に専用のベベル研磨機を使用し、ベベル近傍のキャップ膜および素子形成膜を含む積層膜を除去する。
高速昇降温アニール工程前に、下面スピンエッチャーを適用し、上面側にもベベルよりやや内側まで薬液を浸透させることで、上面ベベル近傍のキャップ膜および素子形成膜を含む積層膜をエッチングする。
高速昇降温アニール工程前に、リソグフィ工程において半導体基板の端部のベベル近傍のみをレジスト開口し、ドライ洗浄技術にてベベル近傍のキャップ膜および素子形成膜を含む積層膜を選択的にエッチング除去する。
高速昇降温アニール工程前の成膜工程において、エッジカットリングを用いることで、ベベル近傍のキャップ膜および素子形成膜を堆積させない。
1a 素子形成領域
1b 素子形成膜
1c、1d ベベル面
1e 側面
1f 下面
1g 上面
1h 境界
2 pウェル層
3 nウェル層
4 素子分離領域(STI)
5a、5b ゲート絶縁膜
6a、6b ゲート電極
7a、7b 側壁スペーサ
8 n+型のソース・ドレイン領域
9 p+型のソース・ドレイン領域
10、11 不純物注入層
12 n型のエクステンション領域(拡散層)
13 p型のエクステンション領域(拡散層)
14 キャップ膜
15 第1の絶縁膜
16 第2の絶縁膜
17a、17b 側壁スペーサ
100 加熱処理装置
101 処理室
102 サセプタ
103 導入配管
104 排気配管
105 透明窓
106 光源
106a 光
107 加熱源
108 ガス供給系
109 電源
Claims (5)
- 半導体基板を加熱処理する工程を含む半導体装置の製造方法において、
前記半導体基板上に、キャップ膜を形成し、
少なくとも前記半導体基板の端部の上面上、前記半導体基板の端部のベベル面上および前記半導体基板の端部の側面上の前記キャップ膜を選択的に除去し、
少なくとも前記半導体基板の端部の上面、前記半導体基板の端部のベベル面および前記半導体基板の端部の側面に形成された素子形成膜を選択的に除去し、
前記素子形成膜を除去した後、0.1m秒〜100m秒のパルス幅の光を前記半導体基板に照射することにより、前記半導体基板を加熱処理することを含み、
前記キャップ膜は、前記光のピーク波長に対する反射率が前記半導体基板よりも低いことを特徴とする半導体装置の製造方法。 - 前記光源は、フラッシュランプ、または、レーザであることを特徴とする請求項1に半導体装置の製造方法。
- 前記キャップ膜は、少なくとも半導体基板の素子が形成される素子領域を被覆するように選択的に除去されることを特徴とする請求項1または2に記載の半導体装置の製造方法。
- 前記半導体基板の前記端部の上面とベベル面との境界から3mmの範囲に対して、前記端部の上面の前記素子形成膜を除去することを特徴とする請求項1ないし3の何れかに記載の半導体装置の製造方法。
- 半導体基板上にゲート絶縁膜を形成し、
前記ゲート絶縁膜上にゲート電極を形成し、
前記ゲート電極をマスクとして、前記半導体基板に不純物イオンを注入し、
前記ゲート電極および前記半導体基板の表面に、キャップ膜を形成し、
少なくとも前記半導体基板の端部の上面上、前記半導体基板の端部のベベル面上および前記半導体基板の端部の側面上の前記キャップ膜を選択的に除去し、
少なくとも前記半導体基板の端部の上面、前記半導体基板の端部のベベル面および前記半導体基板の端部の側面に形成された素子形成膜を選択的に除去し、
前記素子形成膜を除去した後、0.1m秒〜100m秒のパルス幅の光を前記半導体基板に照射することにより、前記半導体基板を加熱処理することを含み、
前記キャップ膜は、前記光のピーク波長に対する反射率が前記半導体基板よりも低いことを特徴とする半導体装置の製造方法。
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JP5297323B2 (ja) * | 2009-09-30 | 2013-09-25 | 株式会社東芝 | 半導体装置の製造方法 |
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JP2013026345A (ja) * | 2011-07-19 | 2013-02-04 | Toshiba Corp | 半導体装置の製造方法 |
KR101829676B1 (ko) * | 2011-12-29 | 2018-02-20 | 삼성전자주식회사 | 웨이퍼 열 처리 방법 |
CN103928290B (zh) * | 2013-01-11 | 2016-08-10 | 中芯国际集成电路制造(上海)有限公司 | 晶圆边缘的刻蚀方法 |
JP6756125B2 (ja) * | 2016-03-16 | 2020-09-16 | 富士電機株式会社 | 半導体装置および半導体装置の製造方法 |
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