JP2008244382A - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- JP2008244382A JP2008244382A JP2007086385A JP2007086385A JP2008244382A JP 2008244382 A JP2008244382 A JP 2008244382A JP 2007086385 A JP2007086385 A JP 2007086385A JP 2007086385 A JP2007086385 A JP 2007086385A JP 2008244382 A JP2008244382 A JP 2008244382A
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- Prior art keywords
- directional coupler
- semiconductor device
- output
- semiconductor
- wiring
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Abstract
【解決手段】RFパワーモジュールの増幅部が形成される半導体チップの内部に方向性結合器を形成する。半導体チップの増幅部となるLDMOSFETのドレイン領域に接続するドレイン配線35cと同層に方向性結合器の副線路32を形成する。これにより、所定のドレイン配線35cを主線路とし、この主線路に絶縁膜を介して平行に配置された副線路32で方向性結合器を構成する。
【選択図】図8
Description
図1は、例えばデジタル携帯電話機における信号送受信部のブロック図を示したものである。図1において、携帯電話機における信号送受信部は、デジタル信号処理部1、IF(Intermediate Frequency)部2、変調信号源3、ミキサ4、RFパワーモジュール5、アンテナスイッチ6、アンテナ7、低雑音増幅器8を有している。
前記実施の形態1では、ドレイン配線35cと同層で方向性結合器の副線路32を形成する例について説明したが、本実施の形態2ではドレイン配線35cの上層に方向性結合器の副線路32を形成する例について説明する。
前記実施の形態2では1本のドレイン配線35cを主線路とし、この主線路の上層に副線路32を設けることにより方向性結合器を構成する例について説明したが、本実施の形態3では、複数のドレイン配線35cを主線路とし、この複数のドレイン配線35c上に副線路32を設ける例について説明する。
前記実施の形態1では、図5に示すように、RFパワーモジュールを構成する実装基板10上に1つの半導体チップ11を搭載する例について説明したが、本実施の形態4では別の形態について説明する。つまり、前記実施の形態1では、図2に示す増幅回路13aa、13b、バンド切換スイッチ18、19および差動増幅器20が1つの半導体チップ11に形成されているが、例えば、本実施の形態4では、図2に示す増幅回路13a、13b、バンド切換スイッチ18、19および差動増幅器20を図24に示すように実装基板10上の2つの半導体チップ11a、11bに分けて形成している。例えば、図24では、図2に示す増幅部14a、14bが半導体チップ11aに形成されており、図2に示すバイアス回路15a、15bなどの増幅部14a、14bを制御する制御回路が半導体チップ11bに形成されている。このような構成をとる場合、図2に示す方向性結合器16a、16bは、半導体チップ11aに形成することが望ましい。半導体チップ11aには、電力を増幅する増幅部14a、14bが形成されており、この増幅部14a、14bで増幅された電力を検出する機能を方向性結合器16a、16bが有しているからである。つまり、半導体チップ11bに方向性結合器16a、16bを形成する場合、半導体チップ11aに形成されている増幅部14a、14bからの出力を半導体チップ11bに引き回す必要があり構成が複雑となるからである。なお、図2に示す検波回路17a、17bは、半導体チップ11a、11bのいずれに形成してもよい。このように増幅部14a、14bと制御回路(バイアス回路15a、15bなど)を別々の半導体チップ11a、11bに形成する場合も方向性結合器16a、16bを半導体チップ11aの内部に形成することで、実装基板10の小型化を達成することができる。
本実施の形態5では、前記実施の形態4で説明した図24のレイアウト構成でRFパワーモジュールが形成されている一例について説明する。図24では、実装基板10上に半導体チップ11aと半導体チップ11bが搭載されており、半導体チップ11aには、図2に示す増幅部14a、14bおよび方向性結合器16a、16bが形成され、半導体チップ11bには、図2に示すバイアス回路15a、15bなどの制御回路が形成されている。特に、本実施の形態5では、図2に示す検波回路17a、17bも半導体チップ11bに搭載されている例について説明する。本実施の形態5では、半導体チップ11aはGaAs基板などの化合物半導体基板(半絶縁性基板)から構成され、半導体チップ11bは、シリコン基板から構成されている。
2 IF部
3 変調信号源
4 ミキサ
5 RFパワーモジュール
6 アンテナスイッチ
7 アンテナ
8 低雑音増幅器
10 実装基板
11 半導体チップ
11a〜11h 半導体チップ
12a 整合回路
12b 整合回路
13a 増幅回路
13b 増幅回路
14a 増幅部
14b 増幅部
15a バイアス回路
15b バイアス回路
16a 方向性結合器
16b 方向性結合器
17a 検波回路
17b 検波回路
18 バンド切換スイッチ
19 バンド切換スイッチ
20 差動増幅器
21 nチャネル型MOSFET
22 pチャネル型MOSFET
23 pチャネル型MOSFET
24 nチャネル型MOSFET
25a 初段増幅部
25b 初段増幅部
26a 中段増幅部
26b 中段増幅部
27a 終段増幅部
27b 終段増幅部
28 容量素子
29 抵抗素子
30 制御回路
31 検波回路
32 副線路
33 パッド
34 パッド
35a ドレイン配線
35b ドレイン配線
35c ドレイン配線
36a ソース配線
36b ソース配線
36c ソース配線
37 ゲート配線
40 半導体基板
41 p型エピタキシャル層
42 溝
43 p型打ち抜き層
44 p型ウェル
45 ゲート絶縁膜
46 ゲート電極
47 n−型オフセットドレイン領域
48 n−型ソース領域
49 サイドウォール
50 n型オフセットドレイン領域
51 n+型ドレイン領域
52 n+型ソース領域
53 p+型半導体領域
54 酸化シリコン膜
55 コンタクトホール
56a チタン/窒化チタン膜
56b タングステン膜
57 プラグ
58 酸化シリコン膜
59 スルーホール
60a チタン/窒化チタン膜
60b タングステン膜
61 プラグ
62 酸化シリコン膜
63 スルーホール
64a チタン/窒化チタン膜
64b タングステン膜
65 プラグ
66 酸化シリコン膜
67 窒化シリコン膜
68 裏面電極
69 酸化シリコン膜
70 酸化シリコン膜
71 パッド
72 素子分離領域
73 エミッタ配線
74 ベース配線
75 コレクタ配線
76 コレクタ引き出し配線
77 副線路
80 GaAs基板
81 サブコレクタ用半導体層
82 コレクタ用半導体層
83 ベース用半導体層
84 エミッタ用半導体層
85 GaAs層
86 エミッタ電極
87 ベース電極
88 コレクタ電極
89 絶縁膜
90 絶縁膜
91 裏面電極
100 実装基板
101 半導体チップ
102 方向性結合器
Pin1 端子
Pin2 端子
Pout1 端子
Pout2 端子
Vapc 端子
Claims (18)
- 電力増幅回路を含む半導体チップを備え、前記半導体チップは、
(a)半導体基板と、
(b)前記半導体基板上に形成された前記電力増幅回路を構成するトランジスタと、
(c)前記電力増幅回路から出力される出力電力を検出する方向性結合器とを有し、
前記方向性結合器は、
(c1)前記トランジスタの出力配線を用いた主線路と、
(c2)前記方向性結合器からの出力を電圧あるいは電流に変換する検波回路と第1端子が電気的に接続され、前記第1端子の他端である第2端子が受動素子を介してGNDと電気的に接続された副線路とを含み、
前記主線路と前記副線路とは平行に配置され、かつ、前記主線路と前記副線路との間に導電体が存在しないことを特徴とする半導体装置。 - 請求項1記載の半導体装置であって、
前記半導体チップは、前記方向性結合器からの出力を電圧あるいは電流に変換する前記検波回路を有していることを特徴とする半導体装置。 - 請求項2記載の半導体装置であって、
前記半導体チップは、前記方向性結合器からの出力を電圧あるいは電流に変換する前記検波回路と、
前記検波回路の出力に基づいて前記電力増幅回路からの出力電力が一定となるように前記電力増幅回路を構成する前記トランジスタを制御する制御回路とを有していることを特徴とする半導体装置。 - 請求項1記載の半導体装置であって、
前記主線路と前記副線路とは同一配線層で形成されていることを特徴とする半導体装置。 - 請求項1記載の半導体装置であって、
前記トランジスタに接続されているソース配線の一部を省略し、前記ソース配線の一部を省略することにより空いた領域に前記副線路を配置することを特徴とする半導体装置。 - 請求項1記載の半導体装置であって、
前記主線路が形成されている配線層の上層に位置する配線層に前記副線路が形成されていることを特徴とする半導体装置。 - 請求項1記載の半導体装置であって、
前記トランジスタは、電界効果トランジスタであることを特徴とする半導体装置。 - 請求項1記載の半導体装置であって、
前記トランジスタは、バイポーラトランジスタであることを特徴とする半導体装置。 - 請求項1記載の半導体装置であって、
前記主線路と前記副線路との間には絶縁膜が形成されていることを特徴とする半導体装置。 - 請求項9記載の半導体装置であって、
前記主線路と前記副線路との間の距離は2μm以下であることを特徴とする半導体装置。 - 請求項2記載の半導体装置であって、
前記方向性結合器と前記検波回路との間に前記方向性結合器からの出力を増幅する線形増幅器が接続されていることを特徴とする半導体装置。 - 電力増幅回路を含む半導体チップを備え、前記半導体チップは、
(a)半導体基板と、
(b)前記半導体基板上に形成された前記電力増幅回路を構成するトランジスタと、
(c)前記電力増幅回路から出力される出力電力を検出する方向性結合器とを有し、
前記方向性結合器は、
(c1)前記トランジスタの出力配線を用いた主線路と、
(c2)前記方向性結合器からの出力を電圧あるいは電流に変換する検波回路と接続される副線路とを含むことを特徴とする半導体装置。 - 請求項12記載の半導体装置であって、
前記半導体チップは、前記方向性結合器からの出力を電圧あるいは電流に変換する検波回路を有していることを特徴とする半導体装置。 - 請求項12記載の半導体装置であって、
前記半導体チップは、前記方向性結合器からの出力を電圧あるいは電流に変換する前記検波回路と、
前記検波回路の出力に基づいて前記電力増幅回路からの出力電力が一定となるように前記電力増幅回路を構成する前記トランジスタを制御する制御回路とを有していることを特徴とする半導体装置。 - 電力増幅機能を有する半導体装置であって、
(a)実装基板と、
(b)前記実装基板上に搭載され、電力増幅回路が形成された第1半導体チップとを備え、
前記第1半導体チップは、
(c)半導体基板と、
(d)前記半導体基板上に形成された前記電力増幅回路を構成するトランジスタと、
(e)前記電力増幅回路から出力される出力電力を検出する方向性結合器とを有し、
前記方向性結合器は、
(e1)前記トランジスタの出力配線を用いた主線路と、
(e2)前記方向性結合器からの出力を電圧あるいは電流に変換する検波回路と接続される副線路とを含むことを特徴とする半導体装置。 - 請求項15記載の半導体装置であって、
前記第1半導体チップは、前記方向性結合器からの出力を電圧あるいは電流に変換する前記検波回路と、
前記検波回路の出力に基づいて前記電力増幅回路からの出力電力が一定となるように前記電力増幅回路を構成する前記トランジスタを制御する制御回路とを有していることを特徴とする半導体装置。 - 請求項15記載の半導体装置であって、
前記実装基板上には、さらに、第2半導体チップが搭載されており、
前記第2半導体チップには、前記方向性結合器からの出力を電圧あるいは電流に変換する前記検波回路と、
前記検波回路の出力に基づいて前記電力増幅回路からの出力電力が一定となるように前記電力増幅回路を構成する前記トランジスタを制御する制御回路が形成されていることを特徴とする半導体装置。 - 請求項17記載の半導体装置であって、
前記第1半導体チップは化合物半導体基板から形成され、前記第2半導体チップはシリコン基板から形成されていることを特徴とする半導体装置。
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JP2007086385A JP5175482B2 (ja) | 2007-03-29 | 2007-03-29 | 半導体装置 |
US11/964,217 US8334580B2 (en) | 2007-03-29 | 2007-12-26 | Semiconductor chip comprising a directional coupler having a specific main line and sub-line arrangement |
TW097101793A TW200845362A (en) | 2007-03-29 | 2008-01-17 | Semiconductor device |
CN201210441006.3A CN102945848B (zh) | 2007-03-29 | 2008-02-01 | 半导体器件 |
CN2008100094094A CN101276815B (zh) | 2007-03-29 | 2008-02-01 | 半导体器件 |
KR1020080028476A KR101456712B1 (ko) | 2007-03-29 | 2008-03-27 | 반도체 장치 |
US13/666,248 US8426941B2 (en) | 2007-03-29 | 2012-11-01 | Semiconductor chip comprising a directional coupler having a specific main line and sub-line arrangement |
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CN (2) | CN102945848B (ja) |
TW (1) | TW200845362A (ja) |
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Also Published As
Publication number | Publication date |
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JP5175482B2 (ja) | 2013-04-03 |
CN102945848B (zh) | 2015-06-17 |
TW200845362A (en) | 2008-11-16 |
US8334580B2 (en) | 2012-12-18 |
CN101276815B (zh) | 2012-12-26 |
US8426941B2 (en) | 2013-04-23 |
US20080237736A1 (en) | 2008-10-02 |
CN101276815A (zh) | 2008-10-01 |
CN102945848A (zh) | 2013-02-27 |
KR20080088466A (ko) | 2008-10-02 |
KR101456712B1 (ko) | 2014-10-31 |
US20130056730A1 (en) | 2013-03-07 |
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