JP2008211119A - 半導体装置の製造方法 - Google Patents
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- 239000011800 void material Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
- H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/482—Bit lines
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/488—Word lines
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
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Abstract
【解決手段】上面及び側面が酸化シリコン膜で覆われた配線105bを形成した後、配線を覆って全面にシリコンを含有しない有機塗布膜からなる犠牲層間膜132aを形成し、犠牲層間膜および下層絶縁膜を順次にエッチングしてコンタクトホール108を形成し、コンタクトプラグを形成する。その後、犠牲層間膜を除去してコンタクトプラグの柱を形成し、その上に層間絶縁膜106を形成し、さらに層間絶縁膜を表面から一部除去し、容量コンタクトプラグの表面を露出させるようにした。
【選択図】図5
Description
101a 活性領域
102 素子分離領域
103 ドレイン
104 ソース
105 ワード配線
105a ゲート絶縁膜
105b ゲート電極
105c、105e 保護絶縁膜
105d、105f、111c サイドウォール
106 第1層間絶縁膜
107、108 コンタクトホール
107a、108a コンタクトプラグ
109 第2層間絶縁膜
110 ビット配線コンタクトプラグ
110a 第2コンタクトプラグ
111 ビット配線
111a タングステン膜
111b 酸化シリコン膜
112 第3層間絶縁膜
113 容量コンタクトプラグ
113a 容量コンタクトホール
114 第4層間絶縁膜
115 キャパシタの下部電極
116 容量絶縁膜
117 上部電極
118 第5層間絶縁膜
119 配線層
130、133 ハードマスク
131 ホトレジストパターン
132a、132b 有機塗布膜
134 バリヤ層
134a シリコン膜
134b チタン膜
134c 窒化チタン膜
134d チタンシリサイド膜
135 タングステン膜
136 タングステン膜
137 酸化シリコン膜
Claims (11)
- (1)半導体基板上に有機塗布膜を形成する工程と、
(2)前記有機塗布膜にコンタクトホールを形成する工程と、
(3)前記コンタクトホール内にコンタクトプラグを形成する工程と、
(4)前記有機塗布膜を選択的に除去して、前記コンタクトプラグの側壁の少なくとも一部を露出させる工程と、
(5)全面に無機絶縁膜を形成し、前記コンタクトプラグを埋め込む工程と、
(6)前記無機絶縁膜の表面を研磨し、前記コンタクトプラグの表面を露出させる工程と、
を上記の順に少なくとも含むことを特徴とする半導体装置の製造方法。 - 請求項1において、前記有機塗布膜は、シリコンを含有しない有機塗布膜であることを特徴とする半導体装置の製造方法。
- 請求項1において、前記有機塗布膜を形成する工程の前に、前記半導体基板上には配線からなる段差が形成されていることを特徴とする半導体装置の製造方法。
- 請求項3において、前記配線は、ダイナミックランダムアクセスメモリのワード配線であることを特徴とする半導体装置の製造方法。
- 請求項3において、前記配線は、ダイナミックランダムアクセスメモリのビット配線であることを特徴とする半導体装置の製造方法。
- 請求項1において、前記コンタクトプラグは、該コンタクトプラグの下に位置する半導体基板もしくは導体プラグに接続されることを特徴とする半導体装置の製造方法。
- 請求項6において、前記コンタクトプラグは、下層のバリヤ層および上層の金属膜で形成されることを特徴とする半導体装置の製造方法。
- 請求項7において、前記バリヤ層は、シリコン膜、金属膜、金属シリサイド膜、金属窒化物膜から選択される材料で形成されることを特徴とする半導体装置の製造方法。
- 請求項7において、前記コンタクトプラグを形成する工程は、前記有機塗布膜にコンタクトホールを形成した後、
(1)シリコン膜を全面に形成する工程と、
(2)前記シリコン膜を形成した後、第1の金属膜および金属窒化物膜を全面に形成する工程と、
(3)前記第1の金属膜および金属窒化物膜を全面に形成した後、前記コンタクトホールを埋め込むように、全面に第2の金属膜を形成する工程と、
(4)前記有機塗布膜上に形成された前記シリコン膜、前記第1の金属膜および金属窒化物膜、前記第2の金属膜を除去し、前記有機塗布膜の表面を露出させる工程と、
(5)表面が露出した前記有機塗布膜を選択的に除去する工程と、
(6)熱処理により、前記シリコン膜と前記第1の金属膜を反応させ、金属シリサイド膜を形成する工程と、
を、上記の順に少なくとも含むことを特徴とする半導体装置の製造方法。 - (1)半導体基板上に複数のワード配線を形成し、前記ワード配線を覆って全面に回転塗布法により有機塗布膜を形成する工程と、
(2)前記有機塗布膜上にハードマスクを形成する工程と、
(3)前記ハードマスク上にホトレジストのホールパターンを形成する工程と、
(4)前記ホールパターンを前記ハードマスクに転写する工程と、
(5)前記ハードマスクを用いて、アンモニアもしくは酸素プラズマにより前記有機塗布膜をドライエッチングし、前記半導体基板上にコンタクトホールを形成する工程と、
(6)前記コンタクトホール内面を覆うように、全面に、シリコン膜、第1の金属膜および金属窒化物膜からなるバリヤ層を形成する工程と、
(7)前記コンタクトホール内を埋めるように、全面に第2の金属膜を形成する工程と、
(8)前記有機塗布膜の表面に形成された、前記バリヤ層および第2の金属膜を除去してコンタクトプラグを形成すると同時に前記有機塗布膜の表面を露出させる工程と、
(9)前記表面が露出した有機塗布膜を、アンモニアもしくは酸素プラズマによるドライエッチングで除去し、前記コンタクトプラグの柱を形成する工程と、
(10)前記コンタクトプラグの柱を覆うように、全面に無機絶縁膜を形成する工程と、
(11)前記無機絶縁膜を表面から研磨し、前記コンタクトプラグの表面を露出させる工程と、
を上記の順に少なくとも含むことを特徴とする半導体装置の製造方法。 - 請求項10において、前記工程(9)以降の工程で熱処理し、前記シリコン膜と前記第1の金属膜を反応させて、少なくとも前記金属窒化物膜と前記半導体基板の間に金属シリサイド膜を形成する工程をさらに含むことを特徴とする半導体装置の製造方法。
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JP2007048515A JP4437301B2 (ja) | 2007-02-28 | 2007-02-28 | 半導体装置の製造方法 |
US12/037,118 US7592249B2 (en) | 2007-02-28 | 2008-02-26 | Method for manufacturing a semiconductor device |
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
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JP2014505369A (ja) * | 2011-02-01 | 2014-02-27 | エーエスエムエル ネザーランズ ビー.ブイ. | 基板テーブル、リソグラフィ装置、およびデバイス製造方法 |
CN113224058A (zh) * | 2021-04-07 | 2021-08-06 | 芯盟科技有限公司 | 半导体结构及半导体结构的形成方法 |
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US8283259B2 (en) * | 2010-08-31 | 2012-10-09 | Micron Technology, Inc. | Methods of removing a metal nitride material |
US8551877B2 (en) * | 2012-03-07 | 2013-10-08 | Tokyo Electron Limited | Sidewall and chamfer protection during hard mask removal for interconnect patterning |
TWI649838B (zh) | 2018-04-10 | 2019-02-01 | 華邦電子股份有限公司 | 半導體裝置及其製造方法 |
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JPH1187493A (ja) | 1997-09-08 | 1999-03-30 | Hitachi Ltd | 半導体装置の製造方法 |
JP2001102550A (ja) | 1999-09-02 | 2001-04-13 | Samsung Electronics Co Ltd | 自己整合コンタクトを有する半導体メモリ装置及びその製造方法 |
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JP2014505369A (ja) * | 2011-02-01 | 2014-02-27 | エーエスエムエル ネザーランズ ビー.ブイ. | 基板テーブル、リソグラフィ装置、およびデバイス製造方法 |
US9329497B2 (en) | 2011-02-01 | 2016-05-03 | Asml Netherlands B.V. | Substrate table, lithographic apparatus and device manufacturing method |
CN113224058A (zh) * | 2021-04-07 | 2021-08-06 | 芯盟科技有限公司 | 半导体结构及半导体结构的形成方法 |
CN113224058B (zh) * | 2021-04-07 | 2023-03-10 | 芯盟科技有限公司 | 半导体结构及半导体结构的形成方法 |
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