JP2008112928A - 回路装置の製造方法 - Google Patents
回路装置の製造方法 Download PDFInfo
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
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- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
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- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
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- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
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- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
- H01L2924/13055—Insulated gate bipolar transistor [IGBT]
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- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
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- H01L2924/181—Encapsulation
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- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
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Abstract
【解決手段】本発明の回路装置の製造方法では、モールド用の金型22の上金型22Aに第2側面28を設けている。この構成により、封止樹脂14に含まれるボイド24の殆どは、エアベント30から外部に放出される。また、キャビティ23の内部にボイド24が残留したとしても、これらのボイド24の大部分は、回路素子や導電パターンが設けられない第2領域32に位置している。従って、第2領域32に位置するボイドは、回路素子と外部とのショートを誘発しないので、このボイドに起因した装置全体の耐圧の低下は抑制される。
【選択図】図5
Description
本形態では、図1および図2を参照して、回路装置の一例として混成集積回路装置10の構造を説明する。
本形態では、図3から図5を参照して、上述した構成の混成集積回路装置の製造方法を説明する。
11 回路基板
12 絶縁層
13 導電パターン
13A パッド
14 封止樹脂
15A 制御素子
15B、15C パワー素子
15D チップ素子
17 金属細線
19 回路素子
20A、20B、20C リブ
21 封止領域
22 金型
22A 上金型
22B 下金型
23 キャビティ
24 ボイド
25 リード
26 ヒートシンク
27 第1側面
28 第2側面
29 ゲート
30 エアベント
31 第1領域
32 第2領域
33 ビス穴
34 当接ピン
40 リードフレーム
Claims (4)
- 導電パターンおよび回路素子から成る混成集積回路が上面に組み込まれた回路基板の少なくとも上面および側面を、金型を用いて封止樹脂にて被覆する回路装置の製造方法であり、
前記金型には、前記回路基板が収納されるキャビティの最外周部に位置する第1側面と、前記第1側面よりも内側であり且つ前記回路素子が配置される領域よりも外側に位置する第2側面が設けられ、
前記回路基板を前記封止樹脂により被覆する工程では、前記第2側面よりも内側の領域である第1領域に前記封止樹脂を充填させた後に、前記第2側面よりも外側であり且つ前記第1側面に囲まれる第2領域に前記封止樹脂を充填させ、前記封止樹脂に含まれるボイドを前記第1領域から前記第2領域に移動させることを特徴とする回路装置の製造方法。 - 前記封止樹脂により、前記回路基板の上面、側面および下面を被覆することを特徴とする請求項1記載の回路装置の製造方法。
- 前記第2側面を前記回路基板の外周端部よりも内側に設けて、前記第1領域に注入されて前記第2領域に流入する前記封止樹脂の量を制限することを特徴とする請求項1記載の回路装置の製造方法。
- 前記回路基板は矩形形状であり、
前記第2側面は、前記回路基板の長手方向に於いて前記第1側面よりも内側に位置し、
前記第2領域は、前記回路基板の長手方向の外側に設けられることを特徴とする請求項1記載の回路装置の製造方法。
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JP2006296221A JP2008112928A (ja) | 2006-10-31 | 2006-10-31 | 回路装置の製造方法 |
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JP2006296221A JP2008112928A (ja) | 2006-10-31 | 2006-10-31 | 回路装置の製造方法 |
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2012134430A (ja) * | 2010-12-24 | 2012-07-12 | On Semiconductor Trading Ltd | 回路装置およびその製造方法 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH06333966A (ja) * | 1993-05-17 | 1994-12-02 | American Teleph & Telegr Co <Att> | 電子部品搭載基板のプラスチックカプセル内へのパッケージ方法 |
JPH11163011A (ja) * | 1997-11-26 | 1999-06-18 | Sanken Electric Co Ltd | 樹脂封止型半導体装置の製造方法 |
JP2002110721A (ja) * | 2000-10-02 | 2002-04-12 | Hitachi Ltd | 半導体装置の製造方法 |
JP2003017631A (ja) * | 2001-06-28 | 2003-01-17 | Sanyo Electric Co Ltd | 混成集積回路装置およびその製造方法 |
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- 2006-10-31 JP JP2006296221A patent/JP2008112928A/ja active Pending
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH06333966A (ja) * | 1993-05-17 | 1994-12-02 | American Teleph & Telegr Co <Att> | 電子部品搭載基板のプラスチックカプセル内へのパッケージ方法 |
JPH11163011A (ja) * | 1997-11-26 | 1999-06-18 | Sanken Electric Co Ltd | 樹脂封止型半導体装置の製造方法 |
JP2002110721A (ja) * | 2000-10-02 | 2002-04-12 | Hitachi Ltd | 半導体装置の製造方法 |
JP2003017631A (ja) * | 2001-06-28 | 2003-01-17 | Sanyo Electric Co Ltd | 混成集積回路装置およびその製造方法 |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2012134430A (ja) * | 2010-12-24 | 2012-07-12 | On Semiconductor Trading Ltd | 回路装置およびその製造方法 |
US8995139B2 (en) | 2010-12-24 | 2015-03-31 | Semiconductor Components Industries, L.L.C. | Circuit device and method of manufacturing the same |
US10332816B2 (en) | 2010-12-24 | 2019-06-25 | Semiconductor Components Industries, Llc | Circuit device and method of manufacturing the same |
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