JP2008034748A - Light-emitting apparatus - Google Patents

Light-emitting apparatus Download PDF

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JP2008034748A
JP2008034748A JP2006208840A JP2006208840A JP2008034748A JP 2008034748 A JP2008034748 A JP 2008034748A JP 2006208840 A JP2006208840 A JP 2006208840A JP 2006208840 A JP2006208840 A JP 2006208840A JP 2008034748 A JP2008034748 A JP 2008034748A
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led chip
substrate
light
mounting substrate
led
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JP5010203B2 (en
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Masanao Kamakura
將有 鎌倉
Kenichiro Tanaka
健一郎 田中
Kazuji Yoshida
和司 吉田
Masao Kirihara
昌男 桐原
Takeshi Nakasuji
威 中筋
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Panasonic Electric Works Co Ltd
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Matsushita Electric Works Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding

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  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a light-emitting apparatus capable of improving heat radiation performance. <P>SOLUTION: The light-emitting apparatus is provided with an LED chip 1, and a mounting substrate 2 formed using silicon substrates 20a, 30a, 40a as a semiconductor substrate and mounted with the LED chip 1. A plurality of through-hole wirings 24 as one part of a power feed passage to the LED chip 1, and a plurality of thermal vias 26 used as a passage for radiating the heat generated from the LED chip 1, are provided to pierce in the thickness direction of the mounting substrate 2. The cross-sectional area of each of the thermal vias 26 in a cross section orthogonal to the thickness direction is larger than the cross-sectional area of each of the through-hole wirings 24, and the mounting substrate 2 has a die pad 25aa as a heat equalizing plate joined to the overall one surface of the LED chip 1 and for thermally coupling the LED chip 1 to the thermal vias 26. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

本発明は、ＬＥＤチップ（発光ダイオードチップ）を用いた発光装置に関するものである。   The present invention relates to a light emitting device using an LED chip (light emitting diode chip).

従来から、図１５に示すように、ＬＥＤチップ１’と、シリコン基板２０ａ’を用いて形成されＬＥＤチップ１’が実装された実装基板（パッケージ）２’とを備え、ＬＥＤチップ１’への給電路の一部となる複数の貫通孔配線２４’およびＬＥＤチップ１’で発生した熱の放熱路となる複数のサーマルビア２６’が実装基板２’の厚み方向に貫設された発光装置が提案されている（例えば、特許文献１参照）。   Conventionally, as shown in FIG. 15, an LED chip 1 ′ and a mounting substrate (package) 2 ′ formed by using a silicon substrate 20 a ′ and mounted with the LED chip 1 ′ are mounted on the LED chip 1 ′. A light-emitting device in which a plurality of through-hole wirings 24 ′ serving as a part of a power feeding path and a plurality of thermal vias 26 ′ serving as a heat dissipation path for heat generated in the LED chip 1 ′ are penetrated in the thickness direction of the mounting substrate 2 ′. It has been proposed (see, for example, Patent Document 1).

ここにおいて、図１５に示した構成の発光装置は、ＬＥＤチップ１’の一表面側に形成された各電極（図示せず）がＡｕバンプ１３ａ’，１３ａ’を介して実装基板２’の導体パターン２５ａ’，２５ａ’と電気的に接続されるとともに、各導体パターン２５ａ’，２５ａ’それぞれが複数（図示例では、３つ）の貫通孔配線２４’を介して外部接続用電極２７ａ’，２７ａ’と電気的に接続されている。また、この発光装置は、実装基板２’におけるＬＥＤチップ１’との対向面にＬＥＤチップ１’のチップサイズよりも小さな放熱用金属部２１’が形成されており、ＬＥＤチップ１’と放熱用金属部２１’とが複数のＡｕバンプ１３ｃ’を介して熱結合されるとともに、放熱用金属部２１’が複数のサーマルビア２６’を介して放熱用パッド部２８’と熱結合されている。   Here, in the light emitting device having the configuration shown in FIG. 15, each electrode (not shown) formed on the one surface side of the LED chip 1 ′ has conductors of the mounting substrate 2 ′ via Au bumps 13a ′ and 13a ′. The conductor patterns 25a ′ and 25a ′ are electrically connected to the patterns 25a ′ and 25a ′, and the conductor patterns 25a ′ and 25a ′ are respectively connected to the external connection electrodes 27a ′ and the like via a plurality of (three in the illustrated example) through-hole wirings 24 ′. 27a 'is electrically connected. Further, in this light emitting device, a heat radiating metal portion 21 ′ smaller than the chip size of the LED chip 1 ′ is formed on the surface of the mounting substrate 2 ′ facing the LED chip 1 ′. The metal portion 21 ′ is thermally coupled to the heat radiating metal portion 21 ′ via the plurality of Au bumps 13c ′, and the heat radiating metal portion 21 ′ is thermally coupled to the heat radiating pad portion 28 ′ via the plurality of thermal vias 26 ′.

なお、図１５に示した構成の発光装置は、各貫通孔配線２４’および各サーマルビア２６’の形成にあたって、シリコン基板２０ａ’に貫通孔配線２４’用の貫通孔およびサーマルビア２６’用の貫通孔を同時に形成してから、熱酸化によりシリコン酸化膜からなる絶縁膜（図示せず）を形成し、その後、めっき法などによって貫通孔配線２４’とサーマルビア２６’とを同時に形成している。
特開２００５−１９６０９号公報 In the light emitting device having the configuration shown in FIG. 15, in the formation of each through hole wiring 24 ′ and each thermal via 26 ′, the through hole for the through hole wiring 24 ′ and the thermal via 26 ′ are formed in the silicon substrate 20a ′. After forming the through holes at the same time, an insulating film (not shown) made of a silicon oxide film is formed by thermal oxidation, and then the through hole wiring 24 ′ and the thermal via 26 ′ are formed simultaneously by plating or the like. Yes.
Japanese Patent Laid-Open No. 2005-19609

図１５に示した構成の発光装置では、ＬＥＤチップ１’の各電極と電気的に接続された導体パターン２５ａ’，２５ａ’が貫通孔配線２４’，２４’を介して外部接続用電極２７ａ’，２７ａ’と電気的に接続されているので、実装基板２’の平面サイズの小型化を図れるとともに、回路基板などへの実装面積を小さくすることができる。しかしながら、図１５に示した構成の発光装置では、ＬＥＤチップ１’と放熱用金属部２１’とが複数のＡｕバンプ１３ｃ’により熱結合されており、しかも、放熱用金属部２１’の平面サイズがＬＥＤチップ１’のチップサイズよりも小さいので、ＬＥＤチップ１’で発生した熱の放熱路の熱抵抗が比較的大きく、しかも、放熱用金属部２１’の平面サイズによりサーマルビア２６’の数が制限されるので、放熱性の向上が望まれていた。   In the light emitting device having the configuration shown in FIG. 15, the conductor patterns 25a ′ and 25a ′ electrically connected to the respective electrodes of the LED chip 1 ′ are connected to the external connection electrodes 27a ′ via the through-hole wirings 24 ′ and 24 ′. , 27a ′, the planar size of the mounting substrate 2 ′ can be reduced, and the mounting area on the circuit board or the like can be reduced. However, in the light emitting device having the configuration shown in FIG. 15, the LED chip 1 ′ and the heat radiating metal portion 21 ′ are thermally coupled by the plurality of Au bumps 13 c ′, and the planar size of the heat radiating metal portion 21 ′ is obtained. Is smaller than the chip size of the LED chip 1 ′, the thermal resistance of the heat dissipation path of the heat generated in the LED chip 1 ′ is relatively large, and the number of thermal vias 26 ′ depends on the planar size of the heat radiating metal portion 21 ′. Therefore, improvement in heat dissipation has been desired.

本発明は上記事由に鑑みて為されたものであり、その目的は、放熱性を高めることが可能な発光装置を提供することにある。   This invention is made | formed in view of the said reason, The objective is to provide the light-emitting device which can improve heat dissipation.

請求項１の発明は、ＬＥＤチップと、半導体基板を用いて形成されＬＥＤチップが実装された実装基板とを備え、ＬＥＤチップへの給電路の一部となる複数の貫通孔配線およびＬＥＤチップで発生した熱の放熱路となる複数のサーマルビアが実装基板の厚み方向に貫設された発光装置であって、実装基板は、前記厚み方向に直交する断面における各サーマルビアの断面積が各貫通孔配線の断面積よりも大きく、且つ、ＬＥＤチップの一面全体が接合されＬＥＤチップと複数のサーマルビアとを熱結合する均熱板部を有してなることを特徴とする。   The invention of claim 1 includes an LED chip and a mounting substrate formed using a semiconductor substrate and mounted with the LED chip, and a plurality of through-hole wirings and LED chips that are part of a power feeding path to the LED chip. A light-emitting device in which a plurality of thermal vias serving as heat dissipation paths for generated heat are provided in the thickness direction of the mounting board, and the mounting board has a cross-sectional area of each thermal via in a cross section perpendicular to the thickness direction. The cross-sectional area of the hole wiring is larger, and the whole surface of the LED chip is joined, and a heat equalizing plate portion that thermally couples the LED chip and the plurality of thermal vias is provided.

この発明によれば、実装基板は、当該実装基板の厚み方向に直交する断面における各サーマルビアの断面積が各貫通孔配線の断面積よりも大きく、且つ、ＬＥＤチップの一面全体が接合されＬＥＤチップと複数のサーマルビアとを熱結合する均熱板部を有しているので、ＬＥＤチップで発生した熱の放熱路のうちＬＥＤチップから各サーマルビアまでの間に放熱路の断面積がＬＥＤチップのチップサイズよりも小さくなる区間が存在しないことにより、熱抵抗を低減することができて放熱性を高めることが可能となり、しかも、実装基板の厚み方向に直交する断面における各サーマルビアの断面積を小さくすることなくサーマルビアの数を増やすことが可能となるから、放熱性をより一層高めることが可能となる。   According to the present invention, the mounting substrate has an LED in which the cross-sectional area of each thermal via in the cross section perpendicular to the thickness direction of the mounting substrate is larger than the cross-sectional area of each through-hole wiring, and the entire surface of the LED chip is bonded. Since it has a soaking plate part that thermally couples the chip and a plurality of thermal vias, the cross-sectional area of the heat radiation path is between the LED chip and each thermal via among the heat radiation paths generated by the LED chip. Since there is no section smaller than the chip size of the chip, it is possible to reduce the thermal resistance and increase the heat dissipation, and to cut off each thermal via in the cross section perpendicular to the thickness direction of the mounting board. Since the number of thermal vias can be increased without reducing the area, the heat dissipation can be further enhanced.

請求項２の発明は、請求項１の発明において、前記実装基板は、前記各貫通孔配線と接続される複数の導体部が前記均熱板部の周辺に形成されてなることを特徴とする。   According to a second aspect of the present invention, in the first aspect of the invention, the mounting board includes a plurality of conductor portions connected to the through-hole wirings formed around the heat equalizing plate portion. .

この発明によれば、前記実装基板の厚み方向において前記ＬＥＤチップと前記貫通孔配線とが重複している場合に比べて、前記サーマルビアの数を増やすことが可能となるから、放熱性を高めることが可能となる。   According to this invention, since it becomes possible to increase the number of the thermal vias compared to the case where the LED chip and the through-hole wiring overlap in the thickness direction of the mounting substrate, the heat dissipation is improved. It becomes possible.

請求項１の発明では、放熱性を高めることが可能になるという効果がある。   In the invention of claim 1, there is an effect that it is possible to improve the heat dissipation.

（実施形態１）
以下、本実施形態の発光装置について図１〜図１０に基づいて説明する。 (Embodiment 1)
Hereinafter, the light-emitting device of this embodiment will be described with reference to FIGS.

本実施形態の発光装置は、可視光（例えば、赤色光、緑色光、青色光など）を放射するＬＥＤチップ１と、ＬＥＤチップ１を収納する収納凹所２ａが一表面に形成され収納凹所２ａの内底面にＬＥＤチップ１が実装された実装基板２と、実装基板２の上記一表面側において収納凹所２ａを閉塞する形で実装基板２に固着された透光性部材３と、実装基板２に設けられＬＥＤチップ１から放射された光を検出する光検出素子４（図３参照）と、実装基板２の収納凹所２ａに充填された透光性の封止樹脂（例えば、シリコーン樹脂、アクリル樹脂など）からなりＬＥＤチップ１および当該ＬＥＤチップ１に接続されたボンディングワイヤ１４を封止した封止部５と備えている。ここで、実装基板２は、上記一表面側において収納凹所２ａの周部から内方へ突出した庇状の張出部２ｃを有しており、当該張出部２ｃに光検出素子４が設けられている。なお、本実施形態では、実装基板２と透光性部材３とでパッケージを構成しているが、透光性部材３は、必ずしも設けなくてもよく、必要に応じて適宜設ければよい。   In the light emitting device of this embodiment, an LED chip 1 that emits visible light (for example, red light, green light, blue light, and the like) and a storage recess 2a that stores the LED chip 1 are formed on one surface. A mounting substrate 2 on which the LED chip 1 is mounted on the inner bottom surface of 2a, a translucent member 3 fixed to the mounting substrate 2 so as to close the housing recess 2a on the one surface side of the mounting substrate 2, and a mounting A light detecting element 4 (see FIG. 3) for detecting light emitted from the LED chip 1 provided on the substrate 2 and a translucent sealing resin (for example, silicone) filled in the housing recess 2a of the mounting substrate 2 A sealing portion 5 that is made of a resin, an acrylic resin, or the like and seals the LED chip 1 and the bonding wire 14 connected to the LED chip 1. Here, the mounting substrate 2 has a hook-like protruding portion 2c protruding inward from the peripheral portion of the storage recess 2a on the one surface side, and the light detection element 4 is provided on the protruding portion 2c. Is provided. In the present embodiment, the package is constituted by the mounting substrate 2 and the translucent member 3, but the translucent member 3 is not necessarily provided, and may be appropriately provided as necessary.

実装基板２は、図１〜図３に示すように、ＬＥＤチップ１が一表面側に搭載される矩形板状のＬＥＤ搭載用基板２０と、ＬＥＤ搭載用基板２０の上記一表面側に対向配置され円形状の光取出窓４１が形成されるとともに光検出素子４が形成された光検出素子形成基板４０と、ＬＥＤ搭載用基板２０と光検出素子形成基板４０との間に介在し光取出窓４１に連通する矩形状の開口窓３１が形成された中間層基板３０とで構成されており、ＬＥＤ搭載用基板２０と中間層基板３０と光検出素子形成基板４０とで囲まれた空間が上記収納凹所２ａを構成している。ここにおいて、ＬＥＤ搭載用基板２０および中間層基板３０および光検出素子形成基板４０の外周形状は矩形状であり、中間層基板３０および光検出素子形成基板４０はＬＥＤ搭載用基板２０と同じ外形寸法に形成されている。また、光検出素子形成基板４０の厚み寸法はＬＥＤ搭載用基板２０および中間層基板３０の厚み寸法に比べて小さく設定されている。なお、本実施形態では、ＬＥＤ搭載用基板２０が、ＬＥＤチップ１が実装されるＬＥＤ実装部を構成し、中間層基板３０と光検出素子形成基板４０とが、ＬＥＤ実装部においてＬＥＤチップ１が実装される領域の周部に設けられた壁部２ｂを構成し、光検出素子形成基板４０において中間層基板３０の開口窓３１上に張り出した部位が、張出部２ｃを構成している。   As shown in FIGS. 1 to 3, the mounting substrate 2 is disposed opposite to the rectangular plate-shaped LED mounting substrate 20 on which the LED chip 1 is mounted on one surface side and the LED mounting substrate 20 on the one surface side. The circular light extraction window 41 and the light detection element forming substrate 40 on which the light detection element 4 is formed, and the light extraction window interposed between the LED mounting substrate 20 and the light detection element formation substrate 40. The space surrounded by the LED mounting substrate 20, the intermediate layer substrate 30, and the photodetecting element forming substrate 40 is configured by the intermediate layer substrate 30 in which the rectangular opening window 31 communicating with the terminal 41 is formed. The storage recess 2a is configured. Here, the outer peripheral shapes of the LED mounting substrate 20, the intermediate layer substrate 30, and the light detection element formation substrate 40 are rectangular, and the intermediate layer substrate 30 and the light detection element formation substrate 40 have the same outer dimensions as the LED mounting substrate 20. Is formed. Further, the thickness dimension of the light detection element forming substrate 40 is set smaller than the thickness dimension of the LED mounting substrate 20 and the intermediate layer substrate 30. In the present embodiment, the LED mounting substrate 20 constitutes an LED mounting portion on which the LED chip 1 is mounted, and the intermediate layer substrate 30 and the light detection element forming substrate 40 are connected to the LED chip 1 in the LED mounting portion. The wall 2b provided in the periphery of the area to be mounted, and the portion of the photodetecting element forming substrate 40 that protrudes over the opening window 31 of the intermediate layer substrate 30 constitutes the protruding portion 2c.

上述のＬＥＤ搭載用基板２０、中間層基板３０、光検出素子形成基板４０は、それぞれ、導電形がｎ形で主表面が（１００）面のシリコン基板２０ａ，３０ａ，４０ａを用いて形成してある。ここにおいて、本実施形態では、各シリコン基板２０ａ，３０ａ，４０ａそれぞれが半導体基板を構成している。要するに、本実施形態では、実装基板２が３枚の半導体基板を用いて形成されている。   The LED mounting substrate 20, the intermediate layer substrate 30, and the light detection element formation substrate 40 described above are formed using silicon substrates 20 a, 30 a, and 40 a each having an n-type conductivity and a (100) plane main surface. is there. Here, in the present embodiment, each of the silicon substrates 20a, 30a, and 40a constitutes a semiconductor substrate. In short, in the present embodiment, the mounting substrate 2 is formed using three semiconductor substrates.

また、本実施形態では、中間層基板３０の内側面が、アルカリ系溶液（例えば、ＴＭＡＨ溶液、ＫＯＨ溶液など）を用いた異方性エッチングにより形成された（１１１）面により構成されており（つまり、中間層基板３０は、開口窓３１の開口面積がＬＥＤ搭載用基板２０から離れるにつれて徐々に大きくなっており）、ＬＥＤチップ１から放射された光を前方へ反射するミラー２ｄを構成している。要するに、本実施形態では、中間層基板３０がＬＥＤチップ１から側方へ放射された光を前方へ反射させる枠状のリフレクタを兼ねている。   In the present embodiment, the inner side surface of the intermediate layer substrate 30 is constituted by a (111) plane formed by anisotropic etching using an alkaline solution (for example, TMAH solution, KOH solution, etc.) ( That is, the intermediate layer substrate 30 gradually increases as the opening area of the opening window 31 increases from the LED mounting substrate 20), and forms a mirror 2 d that reflects the light emitted from the LED chip 1 forward. Yes. In short, in the present embodiment, the intermediate layer substrate 30 also serves as a frame-like reflector that reflects light emitted from the LED chip 1 to the side.

ＬＥＤ搭載用基板２０は、図４および図５に示すように、シリコン基板２０ａの一表面側（図４（ｃ）における左面側）に、ＬＥＤチップ１の両電極それぞれと電気的に接続される２つの導体パターン２５ａ，２５ａが形成されるとともに、中間層基板３０に形成された後述の２つの貫通孔配線３４，３４を介して光検出素子４と電気的に接続される２つの導体パターン２５ｂ，２５ｂが形成されており、各導体パターン２５ａ，２５ａ，２５ｂ，２５ｂとシリコン基板２０ａの他表面側（図４（ｃ）における右面側）に形成された４つの外部接続用電極２７ａ，２７ａ，２７ｂ，２７ｂとがそれぞれ貫通孔配線２４を介して電気的に接続されている。また、ＬＥＤ搭載用基板２０は、シリコン基板２０ａの上記一表面側に、中間層基板３０と接合するための接合用金属層２９も形成されている。   As shown in FIGS. 4 and 5, the LED mounting substrate 20 is electrically connected to each of both electrodes of the LED chip 1 on one surface side (left surface side in FIG. 4C) of the silicon substrate 20 a. Two conductor patterns 25a and 25a are formed, and two conductor patterns 25b that are electrically connected to the light detection element 4 through two through-hole wirings 34 and 34, which will be described later, formed on the intermediate layer substrate 30. , 25b, and four external connection electrodes 27a, 27a, 27b formed on the other surface side (the right side in FIG. 4C) of each conductor pattern 25a, 25a, 25b, 25b and the silicon substrate 20a. 27b and 27b are electrically connected through the through-hole wiring 24, respectively. The LED mounting substrate 20 is also formed with a bonding metal layer 29 for bonding to the intermediate layer substrate 30 on the one surface side of the silicon substrate 20a.

本実施形態におけるＬＥＤチップ１は、結晶成長用基板として導電性基板を用い厚み方向の両面に電極（図示せず）が形成された可視光ＬＥＤチップである。そこで、ＬＥＤ搭載用基板２０は、ＬＥＤチップ１が電気的に接続される２つの導体パターン２５ａ，２５ａのうちの一方の導体パターン２５ａを、ＬＥＤチップ１がダイボンディングされる矩形状のダイパッド部２５ａａと、ダイパッド部２５ａａに連続一体に形成され貫通孔配線２４との接続部位となる引き出し配線部２５ａｂとで構成してある。要するに、ＬＥＤチップ１は、上記一方の導体パターン２５ａのダイパッド部２５ａａにダイボンディングされており、ダイパッド部２５ａａ側の電極がダイパッド部２５ａａに接合されて電気的に接続され、光取り出し面側の電極がボンディングワイヤ１４を介して他方の導体パターン２５ａと電気的に接続されている。ここで、本実施形態では、ＬＥＤチップ１およびダイパッド部２５ａａの平面視における外周形状を矩形状（図示例では、正方形状）としてあり、ダイパッド部２５ａａの平面サイズをＬＥＤチップ１の平面サイズよりもやや大きく設定してある。   The LED chip 1 in the present embodiment is a visible light LED chip in which a conductive substrate is used as a crystal growth substrate and electrodes (not shown) are formed on both surfaces in the thickness direction. Therefore, the LED mounting substrate 20 has one of the two conductor patterns 25a, 25a to which the LED chip 1 is electrically connected, the rectangular die pad portion 25aa to which the LED chip 1 is die-bonded. And a lead-out wiring portion 25ab that is continuously formed integrally with the die pad portion 25aa and serves as a connection portion with the through-hole wiring 24. In short, the LED chip 1 is die-bonded to the die pad portion 25aa of the one conductor pattern 25a, and the electrode on the die pad portion 25aa side is joined and electrically connected to the die pad portion 25aa, and the electrode on the light extraction surface side. Is electrically connected to the other conductor pattern 25 a via the bonding wire 14. Here, in the present embodiment, the outer peripheral shape in plan view of the LED chip 1 and the die pad portion 25aa is rectangular (in the illustrated example, a square shape), and the planar size of the die pad portion 25aa is larger than the planar size of the LED chip 1. Set slightly larger.

また、ＬＥＤ搭載用基板２０は、シリコン基板２０ａの上記他表面側に、シリコン基板２０ａよりも熱伝導率の高い金属材料からなる矩形状の放熱用パッド部２８が形成されており、ダイパッド部２５ａａと放熱用パッド部２８とがシリコン基板２０ａよりも熱伝導率の高い金属材料（例えば、Ｃｕなど）からなる複数（本実施形態では、９つ）の円柱状のサーマルビア２６を介して熱的に結合されており、ＬＥＤチップ１で発生した熱が各サーマルビア２６および放熱用パッド部２８を介して放熱されるようになっている。   The LED mounting substrate 20 has a rectangular heat radiation pad portion 28 made of a metal material having a higher thermal conductivity than the silicon substrate 20a on the other surface side of the silicon substrate 20a. The die pad portion 25aa And the heat dissipating pad portion 28 through a plurality of (in this embodiment, nine) cylindrical thermal vias 26 made of a metal material (for example, Cu) having a thermal conductivity higher than that of the silicon substrate 20a. The heat generated in the LED chip 1 is dissipated through the thermal vias 26 and the heat dissipating pad portion 28.

ところで、ＬＥＤ搭載用基板２０は、シリコン基板２０ａに、上述の４つの貫通孔配線２４それぞれが内側に形成される４つの貫通孔２２ａと、上述の９つのサーマルビア２６それぞれが内側に形成される９つの貫通孔２２ｂとが厚み方向に貫設され、シリコン基板２０ａの上記一表面および上記他表面と各貫通孔２２ａ，２２ｂの内面とに跨って熱酸化膜（シリコン酸化膜）からなる絶縁膜２３が形成されており、各導体パターン２５ａ，２５ａ，２５ｂ，２５ｂ、接合用金属層２９、各外部接続用電極２７ａ，２７ａ，２７ｂ，２７ｂ、放熱用パッド部２８、各貫通孔配線２４および各サーマルビア２６がシリコン基板２０ａと電気的に絶縁されている。ここで、本実施形態では、各サーマルビア２６用の貫通孔２２ｂの開口形状および各貫通孔配線２４用の貫通孔２２ａの開口形状を円形状としてあるが、サーマルビア２６用の貫通孔２２ｂの内径寸法を貫通孔配線２４用の貫通孔２２ａの内径よりも大きく設定してあり、シリコン基板２０ａの厚み方向に直交する断面におけるサーマルビア２６の断面積が貫通孔配線２４の断面積よりも大きくなっている。   By the way, the LED mounting substrate 20 has, in the silicon substrate 20a, four through holes 22a in which the above-described four through-hole wirings 24 are formed inside, and each of the nine thermal vias 26 in the inside. Nine through holes 22b are provided in the thickness direction, and an insulating film made of a thermal oxide film (silicon oxide film) straddling the one surface and the other surface of the silicon substrate 20a and the inner surfaces of the through holes 22a and 22b. 23, each conductor pattern 25a, 25a, 25b, 25b, bonding metal layer 29, each external connection electrode 27a, 27a, 27b, 27b, heat radiation pad 28, each through-hole wiring 24, and each The thermal via 26 is electrically insulated from the silicon substrate 20a. Here, in this embodiment, the opening shape of the through hole 22b for each thermal via 26 and the opening shape of the through hole 22a for each through hole wiring 24 are circular, but the through hole 22b for the thermal via 26 has a circular shape. The inner diameter dimension is set larger than the inner diameter of the through hole 22a for the through hole wiring 24, and the cross sectional area of the thermal via 26 in the cross section perpendicular to the thickness direction of the silicon substrate 20a is larger than the cross sectional area of the through hole wiring 24. It has become.

また、各導体パターン２５ａ，２５ａ，２５ｂ，２５ｂ、接合用金属層２９、各外部接続用電極２７ａ，２７ａ，２７ｂ，２７ｂ、放熱用パッド部２８は、絶縁膜２３上に形成されたＴｉ膜と当該Ｔｉ膜上に形成されたＡｕ膜との積層膜により構成されており、各導体パターン２５ａ，２５ａ，２５ｂ，２５ｂと接合用金属層２９とが同時に形成され、各外部接続用電極２７ａ，２７ａ，２７ｂ，２７ｂと放熱用パッド部２８とが同時に形成されている。なお、本実施形態では、絶縁膜２３上のＴｉ膜の膜厚を１５〜５０ｎｍ、Ｔｉ膜上のＡｕ膜の膜厚を５００ｎｍに設定してあるが、これらの数値は一例であって特に限定するものではない。また、各Ａｕ膜の材料は、純金に限らず不純物を添加したものでもよい。また、各Ａｕ膜と絶縁膜２３との間に密着性改善用の密着層としてＴｉ膜を介在させてあるが、密着層の材料はＴｉに限らず、例えば、Ｃｒ、Ｎｂ、Ｚｒ、ＴｉＮ、ＴａＮなどでもよい。また、貫通孔配線２４およびサーマルビア２６の材料としては、Ｃｕを採用しているが、Ｃｕに限らず、例えば、Ｎｉなどを採用してもよい。   The conductor patterns 25a, 25a, 25b, and 25b, the bonding metal layer 29, the external connection electrodes 27a, 27a, 27b, and 27b, and the heat dissipating pad portion 28 are made of a Ti film formed on the insulating film 23. Each conductive pattern 25a, 25a, 25b, 25b and the bonding metal layer 29 are formed at the same time, and each external connection electrode 27a, 27a is formed by a laminated film with an Au film formed on the Ti film. , 27b, 27b and the heat radiating pad portion 28 are formed simultaneously. In this embodiment, the thickness of the Ti film on the insulating film 23 is set to 15 to 50 nm, and the thickness of the Au film on the Ti film is set to 500 nm. However, these numerical values are only examples and are particularly limited. Not what you want. Further, the material of each Au film is not limited to pure gold, and may be one added with impurities. Further, a Ti film is interposed as an adhesion layer for improving adhesion between each Au film and the insulating film 23, but the material of the adhesion layer is not limited to Ti, for example, Cr, Nb, Zr, TiN, TaN or the like may be used. Moreover, although Cu is adopted as the material of the through-hole wiring 24 and the thermal via 26, it is not limited to Cu, and for example, Ni may be adopted.

ここにおいて、本実施形態では、上記一方の導体パターン２５ａのダイパッド部２５ａａが、ＬＥＤチップ１の一面全体が接合されＬＥＤチップ１と複数のサーマルビア２６とを熱結合する均熱板部を構成し、上記一方の導体パターン２５の引き出し配線部２５ａｂおよび上記他方の導体パターン２５が、均熱板部の周辺において貫通孔配線２４と接続される導体部を構成している。なお、本実施形態では、均熱板部と導体部とが同一材料により形成され、均熱板部と一方の導体部とが連続一体に形成されているが、均熱板部と導体部とは別材料により形成してもよい。また、ＬＥＤチップ１の結晶成長用基板が絶縁性基板や半絶縁性基板であって当該結晶成長用基板を均熱板部に接合する場合には、均熱板部の材料は必ずしも導電性材料に限らず、熱伝導率の高い材料（例えば、ＡｌＮなど）であればよい。   Here, in the present embodiment, the die pad portion 25aa of the one conductor pattern 25a constitutes a soaking plate portion in which the entire one surface of the LED chip 1 is bonded and the LED chip 1 and the plurality of thermal vias 26 are thermally coupled. The lead wiring portion 25ab of the one conductor pattern 25 and the other conductor pattern 25 constitute a conductor portion connected to the through-hole wiring 24 around the heat equalizing plate portion. In this embodiment, the heat equalizing plate portion and the conductor portion are formed of the same material, and the heat equalizing plate portion and one conductor portion are continuously formed integrally. May be formed of another material. Further, when the crystal growth substrate of the LED chip 1 is an insulating substrate or a semi-insulating substrate, and the crystal growth substrate is bonded to the soaking plate portion, the material of the soaking plate portion is not necessarily a conductive material. However, the present invention is not limited to this, and any material having high thermal conductivity (for example, AlN) may be used.

中間層基板３０は、図６および図７に示すように、シリコン基板３０ａの一表面側（図６（ｃ）における右面側）に、ＬＥＤ搭載用基板２０の２つの導体パターン２７ｂ，２７ｂと接合されて電気的に接続される２つの導体パターン３５，３５が形成されるとともに、ＬＥＤ搭載用基板２０の接合用金属層２９と接合される接合用金属層３６が形成されている。また、中間層基板３０は、シリコン基板３０ａの他表面側（図６（ｃ）における左面側）に、貫通孔配線３４，３４を介して導体パターン３５，３５と電気的に接続される導体パターン３７，３７が形成されるとともに、光検出素子形成基板４０と接合するための接合用金属層３８が形成されている。   As shown in FIGS. 6 and 7, the intermediate layer substrate 30 is bonded to the two conductor patterns 27b and 27b of the LED mounting substrate 20 on one surface side (the right side in FIG. 6C) of the silicon substrate 30a. Thus, two conductive patterns 35 and 35 that are electrically connected are formed, and a bonding metal layer 36 that is bonded to the bonding metal layer 29 of the LED mounting substrate 20 is formed. In addition, the intermediate layer substrate 30 is a conductor pattern electrically connected to the conductor patterns 35 and 35 via the through-hole wirings 34 and 34 on the other surface side of the silicon substrate 30a (the left side in FIG. 6C). 37 and 37 are formed, and a bonding metal layer 38 for bonding to the light detection element forming substrate 40 is formed.

また、中間層基板３０は、上述の２つの貫通孔配線３４それぞれが内側に形成される２つの貫通孔３２がシリコン基板３０ａの厚み方向に貫設され、シリコン基板３０ａの上記一表面および上記他表面と各貫通孔３２の内面とに跨って熱酸化膜（シリコン酸化膜）からなる絶縁膜３３が形成されており、各導体パターン３５，３５，３７，３７および各接合用金属層３６，３８および各貫通孔配線３４がシリコン基板３０ａと電気的に絶縁されている。ここにおいて、各導体パターン３５，３５，３７，３７および各接合用金属層３６，３８は、絶縁膜３３上に形成されたＴｉ膜と当該Ｔｉ膜上に形成されたＡｕ膜との積層膜により構成されており、導体パターン３５，３５と接合用金属層３６とが同時に形成され、導体パターン３７，３７と接合用金属層３８とが同時に形成されている。なお、本実施形態では、絶縁膜３３上のＴｉ膜の膜厚を１５〜５０ｎｍ、Ｔｉ膜上のＡｕ膜の膜厚を５００ｎｍに設定してあるが、これらの数値は一例であって特に限定するものではない。ここにおいて、各Ａｕ膜の材料は、純金に限らず不純物を添加したものでもよい。また、各Ａｕ膜と絶縁膜３３との間に密着性改善用の密着層としてＴｉ膜を介在させてあるが、密着層の材料はＴｉに限らず、例えば、Ｃｒ、Ｎｂ、Ｚｒ、ＴｉＮ、ＴａＮなどでもよい。また、貫通孔配線３４の材料としては、Ｃｕを採用しているが、Ｃｕに限らず、例えば、Ｎｉなどを採用してもよい。   Further, the intermediate layer substrate 30 has two through holes 32 formed therein in the thickness direction of the silicon substrate 30a, and the one surface of the silicon substrate 30a and the other. An insulating film 33 made of a thermal oxide film (silicon oxide film) is formed across the surface and the inner surface of each through hole 32, and each conductor pattern 35, 35, 37, 37 and each bonding metal layer 36, 38 are formed. Each through-hole wiring 34 is electrically insulated from the silicon substrate 30a. Here, each of the conductor patterns 35, 35, 37, 37 and each of the bonding metal layers 36, 38 is a laminated film of a Ti film formed on the insulating film 33 and an Au film formed on the Ti film. The conductor patterns 35 and 35 and the bonding metal layer 36 are formed at the same time, and the conductor patterns 37 and 37 and the bonding metal layer 38 are formed at the same time. In this embodiment, the thickness of the Ti film on the insulating film 33 is set to 15 to 50 nm, and the thickness of the Au film on the Ti film is set to 500 nm. However, these numerical values are only examples and are particularly limited. Not what you want. Here, the material of each Au film is not limited to pure gold, and may be added with impurities. Further, although a Ti film is interposed as an adhesion improving layer for adhesion between each Au film and the insulating film 33, the material of the adhesion layer is not limited to Ti, for example, Cr, Nb, Zr, TiN, TaN or the like may be used. Moreover, although Cu is adopted as the material of the through-hole wiring 34, it is not limited to Cu, and for example, Ni may be adopted.

光検出素子形成基板４０は、図８および図９に示すように、シリコン基板４０ａの一表面側（図８（ｃ）における右面側）に、中間層基板３０の２つの導体パターン３７，３７と接合されて電気的に接続される２つの導体パターン４７ａ，４７ｂが形成されるとともに、中間層基板３０の接合用金属層３８と接合される接合用金属層４８が形成されている。ここにおいて、光検出素子４は、フォトダイオードにより構成されており、光検出素子形成基板４０に形成された２つの導体パターン４７ａ，４７ｂの一方の導体パターン４７ａ（図９における上側の導体パターン４７ａ）は、光検出素子４を構成するフォトダイオードのｐ形領域４ａに電気的に接続され、他方の導体パターン４７ｂ（図９における下側の導体パターン４７ｂ）は、上記フォトダイオードのｎ形領域４ｂを構成するシリコン基板４０ａに電気的に接続されている。   As shown in FIGS. 8 and 9, the photodetecting element forming substrate 40 has two conductor patterns 37 and 37 on the intermediate layer substrate 30 on one surface side (right side in FIG. 8C) of the silicon substrate 40a. Two conductor patterns 47 a and 47 b that are bonded and electrically connected are formed, and a bonding metal layer 48 that is bonded to the bonding metal layer 38 of the intermediate layer substrate 30 is formed. Here, the photodetecting element 4 is constituted by a photodiode, and one of the two conductor patterns 47a and 47b formed on the photodetecting element forming substrate 40 (the upper conductor pattern 47a in FIG. 9). Is electrically connected to the p-type region 4a of the photodiode constituting the photodetecting element 4, and the other conductor pattern 47b (lower conductor pattern 47b in FIG. 9) is connected to the n-type region 4b of the photodiode. It is electrically connected to the silicon substrate 40a that constitutes it.

また、光検出素子形成基板４０は、シリコン基板４０ａの上記一表面側にシリコン酸化膜からなる絶縁膜４３が形成されており、当該絶縁膜４３がフォトダイオードの反射防止膜を兼ねている。また、光検出素子形成基板４０は、上記一方の導体パターン４７ａが、絶縁膜４３に形成したコンタクトホール４３ａを通してｐ形領域４３ａと電気的に接続され、上記他方の導体パターン４７ｂが絶縁膜４３に形成したコンタクトホール４３ｂを通してｎ形領域４ｂと電気的に接続されている。ここにおいて、各導体パターン４７ａ，４７ｂおよび接合用金属層４８は、絶縁膜４３上に形成されたＴｉ膜と当該Ｔｉ膜上に形成されたＡｕ膜との積層膜により構成されており、同時に形成してある。なお、本実施形態では、絶縁膜４３上のＴｉ膜の膜厚を１５〜５０ｎｍ、Ｔｉ膜上のＡｕ膜の膜厚を５００ｎｍに設定してあるが、これらの数値は一例であって特に限定するものではない。ここにおいて、各Ａｕ膜の材料は、純金に限らず不純物を添加したものでもよい。また、各Ａｕ膜と絶縁膜４３との間に密着性改善用の密着層としてＴｉ膜を介在させてあるが、密着層の材料はＴｉに限らず、例えば、Ｃｒ、Ｎｂ、Ｚｒ、ＴｉＮ、ＴａＮなどでもよい。   Further, in the photodetecting element forming substrate 40, an insulating film 43 made of a silicon oxide film is formed on the one surface side of the silicon substrate 40a, and the insulating film 43 also serves as an antireflection film of the photodiode. In the photodetecting element forming substrate 40, the one conductor pattern 47 a is electrically connected to the p-type region 43 a through the contact hole 43 a formed in the insulating film 43, and the other conductor pattern 47 b is connected to the insulating film 43. The n-type region 4b is electrically connected through the formed contact hole 43b. Here, each of the conductor patterns 47a and 47b and the bonding metal layer 48 is composed of a laminated film of a Ti film formed on the insulating film 43 and an Au film formed on the Ti film, and is formed at the same time. It is. In this embodiment, the thickness of the Ti film on the insulating film 43 is set to 15 to 50 nm, and the thickness of the Au film on the Ti film is set to 500 nm. However, these numerical values are only examples and are particularly limited. Not what you want. Here, the material of each Au film is not limited to pure gold, and may be added with impurities. Further, a Ti film is interposed as an adhesion layer for improving adhesion between each Au film and the insulating film 43, but the material of the adhesion layer is not limited to Ti, for example, Cr, Nb, Zr, TiN, TaN or the like may be used.

上述の実装基板２の形成にあたっては、例えば図１０に示すように、光検出素子４、絶縁膜４３、各導体パターン４７ａ，４７ｂ、および接合用金属層４８が形成されたシリコン基板４０ａと中間層基板３０とを低温での直接接合が可能な常温接合法などにより接合する第１の接合工程を行った後、シリコン基板４０ａを所望の厚みまで研磨する研磨工程を行い、その後、誘導結合プラズマ（ＩＣＰ）型のドライエッチング装置などを用いてシリコン基板４０ａに光取出窓４１を形成する光取出窓形成工程を行うことで光検出素子形成基板４０を完成させてから、ＬＥＤチップ１が実装されボンディングワイヤ１４の結線が行われたＬＥＤ搭載用基板２０と中間層基板３０とを常温接合法などにより接合する第２の接合工程を行うようにすればよい。なお、常温接合法では、接合前に互いの接合表面へアルゴンのプラズマ若しくはイオンビーム若しくは原子ビームを真空中で照射して各接合表面の清浄化・活性化を行ってから、接合表面同士を接触させ、常温下で直接接合する。   In forming the mounting substrate 2 described above, for example, as shown in FIG. 10, the silicon substrate 40a and the intermediate layer on which the photodetecting element 4, the insulating film 43, the respective conductor patterns 47a and 47b, and the bonding metal layer 48 are formed. After performing a first bonding step for bonding the substrate 30 to the substrate 30 by a room temperature bonding method capable of direct bonding at a low temperature, a polishing step for polishing the silicon substrate 40a to a desired thickness is performed, and then inductively coupled plasma ( The light detection element forming substrate 40 is completed by performing the light extraction window forming step of forming the light extraction window 41 on the silicon substrate 40a using an ICP) type dry etching apparatus or the like, and then the LED chip 1 is mounted and bonded. A second bonding step is performed in which the LED mounting substrate 20 to which the wires 14 are connected and the intermediate layer substrate 30 are bonded by a room temperature bonding method or the like. Good. In the normal temperature bonding method, the bonding surfaces are contacted with each other after the bonding surfaces are cleaned and activated by irradiating the bonding surfaces with argon plasma, ion beam or atomic beam in vacuum before bonding. And bond directly at room temperature.

上述の第１の接合工程では、シリコン基板４０ａの接合用金属層４８と中間層基板３０の接合用金属層３８とが接合されるとともに、シリコン基板４０ａの導体パターン４７ａ，４７ｂと中間層基板３０の導体パターン３７，３７とが接合され電気的に接続される。ここで、導体パターン４７ａ，４７ｂと導体パターン３７，３７との接合部位は、貫通孔配線３４に重なる領域からずらしてあるので、導体パターン４７ａ，４７ｂと導体パターン３７，３７との互いの接合面の平坦度を高めることができ、接合歩留まりを高めることができるとともに接合信頼性を高めることができる。また、第２の接合工程では、ＬＥＤ搭載用基板２０の接合用金属層２９と中間層基板３０の接合用金属層３６とが接合されるとともに、ＬＥＤ搭載用基板２０の導体パターン２５ｂ，２５ｂと中間層基板３０の導体パターン３５，３５とが接合され電気的に接続される。ここで、導体パターン２５ｂ，２５ｂと導体パターン３５，３５との接合部位は、貫通孔配線２４に重なる領域および貫通孔配線３４に重なる領域からずらしてあるので、導体パターン２５ｂ，２５ｂと導体パターン３５，３５との互いの接合面の平坦度を高めることができ、接合歩留まりを高めることができるとともに接合信頼性を高めることができる。   In the first bonding step, the bonding metal layer 48 of the silicon substrate 40a and the bonding metal layer 38 of the intermediate layer substrate 30 are bonded, and the conductor patterns 47a and 47b of the silicon substrate 40a and the intermediate layer substrate 30 are bonded. The conductor patterns 37 and 37 are joined and electrically connected. Here, since the joint portions of the conductor patterns 47a and 47b and the conductor patterns 37 and 37 are shifted from the region overlapping the through-hole wiring 34, the joint surfaces of the conductor patterns 47a and 47b and the conductor patterns 37 and 37 are mutually connected. The flatness of the substrate can be increased, the junction yield can be increased, and the junction reliability can be increased. In the second bonding step, the bonding metal layer 29 of the LED mounting substrate 20 and the bonding metal layer 36 of the intermediate layer substrate 30 are bonded, and the conductor patterns 25b and 25b of the LED mounting substrate 20 The conductor patterns 35 and 35 of the intermediate layer substrate 30 are joined and electrically connected. Here, since the joint portions of the conductor patterns 25b and 25b and the conductor patterns 35 and 35 are shifted from the region overlapping the through-hole wiring 24 and the region overlapping the through-hole wiring 34, the conductor patterns 25b and 25b and the conductor pattern 35 are arranged. , 35, the flatness of the mutual joint surfaces can be increased, the joint yield can be increased, and the joint reliability can be enhanced.

また、上述の透光性部材３は、透光性材料（例えば、シリコーン、アクリル樹脂、ガラスなど）からなる透光性基板を用いて形成してある。ここで、透光性部材３は、実装基板２と同じ外周形状の矩形板状に形成されており、実装基板２側とは反対の光取り出し面に、ＬＥＤチップ１から放射された光の全反射を抑制する微細凹凸構造が形成されている。ここにおいて、透光性部材３の光取り出し面に形成する微細凹凸構造は、多数の微細な凹部が２次元周期構造を有するように形成されている。なお、上述の微細凹凸構造は、例えば、レーザ加工技術やエッチング技術やインプリントリソグラフィ技術などを利用して形成すればよい。また、微細凹凸構造の周期は、ＬＥＤチップ１の発光ピーク波長の１／４〜１００倍程度の範囲で適宜設定すればよい。   Moreover, the above-mentioned translucent member 3 is formed using the translucent board | substrate which consists of translucent materials (for example, silicone, an acrylic resin, glass, etc.). Here, the translucent member 3 is formed in a rectangular plate shape having the same outer peripheral shape as the mounting substrate 2, and all of the light emitted from the LED chip 1 is formed on the light extraction surface opposite to the mounting substrate 2 side. A fine concavo-convex structure that suppresses reflection is formed. Here, the fine concavo-convex structure formed on the light extraction surface of the translucent member 3 is formed such that many fine concave portions have a two-dimensional periodic structure. The fine concavo-convex structure described above may be formed using, for example, a laser processing technique, an etching technique, an imprint lithography technique, or the like. The period of the fine concavo-convex structure may be set as appropriate within a range of about ¼ to 100 times the emission peak wavelength of the LED chip 1.

本実施形態の発光装置の製造にあたっては、上述の各シリコン基板２０ａ，３０ａ，４０ａとして、それぞれＬＥＤ搭載用基板２０、中間層基板３０、光検出素子形成基板４０を多数形成可能なシリコンウェハを用いるとともに、上述の透光性基板として透光性部材３を多数形成可能なウェハ状のもの（透光性ウェハ）を用い、上述の第１の接合工程、研磨工程、第２の接合工程、光取出窓形成工程、第２の接合工程、実装基板２の収納凹所２ａに封止樹脂を充填して封止部５を形成する封止部形成工程、封止部形成工程の後で実装基板２と透光性部材３とを接合する第３の接合工程などの各工程をウェハレベルで行うことでウェハレベルパッケージ構造体を形成してから、ダイシング工程により実装基板２のサイズに分割されている。したがって、ＬＥＤ搭載用基板２０と中間層基板３０と光検出素子形成基板４０と透光性部材３とが同じ外形サイズとなり、小型のパッケージを実現できるとともに、製造が容易になる。また、実装基板２の形成にあたって上述の各接合工程において、低温での直接接合が可能な常温接合法を採用しているので、各接合工程でＬＥＤチップ１のジャンクション温度が最大ジャンクション温度を超えるのを防止することができる。   In manufacturing the light emitting device of this embodiment, a silicon wafer capable of forming a large number of LED mounting substrates 20, intermediate layer substrates 30, and light detection element formation substrates 40 is used as each of the silicon substrates 20a, 30a, and 40a described above. In addition, a wafer-like one (translucent wafer) capable of forming a large number of translucent members 3 is used as the above-described translucent substrate, and the above-described first bonding step, polishing step, second bonding step, light The mounting substrate after the extraction window forming step, the second bonding step, the sealing portion forming step of filling the housing recess 2a of the mounting substrate 2 with the sealing resin to form the sealing portion 5, and the sealing portion forming step The wafer level package structure is formed by performing each process such as a third joining process for joining 2 and the translucent member 3 at the wafer level, and then divided into the size of the mounting substrate 2 by the dicing process. Yes. Therefore, the LED mounting substrate 20, the intermediate layer substrate 30, the light detection element forming substrate 40, and the translucent member 3 have the same outer size, so that a small package can be realized and manufacturing is facilitated. In addition, since the room temperature bonding method capable of direct bonding at a low temperature is adopted in each of the above-described bonding processes in forming the mounting substrate 2, the junction temperature of the LED chip 1 exceeds the maximum junction temperature in each bonding process. Can be prevented.

以上説明した本実施形態の発光装置では、実装基板２は、当該実装基板２の厚み方向に直交する断面における各サーマルビア２６の断面積が各貫通孔配線２４の断面積よりも大きく、且つ、ＬＥＤチップ１の一面全体が接合されＬＥＤチップ１と複数のサーマルビア２６とを熱結合する均熱板部として機能するダイパッド部２５ａａを有しているので、ＬＥＤチップ１で発生した熱の放熱路のうちＬＥＤチップ１から各サーマルビア２６までの間に放熱路の断面積がＬＥＤチップ１のチップサイズよりも小さくなる区間が存在しないことにより、熱抵抗を低減することができて放熱性を高めることが可能となり、しかも、実装基板２の厚み方向に直交する断面における各サーマルビア２６の断面積を小さくすることなくサーマルビア２６の数を増やすことが可能となるから、放熱性をより一層高めることが可能となる。したがって、本実施形態の発光装置では、ＬＥＤチップ１で発生した熱を効率よく外部へ逃がすことができ、ＬＥＤチップ１のジャンクション温度の温度上昇を抑制できるから、入力電力を大きくでき、光出力の高出力化を図れる。   In the light emitting device of the present embodiment described above, the mounting substrate 2 has a cross sectional area of each thermal via 26 in a cross section perpendicular to the thickness direction of the mounting substrate 2 larger than the cross sectional area of each through hole wiring 24, and Since the entire surface of the LED chip 1 is bonded and has the die pad portion 25aa that functions as a heat equalizing plate portion that thermally couples the LED chip 1 and the plurality of thermal vias 26, a heat dissipation path for the heat generated in the LED chip 1 Among these, since there is no section where the cross-sectional area of the heat radiation path is smaller than the chip size of the LED chip 1 between the LED chip 1 and each thermal via 26, the thermal resistance can be reduced and the heat radiation performance is improved. In addition, the number of thermal vias 26 can be reduced without reducing the cross-sectional area of each thermal via 26 in the cross section perpendicular to the thickness direction of the mounting substrate 2. Since it becomes possible to increase, it is possible to improve the heat dissipation more. Therefore, in the light emitting device of the present embodiment, the heat generated in the LED chip 1 can be efficiently released to the outside, and the temperature rise of the junction temperature of the LED chip 1 can be suppressed, so that the input power can be increased and the light output can be increased. High output can be achieved.

また、本実施形態の発光装置では、実装基板２は、各貫通孔配線２４と接続される複数の導体部が均熱板部たるダイパッド部２５ａａの周辺に形成されているので、実装基板２の厚み方向においてＬＥＤチップ１と貫通孔配線２４とが重複している場合に比べて、サーマルビア２６の数を増やすことが可能となるから、放熱性を高めることが可能となる。   Further, in the light emitting device of the present embodiment, the mounting substrate 2 has a plurality of conductor portions connected to each through-hole wiring 24 formed around the die pad portion 25aa which is a heat equalizing plate portion. Compared with the case where the LED chip 1 and the through-hole wiring 24 overlap in the thickness direction, the number of the thermal vias 26 can be increased, so that heat dissipation can be improved.

ところで、図１５に示した従来構成の発光装置では、ＬＥＤチップ１から放射された光を検出することができないが、本実施形態の発光装置では、実装基板２における収納凹所２ａの周部から内方へ突出する張出部２ｃにＬＥＤチップ１から放射された光を検出する光検出素子４が設けられているので、ＬＥＤチップ１から放射された光を検出することができる。したがって、例えば、ＬＥＤチップ１として赤色ＬＥＤチップを採用した発光装置と、ＬＥＤチップ１として緑色ＬＥＤチップを採用した発光装置と、ＬＥＤチップ１として青色ＬＥＤチップを採用した発光装置とを同一の回路基板上に近接して配置して、当該回路基板に各発光装置のＬＥＤチップ１を駆動する駆動回路部と、各光検出素子４により検出される光強度がそれぞれの目標値に保たれるように駆動回路部から各発光色のＬＥＤチップ１に流れる電流をフィードバック制御する制御回路部などを設けておくことにより、各光検出素子４それぞれの出力に基づいて各発光色のＬＥＤチップ１の光出力を各別に制御することができ、各発光色ごとのＬＥＤチップ１の光出力の経時変化の違いなどによらず混色光（ここでは、白色光）の光色や色温度の精度を向上することができる。要するに、本実施形態の発光装置では、所望の混色光を安定して得ることが可能となる。   By the way, in the light emitting device having the conventional configuration shown in FIG. 15, the light emitted from the LED chip 1 cannot be detected. However, in the light emitting device of this embodiment, from the peripheral portion of the housing recess 2 a in the mounting substrate 2. Since the light detection element 4 for detecting the light emitted from the LED chip 1 is provided on the projecting portion 2c protruding inward, the light emitted from the LED chip 1 can be detected. Therefore, for example, a light emitting device that employs a red LED chip as the LED chip 1, a light emitting device that employs a green LED chip as the LED chip 1, and a light emitting device that employs a blue LED chip as the LED chip 1 are the same circuit board. Arranged close to each other, the drive circuit unit for driving the LED chip 1 of each light emitting device on the circuit board and the light intensity detected by each light detection element 4 are maintained at the respective target values. By providing a control circuit unit that feedback-controls the current flowing from the drive circuit unit to the LED chip 1 of each emission color, the light output of the LED chip 1 of each emission color is based on the output of each of the light detection elements 4. Can be controlled separately, and the mixed color light (in this case, white light) can be controlled regardless of the temporal change in the light output of the LED chip 1 for each emission color. It is possible to improve the accuracy of color or color temperature. In short, in the light emitting device of this embodiment, it is possible to stably obtain desired mixed color light.

なお、本実施形態では、実装基板２の収納凹所２ａの内底面に１つのＬＥＤチップ１を実装してあるが、ＬＥＤチップ１の数は特に限定するものではなく、発光色が同じ複数のＬＥＤチップ１を収納凹所２ａの内底面に実装するようにしてもよい。   In the present embodiment, one LED chip 1 is mounted on the inner bottom surface of the housing recess 2a of the mounting substrate 2. However, the number of LED chips 1 is not particularly limited, and a plurality of light emission colors are the same. The LED chip 1 may be mounted on the inner bottom surface of the storage recess 2a.

（実施形態２）
以下、本実施形態の発光装置について図１１〜図１４に基づいて説明する。 (Embodiment 2)
Hereinafter, the light-emitting device of this embodiment will be described with reference to FIGS.

本実施形態の発光装置の基本構成は実施形態１と略同じであり、実装基板２の収納凹所２ａの内底面に互いに発光色の異なる複数（図示例では、４つ）のＬＥＤチップ１が実装され、光検出素子形成基板４０に、各発光色のＬＥＤチップ１それぞれから放射された光を各別に検出する複数の光検出素子４（図示例では、４つ）が設けられている点などが相違する。ここにおいて、本実施形態では、４つのＬＥＤチップ１として、発光色が赤色のＬＥＤチップ１ａと、発光色が緑色のＬＥＤチップ１ｂと、発光色が青色のＬＥＤチップ１ｃと、発光色が黄色のＬＥＤチップ１ｄとを採用しており、赤色光と緑色光と青色光と黄色光の混色光として白色光を得ることができる。ただし、各ＬＥＤチップ１の発光色は特に限定するものではなく、所望の混色光に応じて適宜選択すればよい。なお、実施形態１と同様の構成要素には同一の符号を付して説明を省略する。   The basic configuration of the light emitting device of the present embodiment is substantially the same as that of the first embodiment, and a plurality (four in the illustrated example) of LED chips 1 having different emission colors are provided on the inner bottom surface of the housing recess 2a of the mounting substrate 2. A plurality of light detection elements 4 (four in the illustrated example) that are mounted and detect light emitted from the respective LED chips 1 of the respective emission colors are provided on the light detection element forming substrate 40. Is different. Here, in this embodiment, as the four LED chips 1, the LED chip 1a whose emission color is red, the LED chip 1b whose emission color is green, the LED chip 1c whose emission color is blue, and the emission color which is yellow are shown. The LED chip 1d is employed, and white light can be obtained as mixed color light of red light, green light, blue light, and yellow light. However, the emission color of each LED chip 1 is not particularly limited, and may be appropriately selected according to the desired mixed color light. In addition, the same code | symbol is attached | subjected to the component similar to Embodiment 1, and description is abbreviate | omitted.

本実施形態の発光装置は、各光検出素子４において対応するＬＥＤチップ１ａ〜１ｄから放射された光のみを選択的に検出可能とするために、各ＬＥＤチップ１ａ〜１ｄそれぞれから放射される光の放射範囲を制限する十字状の遮光壁３９を中間層基板３０に連続一体に形成してある。要するに、本実施形態の発光装置では、中間層基板３０の開口窓３１が遮光壁３９によって４つの小空間３１ａに分けられている。ここにおいて、本実施形態では、中間層基板３０における遮光壁３９がアルカリ系溶液を用いた異方性エッチングにより開口窓３１と同時に形成されており、遮光壁３９の各側面が開口窓３１の内側面と同様に（１１１）面となっているので、遮光壁３９の各側面がＬＥＤチップ１ａ〜１ｄから放射された光を前方へ反射するミラーとして機能する。   In the light emitting device of this embodiment, in order to selectively detect only the light emitted from the corresponding LED chips 1a to 1d in each light detection element 4, the light emitted from each of the LED chips 1a to 1d. A cross-shaped light shielding wall 39 that restricts the radiation range is formed integrally with the intermediate layer substrate 30 continuously. In short, in the light emitting device of this embodiment, the opening window 31 of the intermediate layer substrate 30 is divided into four small spaces 31 a by the light shielding wall 39. Here, in this embodiment, the light shielding wall 39 in the intermediate layer substrate 30 is formed simultaneously with the opening window 31 by anisotropic etching using an alkaline solution, and each side surface of the light shielding wall 39 is within the opening window 31. Since it is a (111) plane like the side surface, each side surface of the light shielding wall 39 functions as a mirror that reflects light emitted from the LED chips 1a to 1d forward.

しかして、本実施形態の発光装置では、各発光色のＬＥＤチップ１ａ〜１ｄから同時に放射された光を各光検出素子４にて各別に精度良く検出することができ、各光検出素子４それぞれの出力に基づいて各発光色のＬＥＤチップ１ａ〜１ｄの光出力を各別に制御することが可能となり、所望の混色光を安定して得ることが可能となる。すなわち、本実施形態の発光装置を実装する回路基板などに、各ＬＥＤチップ１ａ〜１ｄを駆動する駆動回路部、各光検出素子４により検出される光強度がそれぞれの目標値に保たれるように駆動回路部から各ＬＥＤチップ１ａ〜１ｄに流れる電流をフィードバック制御する制御回路部などを設けておくことにより、各光検出素子４それぞれの出力に基づいて各発光色のＬＥＤチップ１ａ〜１ｄの光出力を各別に制御することができ、各発光色ごとのＬＥＤチップ１ａ，１ｂ，１ｃ，１ｄの光出力の経時変化の違いなどによらず混色光（ここでは、白色光）の光色や色温度の精度を向上することができる。   Thus, in the light emitting device according to the present embodiment, the light emitted from the LED chips 1a to 1d of the respective emission colors can be detected with high accuracy by the respective light detecting elements 4, and each of the light detecting elements 4 can be detected. On the basis of the output, the light output of each of the LED chips 1a to 1d of the respective emission colors can be controlled separately, and the desired mixed color light can be stably obtained. That is, the light intensity detected by the drive circuit unit that drives each LED chip 1a to 1d and each photodetecting element 4 is maintained at the target value on the circuit board on which the light emitting device of this embodiment is mounted. Is provided with a control circuit unit that feedback-controls the current flowing from the drive circuit unit to each of the LED chips 1a to 1d, so that each of the LED chips 1a to 1d of each emission color is based on the output of each of the light detection elements 4. The light output can be controlled separately, and the light color of the mixed color light (here, white light) regardless of the temporal change in the light output of the LED chips 1a, 1b, 1c, 1d for each emission color, The accuracy of the color temperature can be improved.

ところで、上記各実施形態１，２では、実装基板２を３枚の半導体基板を用いて形成してあるが、実装基板２の基礎とする半導体基板の数は特に限定するものではなく、例えば、図１５に示した従来例と同様に１枚の半導体基板を用いて形成してもよいし、２枚の半導体基板を用いて形成してもよい。   In the first and second embodiments, the mounting substrate 2 is formed using three semiconductor substrates. However, the number of semiconductor substrates on which the mounting substrate 2 is based is not particularly limited. For example, Similarly to the conventional example shown in FIG. 15, it may be formed using one semiconductor substrate, or may be formed using two semiconductor substrates.

実施形態１の発光装置の概略断面図である。1 is a schematic cross-sectional view of a light emitting device according to Embodiment 1. FIG. 同上の発光装置の概略分解斜視図である。It is a general | schematic disassembled perspective view of a light-emitting device same as the above. 同上における実装基板を示し、（ａ）は概略平面図、（ｂ）は（ａ）のＡ−Ａ’概略断面図、（ｃ）は（ａ）のＢ−Ｂ’概略断面図である。The mounting board | substrate is shown, (a) is a schematic plan view, (b) is A-A 'schematic sectional drawing of (a), (c) is B-B' schematic sectional drawing of (a). 同上におけるＬＥＤ搭載用基板を示し、（ａ）は概略平面図、（ｂ）は（ａ）のＡ−Ａ’概略断面図、（ｃ）は（ａ）のＢ−Ｂ’概略断面図である。The board | substrate for LED mounting same as the above is shown, (a) is a schematic plan view, (b) is AA 'schematic sectional drawing of (a), (c) is BB' schematic sectional drawing of (a). . 同上におけるＬＥＤ搭載用基板の概略下面図である。It is a schematic bottom view of the board | substrate for LED mounting in the same as the above. 同上における中間層基板を示し、（ａ）は概略平面図、（ｂ）は（ａ）のＡ−Ａ’概略断面図、（ｃ）は（ａ）のＢ−Ｂ’概略断面図である。The intermediate | middle layer board | substrate in the same is shown, (a) is a schematic plan view, (b) is A-A 'schematic sectional drawing of (a), (c) is B-B' schematic sectional drawing of (a). 同上における中間層基板の概略下面図である。It is a schematic bottom view of the intermediate | middle layer board | substrate in the same as the above. 同上における光検出素子形成基板を示し、（ａ）は概略平面図、（ｂ）は（ａ）のＡ−Ａ’概略断面図、（ｃ）は（ａ）のＢ−Ｂ’概略断面図である。The optical detection element formation board in the same as above is shown, (a) is a schematic plan view, (b) is an AA 'schematic sectional view of (a), (c) is a BB' schematic sectional view of (a). is there. 同上における光検出素子形成基板の概略下面図である。It is a schematic bottom view of the optical detection element formation board | substrate in the same as the above. 同上における実装基板の形成方法の説明図である。It is explanatory drawing of the formation method of the mounting board | substrate in the same as the above. 実施形態２の発光装置の概略断面図である。6 is a schematic cross-sectional view of a light emitting device according to Embodiment 2. FIG. 同上の発光装置の要部概略平面図である。It is a principal part schematic plan view of a light-emitting device same as the above. 同上の発光装置の概略分解斜視図である。It is a general | schematic disassembled perspective view of a light-emitting device same as the above. 同上の発光装置における光検出素子形成基板の概略下面図である。It is a schematic bottom view of the light detection element formation board | substrate in the light-emitting device same as the above. 従来例を示し、（ａ）は概略平面図、（ｂ）は（ａ）のＡ−Ａ’概略断面図である。A prior art example is shown, (a) is a schematic plan view, and (b) is a schematic cross-sectional view along A-A 'of (a).

符号の説明Explanation of symbols

１ ＬＥＤチップ
２ 実装基板
２０ａ，３０ａ，４０ａ シリコン基板（半導体基板）
２２ａ 貫通孔
２２ｂ 貫通孔
２３ 絶縁膜
２４ 貫通孔配線
２５ａ 導体パターン
２５ａａ ダイパッド部（均熱板部）
２５ａｂ 引き出し配線部（導体部）
２６ サーマルビア
２７ａ 外部接続用電極
２８ 放熱用パッド部 DESCRIPTION OF SYMBOLS 1 LED chip 2 Mounting substrate 20a, 30a, 40a Silicon substrate (semiconductor substrate)
22a Through-hole 22b Through-hole 23 Insulating film 24 Through-hole wiring 25a Conductor pattern 25aa Die pad part (heat equalizing plate part)
25ab Lead-out wiring part (conductor part)
26 Thermal Via 27a External Connection Electrode 28 Heat Dissipation Pad

Claims (2)

ＬＥＤチップと、半導体基板を用いて形成されＬＥＤチップが実装された実装基板とを備え、ＬＥＤチップへの給電路の一部となる複数の貫通孔配線およびＬＥＤチップで発生した熱の放熱路となる複数のサーマルビアが実装基板の厚み方向に貫設された発光装置であって、実装基板は、前記厚み方向に直交する断面における各サーマルビアの断面積が各貫通孔配線の断面積よりも大きく、且つ、ＬＥＤチップの一面全体が接合されＬＥＤチップと複数のサーマルビアとを熱結合する均熱板部を有してなることを特徴とする発光装置。   An LED chip and a mounting substrate formed using a semiconductor substrate and mounted with the LED chip, a plurality of through-hole wirings serving as part of a power feeding path to the LED chip, and a heat dissipation path for heat generated in the LED chip; A plurality of thermal vias are provided in the thickness direction of the mounting board, wherein the mounting board has a cross-sectional area of each thermal via in a cross-section orthogonal to the thickness direction than the cross-sectional area of each through-hole wiring A light-emitting device that is large and has a soaking plate portion that is bonded to the entire surface of the LED chip and thermally couples the LED chip and a plurality of thermal vias. 前記実装基板は、前記各貫通孔配線と接続される複数の導体部が前記均熱板部の周辺に形成されてなることを特徴とする請求項１記載の発光装置。
The light emitting device according to claim 1, wherein the mounting substrate is formed with a plurality of conductor portions connected to the through-hole wirings around the heat equalizing plate portion.
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