JP2009206186A - Light emitting device - Google Patents

Light emitting device Download PDF

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Publication number
JP2009206186A
JP2009206186A JP2008044862A JP2008044862A JP2009206186A JP 2009206186 A JP2009206186 A JP 2009206186A JP 2008044862 A JP2008044862 A JP 2008044862A JP 2008044862 A JP2008044862 A JP 2008044862A JP 2009206186 A JP2009206186 A JP 2009206186A
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light
led chips
substrate
led chip
period
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Kenichiro Tanaka
健一郎 田中
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Panasonic Electric Works Co Ltd
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Panasonic Electric Works Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding

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Abstract

<P>PROBLEM TO BE SOLVED: To provide a light emitting device which has high reliability and is made reduced in cost. <P>SOLUTION: The light emitting device includes a package (not illustrated) which includes one optical detecting element 4 detecting light beams emitted from a plurality of LED chips 1a to 1d differing in light emission color and extracts mixed-color light of the light beams from the respective LED chips 1a to 1d, switching elements Qa to Qd inserted into feed lines to the respective LED chips 1a to 1d, and a control unit 10 which performs PWM control over the respective switching elements Qa to Qd on the basis of the output of the optical detecting element 4 to individually control optical outputs of the respective LED chips 1a to 1d. The control unit 10 generates a PWM signal to be supplied to the respective switching elements Qa to Qd so that a mixed-color period Ta wherein all the LED chips 1a to 1d illuminate and a monitoring period Tu wherein only one LED chip to be monitored using the optical detecting element 4 illuminate may alternate in time series and LED chips which illuminate to be monitored may change in sequence. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

本発明は、発光色の異なる複数個のＬＥＤチップ（発光ダイオードチップ）を用いた発光装置に関するものである。   The present invention relates to a light emitting device using a plurality of LED chips (light emitting diode chips) having different emission colors.

従来から、図４および図５に示すように、発光色の異なる４個のＬＥＤチップ１ａ，１ｂ，１ｃ，１ｄが実装されるとともに各ＬＥＤチップ１ａ〜１ｄから放射される光を１対１で各別に検出するフォトダイオードからなる４つの光検出素子４が設けられてなり各ＬＥＤチップ１ａ〜１ｄからの光の混色光が取り出されるパッケージ２’を備えた発光装置が提案されている（特許文献１）。   Conventionally, as shown in FIGS. 4 and 5, four LED chips 1a, 1b, 1c, and 1d having different emission colors are mounted, and light emitted from each LED chip 1a to 1d is 1: 1. There has been proposed a light-emitting device including a package 2 ′ provided with four photodetecting elements 4 each consisting of a photodiode to be detected, and from which mixed color light from the LED chips 1a to 1d is taken out (Patent Literature). 1).

上述のパッケージ２’は、各ＬＥＤチップ１ａ〜１ｄが収納される収納凹所２ｂが一表面に形成され各ＬＥＤチップ１ａ〜１ｄが実装される実装基板２ａと、実装基板２ａの上記一表面側で収納凹所２ｂを閉塞する形で配設された透光性部材３とで構成されており、収納凹所２ｂ内が各ＬＥＤチップ１ａ〜１ｄを封止した透光性封止材（例えば、シリコーン樹脂など）からなる封止部５により充実されている。   The above-described package 2 ′ includes a mounting substrate 2a on which a housing recess 2b in which each LED chip 1a to 1d is stored is formed on one surface and each LED chip 1a to 1d is mounted, and the one surface side of the mounting substrate 2a. And a translucent member 3 disposed so as to close the housing recess 2b, and the inside of the housing recess 2b seals the LED chips 1a to 1d (for example, , Silicone resin, etc.).

ここにおいて、実装基板２ａは、シリコン基板２０ａを用いて形成され各ＬＥＤチップ１ａ〜１ｄが実装されるベース基板２０と、シリコン基板４０ａを用いて形成され光取出窓４１が形成されるとともに各光検出素子４が形成された光検出素子形成基板４０と、シリコン基板３０ａを用いて形成されてなり光取出窓４１に連通する開口窓３１が形成されベース基板２０と光検出素子形成基板４０との間に介在する配光用基板３０とで構成されており、各ＬＥＤチップ１ａ〜１ｄはベース基板２０に形成された貫通孔配線２４を介して外部接続用電極２７ａ，２７ａと電気的に接続され、各光検出素子４は配光用基板３０に形成された貫通孔配線３４およびベース基板２０に形成された貫通孔配線２４を介して外部接続用電極２７ｂ，２７ｂと電気的に接続されている。   Here, the mounting substrate 2a is formed using the silicon substrate 20a, the base substrate 20 on which the LED chips 1a to 1d are mounted, the silicon substrate 40a, and the light extraction window 41 is formed. A light detection element forming substrate 40 on which the detection element 4 is formed, and an opening window 31 formed using the silicon substrate 30a and communicating with the light extraction window 41 is formed, and the base substrate 20 and the light detection element formation substrate 40 are formed. The LED chips 1a to 1d are electrically connected to the external connection electrodes 27a and 27a through the through-hole wirings 24 formed in the base substrate 20, respectively. Each photodetecting element 4 is connected to the external connection electrodes 27b and 27b through the through-hole wiring 34 formed in the light distribution substrate 30 and the through-hole wiring 24 formed in the base substrate 20. It is electrically connected.

ところで、上述のパッケージ２’は、上述のように、光検出素子形成基板４０に各発光色のＬＥＤチップ１ａ〜１ｄそれぞれから放射された光を各別に検出する４つの光検出素子４が設けられており、４つの光検出素子４と互いに発光色の異なる４つのＬＥＤチップ１ａ〜１ｄとを１対１で対応させるために、ベース基板２０と配光用基板３０とで囲まれた内部空間を各発光色のＬＥＤチップ１ａ〜１ｄそれぞれの収納空間に区画し各ＬＥＤチップ１ａ〜１ｄそれぞれから放射された光が２つ以上の光検出素子４の受光面へ入射するのを阻止する十字状の遮光部３９が、配光用基板３０に連続一体に形成されている。   By the way, as described above, the above-described package 2 ′ is provided with the four light detection elements 4 that individually detect the light emitted from the LED chips 1 a to 1 d of the respective emission colors on the light detection element forming substrate 40. An internal space surrounded by the base substrate 20 and the light distribution substrate 30 is made to correspond one-to-one with the four light detection elements 4 and the four LED chips 1a to 1d having different emission colors. A cross-shaped section that divides the light-emitting LED chips 1a to 1d into storage spaces and blocks light emitted from the LED chips 1a to 1d from entering the light receiving surfaces of the two or more light detection elements 4. The light shielding portion 39 is formed continuously and integrally on the light distribution substrate 30.

上述の発光装置では、パッケージ２’を実装する回路基板を設けて、当該回路基板に、各ＬＥＤチップ１ａ〜１ｄを駆動する駆動回路と、各光検出素子４により検出される光強度がそれぞれの目標値に保たれるように駆動回路から各発光色のＬＥＤチップ１ａ〜１ｄに流れる電流をフィードバック制御する制御回路とを設けることにより、各光検出素子４それぞれの出力に基づいて各発光色のＬＥＤチップ１ａ〜１ｄの光出力を各別に制御することができ、各発光色ごとのＬＥＤチップ１ａ〜１ｄの光出力の経時変化の違いなどによらず混色光（ここでは、白色光）の光色や色温度の精度を向上することができ、信頼性が向上する。
特開２００７−２９４８３４号公報 In the above-described light emitting device, a circuit board on which the package 2 ′ is mounted is provided, and the light intensity detected by each of the light detection elements 4 and the drive circuit that drives the LED chips 1a to 1d is provided on the circuit board. By providing a control circuit that feedback-controls the current that flows from the drive circuit to the LED chips 1a to 1d of the respective emission colors so as to be maintained at the target value, the emission color of each emission color is determined based on the output of each of the photodetector elements 4. The light output of the LED chips 1a to 1d can be controlled separately, and light of mixed color light (here, white light) regardless of the temporal change in the light output of the LED chips 1a to 1d for each emission color. The accuracy of color and color temperature can be improved, and the reliability is improved.
JP 2007-294834 A

しかしながら、図４および図５に示した構成のパッケージ２’と、上記駆動回路と、上記制御回路とを備えた発光装置では、パッケージ２’に複数の光検出素子４を設けるとともに遮光部３９を設ける必要があり、パッケージ２’の構造が煩雑になり、パッケージ２’の小型化が制限されるとともにコストが高くなってしまう。また、遮光部３９での光損失も発生し外部への光取出し効率が低下してしまう。   However, in the light emitting device including the package 2 ′ having the configuration shown in FIGS. 4 and 5, the drive circuit, and the control circuit, a plurality of light detection elements 4 are provided in the package 2 ′ and the light shielding portion 39 is provided. Therefore, the structure of the package 2 ′ becomes complicated, and downsizing of the package 2 ′ is restricted and the cost is increased. Further, light loss at the light shielding portion 39 also occurs, and the light extraction efficiency to the outside is reduced.

本発明は上記事由に鑑みて為されたものであり、その目的は、信頼性が高く且つ低コスト化が可能な発光装置を提供することにある。   The present invention has been made in view of the above-described reasons, and an object of the present invention is to provide a light-emitting device that is highly reliable and can be reduced in cost.

請求項１の発明は、発光色の異なる複数個のＬＥＤチップが実装されるとともに各ＬＥＤチップから放射される光を検出する１つの光検出素子が設けられてなり各ＬＥＤチップからの光の混色光が取り出されるパッケージと、各ＬＥＤチップそれぞれへの給電路に挿入されたスイッチング素子と、光検出素子の出力に基づいて各スイッチング素子それぞれをＰＷＭ制御することで各ＬＥＤチップの光出力を各別に調節する制御部とを備え、制御部は、全てのＬＥＤチップが点灯する混色期間と光検出素子によるモニタリング対象となる１個のＬＥＤチップのみが点灯するモニタリング用期間とが時系列的に交互に現われモニタリング対象として点灯するＬＥＤチップが順次切り替わるように各スイッチング素子それぞれへ与えるＰＷＭ信号を生成することを特徴とする。   According to the first aspect of the present invention, a plurality of LED chips having different emission colors are mounted, and one light detection element for detecting light emitted from each LED chip is provided. The light output of each LED chip is individually controlled by PWM control of each switching element based on the package from which light is extracted, the switching element inserted in the power supply path to each LED chip, and the output of the light detection element A control unit that adjusts, and the control unit alternately alternates the color mixture period in which all the LED chips are lit and the monitoring period in which only one LED chip to be monitored by the light detection element is lit in time series. The PWM signal that is given to each switching element so that the LED chips that appear and are lit as monitoring targets are switched sequentially. Characterized in that it formed.

この発明によれば、制御部が、全てのＬＥＤチップが点灯する混色期間と光検出素子によるモニタリング対象となる１個のＬＥＤチップのみが点灯するモニタリング用期間とが時系列的に交互に現われモニタリング対象として点灯するＬＥＤチップが順次切り替わるように各スイッチング素子それぞれへ与えるＰＷＭ信号を生成するので、パッケージに１つの光検出素子を設けるだけで各発光色のＬＥＤチップそれぞれの光を精度良く検出することができるとともに混色光の光色や色温度の精度を向上することができるから、信頼性が高く且つ低コスト化が可能になる。   According to this invention, the control unit monitors the color mixture period in which all the LED chips are turned on and the monitoring period in which only one LED chip to be monitored by the light detection element is turned on alternately in time series. Since a PWM signal to be supplied to each switching element is generated so that the LED chips that are lit as a target are sequentially switched, it is possible to accurately detect the light of each LED chip of each emission color only by providing one light detection element in the package. In addition, the accuracy of the light color and color temperature of the mixed color light can be improved, so that the reliability is high and the cost can be reduced.

請求項２の発明は、請求項１の発明において、制御部は、少なくとも混色期間とモニタリング用期間とを含む単位期間においてモニタリング対象のＬＥＤチップの点灯開始タイミングを他のＬＥＤチップの点灯開始タイミングよりも早くすることでモニタリング用期間が周期的に現われるように各ＰＷＭ信号を生成することを特徴とする。   According to a second aspect of the present invention, in the first aspect of the invention, the control unit determines the lighting start timing of the LED chip to be monitored from the lighting start timing of other LED chips in a unit period including at least the color mixture period and the monitoring period. Each PWM signal is generated so that the monitoring period appears periodically by making it earlier.

この発明によれば、前記制御部において前記光検出素子の出力を入力するタイミング制御が容易になり、より信頼性が向上する。   According to the present invention, the timing control for inputting the output of the light detection element in the control unit is facilitated, and the reliability is further improved.

請求項１の発明では、信頼性が高く且つ低コスト化が可能になるという効果がある。   According to the first aspect of the invention, there is an effect that the reliability is high and the cost can be reduced.

以下、本実施形態の発光装置について図１〜図３に基づいて説明する。   Hereinafter, the light emitting device of the present embodiment will be described with reference to FIGS.

本実施形態の発光装置は、発光色の異なる複数個（本実施形態では、４個）のＬＥＤチップ１ａ〜１ｄが実装されるとともに各ＬＥＤチップ１ａ〜１ｄから放射される光を検出する１つの光検出素子４が設けられてなり各ＬＥＤチップ１ａ〜１ｄからの光の混色光が取り出されるパッケージ２（図２および図３参照）と、各ＬＥＤチップ１ａ〜１ｄそれぞれへの給電路に挿入されたＭＯＳＦＥＴからなるスイッチング素子Ｑａ〜Ｑｄと、光検出素子４の出力に基づいて各スイッチング素子Ｑａ〜ＱｄそれぞれをＰＷＭ制御することで各ＬＥＤチップ１ａ〜１ｄの光出力を各別に調節する制御部１０とを備えている。   The light emitting device according to the present embodiment includes a plurality of (four in the present embodiment) LED chips 1a to 1d having different emission colors, and detects light emitted from the LED chips 1a to 1d. A package 2 (see FIGS. 2 and 3) that is provided with a light detection element 4 and extracts mixed color light from the LED chips 1a to 1d, and is inserted into a power feeding path to each of the LED chips 1a to 1d. The control unit 10 that adjusts the light output of each of the LED chips 1a to 1d by PWM-controlling each of the switching elements Qa to Qd based on the output of the switching elements Qa to Qd composed of the MOSFETs and the light detection element 4. And.

以下では、まずパッケージ２について説明した後、制御部１０について説明する。   Hereinafter, the package 2 will be described first, and then the control unit 10 will be described.

パッケージ２は、図２および図３に示すように、各ＬＥＤチップ１ａ〜１ｄが収納される収納凹所２ｂが一表面に形成され各ＬＥＤチップ１ａ〜１ｄが実装される実装基板２ａと、実装基板２ａの上記一表面側で収納凹所２ｂを閉塞する形で配設された透光性部材３とで構成されており、収納凹所２ｂ内が各ＬＥＤチップ１ａ〜１ｄを封止した透光性材料（例えば、シリコーン樹脂、アクリル樹脂、エポキシ樹脂、ポリカーボネート樹脂、ガラスなど）からなる封止部５により充実されている。なお、透光性部材３は、必ずしも設ける必要はなく、また、透光性部材３の代わりに、レンズなどの光学部材を設けてもよい。   As shown in FIGS. 2 and 3, the package 2 includes a mounting substrate 2 a on which a housing recess 2 b in which the LED chips 1 a to 1 d are stored is formed on one surface, and the LED chips 1 a to 1 d are mounted. The light-transmitting member 3 is disposed so as to close the housing recess 2b on the one surface side of the substrate 2a, and the inside of the storage recess 2b seals the LED chips 1a to 1d. It is enriched by a sealing portion 5 made of a light material (for example, silicone resin, acrylic resin, epoxy resin, polycarbonate resin, glass, etc.). The translucent member 3 is not necessarily provided, and an optical member such as a lens may be provided instead of the translucent member 3.

上述の４個のＬＥＤチップ１ａ〜１ｄとしては、それぞれ、青色光を放射するＬＥＤチップ１ａ、緑色光を放射するＬＥＤチップ１ｂ、黄色光を放射するＬＥＤチップ１ｃ、赤色光を放射するＬＥＤチップ１ｄを採用しており、青色光と緑色光と黄色光と赤色光の混色光として白色光を得ることができる。ただし、各ＬＥＤチップ１ａ〜１ｄの発光色は特に限定するものではなく、所望の混色光に応じて適宜選択すればよい。   The four LED chips 1a to 1d described above include an LED chip 1a that emits blue light, an LED chip 1b that emits green light, an LED chip 1c that emits yellow light, and an LED chip 1d that emits red light. And white light can be obtained as mixed light of blue light, green light, yellow light and red light. However, the emission colors of the LED chips 1a to 1d are not particularly limited, and may be appropriately selected according to desired mixed color light.

また、実装基板２ａは、各ＬＥＤチップ１ａ〜１ｄが一表面側に実装される矩形板状のベース基板２０と、ベース基板２０の上記一表面側に対向配置され円形状の光取出窓４１が形成されるとともに光検出素子４が形成された光検出素子形成基板４０と、ベース基板２０と光検出素子形成基板４０との間に介在し光取出窓４１に連通する矩形状の開口窓３１が形成された配光用基板３０とで構成されている。ここで、実装基板２ａは、光検出素子形成基板４０において配光用基板３０の開口窓３１上に張り出した部位が、実装基板２ａの上記一表面側において収納凹所２ｂの周部から内方へ突出した庇状の突出部２ｃを構成しており、当該突出部２ｃに光検出素子４が形成されている。なお、光取出窓４１の開口形状は円形状に限らず、例えば、矩形状でもよい。   The mounting substrate 2a includes a rectangular plate-like base substrate 20 on which the LED chips 1a to 1d are mounted on one surface side, and a circular light extraction window 41 arranged to face the one surface side of the base substrate 20. A light detection element forming substrate 40 formed with the light detection element 4 and a rectangular opening window 31 interposed between the base substrate 20 and the light detection element formation substrate 40 and communicating with the light extraction window 41 are provided. The light distribution substrate 30 is formed. Here, in the mounting substrate 2a, the portion of the light detection element forming substrate 40 that protrudes above the opening window 31 of the light distribution substrate 30 is inward from the peripheral portion of the housing recess 2b on the one surface side of the mounting substrate 2a. And a photodetecting element 4 is formed on the protruding portion 2c. The opening shape of the light extraction window 41 is not limited to a circular shape, and may be a rectangular shape, for example.

ここにおいて、ベース基板２０、配光用基板３０および光検出素子形成基板４０の外周形状は矩形状であり、配光用基板３０および光検出素子形成基板４０はベース基板２０と同じ外形寸法に形成されている。また、光検出素子形成基板４０の厚み寸法はベース基板２０および配光用基板３０の厚み寸法に比べて小さく設定されている。   Here, the outer peripheral shapes of the base substrate 20, the light distribution substrate 30, and the light detection element formation substrate 40 are rectangular, and the light distribution substrate 30 and the light detection element formation substrate 40 are formed to have the same outer dimensions as the base substrate 20. Has been. Further, the thickness dimension of the light detection element forming substrate 40 is set smaller than the thickness dimension of the base substrate 20 and the light distribution substrate 30.

上述のベース基板２０、配光用基板３０および光検出素子形成基板４０は、それぞれ、導電形がｎ形で主表面が（１００）面のシリコン基板２０ａ，３０ａ，４０ａを用いて形成してあり、配光用基板３０の開口窓３１の内側面は、アルカリ系溶液（例えば、ＴＭＡＨ水溶液、ＫＯＨ水溶液など）を用いた異方性エッチングにより形成された（１１１）面により構成されており（つまり、配光用基板３０は、開口窓３１の開口面積がベース基板２０から離れるにつれて徐々に大きくなっており）、ＬＥＤチップ１ａ〜１ｄから側方へ放射された光を前方（突出部２ｃ側）へ反射するミラーを構成している。   The base substrate 20, the light distribution substrate 30 and the light detection element formation substrate 40 described above are formed by using silicon substrates 20a, 30a and 40a having an n-type conductivity and a (100) main surface, respectively. The inner side surface of the opening window 31 of the light distribution substrate 30 is constituted by a (111) surface formed by anisotropic etching using an alkaline solution (for example, TMAH aqueous solution, KOH aqueous solution, etc.) (that is, In the light distribution substrate 30, the opening area of the opening window 31 gradually increases as the distance from the base substrate 20 increases), and the light emitted from the LED chips 1a to 1d to the side is forward (on the protruding portion 2c side). This constitutes a mirror that reflects to the surface.

ベース基板２０は、シリコン基板２０ａの一表面側（図２（ａ）における上面側）に、ＬＥＤチップ１ａ〜１ｄの両電極それぞれと電気的に接続される２つ１組の導体パターン２５ａ，２５ａが４組形成されるとともに、配光用基板３０に形成された２つの貫通孔配線３４，３４を介して光検出素子４と電気的に接続される２つ導体パターン２５ｂ，２５ｂが形成されており、各導体パターン２５ａ，２５ａ，２５ｂ，２５ｂとシリコン基板２０ａの他表面側（図２（ａ）における下面側）に形成された各外部接続用電極２７ａ，２７ａ，２７ｂ，２７ｂとがそれぞれ貫通孔配線２４を介して電気的に接続されている。また、ベース基板２０は、シリコン基板２０ａの上記一表面側に、配光用基板３０と接合するための接合用金属層２９も形成されている。   The base substrate 20 has a pair of conductor patterns 25a and 25a that are electrically connected to both electrodes of the LED chips 1a to 1d on one surface side (the upper surface side in FIG. 2A) of the silicon substrate 20a. Are formed, and two conductor patterns 25b and 25b that are electrically connected to the light detecting element 4 through two through-hole wirings 34 and 34 formed on the light distribution substrate 30 are formed. Each of the conductor patterns 25a, 25a, 25b, and 25b and the external connection electrodes 27a, 27a, 27b, and 27b formed on the other surface side (the lower surface side in FIG. 2A) of the silicon substrate 20a penetrate each other. They are electrically connected through the hole wiring 24. The base substrate 20 is also formed with a bonding metal layer 29 for bonding to the light distribution substrate 30 on the one surface side of the silicon substrate 20a.

本実施形態におけるＬＥＤチップ１ａ〜１ｄは、結晶成長用基板として導電性基板を用い厚み方向の両面に電極（図示せず）が形成された可視光ＬＥＤチップである。そこで、ベース基板２０は、各ＬＥＤチップ１ａ〜１ｄが電気的に接続される２つの導体パターン２５ａ，２５ａのうちの一方の導体パターン２５ａを、ＬＥＤチップ１ａ〜１ｄがダイボンディングされる矩形状のダイパッド部２５ａａと、ダイパッド部２５ａａに連続一体に形成され貫通孔配線２４との接続部位となる引き出し配線部２５ａｂとで構成してある。要するに、ＬＥＤチップ１ａ〜１ｄは、上記一方の導体パターン２５ａのダイパッド部２５ａａにダイボンディングされており、ダイパッド部２５ａａ側の電極がダイパッド部２５ａａに接合されて電気的に接続され、光取り出し面側の電極がボンディングワイヤ１４を介して他方の導体パターン２５ａと電気的に接続されている。   The LED chips 1a to 1d in the present embodiment are visible light LED chips in which a conductive substrate is used as a crystal growth substrate and electrodes (not shown) are formed on both surfaces in the thickness direction. Therefore, the base substrate 20 has a rectangular shape in which one of the two conductor patterns 25a and 25a to which the LED chips 1a to 1d are electrically connected is die-bonded to the LED chip 1a to 1d. A die pad portion 25aa and a lead-out wiring portion 25ab that is continuously formed integrally with the die pad portion 25aa and serves as a connection portion with the through-hole wiring 24 are configured. In short, the LED chips 1a to 1d are die-bonded to the die pad portion 25aa of the one conductor pattern 25a, and the electrodes on the die pad portion 25aa side are joined and electrically connected to the die pad portion 25aa, and the light extraction surface side The electrode is electrically connected to the other conductor pattern 25a through the bonding wire.

また、ベース基板２０は、シリコン基板２０ａの上記他表面側における各ダイパッド部２５ａａそれぞれの投影領域に、シリコン基板２０ａよりも熱伝導率の高い金属材料からなる矩形状の放熱用パッド部２８が形成されており、シリコン基板２０ａの厚み方向において重なるダイパッド部２５ａａと放熱用パッド部２８とがシリコン基板２０ａよりも熱伝導率の高い金属材料（例えば、Ｃｕなど）からなる複数の円柱状のサーマルビア２６を介して熱的に結合されており、ＬＥＤチップ１ａ〜１ｄで発生した熱が各サーマルビア２６および放熱用パッド部２８を介して放熱されるようになっている。   Further, in the base substrate 20, a rectangular heat radiation pad portion 28 made of a metal material having a higher thermal conductivity than the silicon substrate 20a is formed in the projection region of each die pad portion 25aa on the other surface side of the silicon substrate 20a. A plurality of cylindrical thermal vias in which the die pad portion 25aa and the heat dissipation pad portion 28 that overlap in the thickness direction of the silicon substrate 20a are made of a metal material (for example, Cu) having a higher thermal conductivity than the silicon substrate 20a. The heat generated by the LED chips 1 a to 1 d is radiated through the thermal vias 26 and the heat radiating pad portions 28.

ところで、ベース基板２０は、シリコン基板２０ａに、上述の各貫通孔配線２４それぞれが内側に形成される複数の貫通孔２２ａと、上述の各サーマルビア２６それぞれが内側に形成される複数の貫通孔２２ｂとが厚み方向に貫設され、シリコン基板２０ａの上記一表面および上記他表面と各貫通孔２２ａ，２２ｂの内面とに跨って熱酸化膜（シリコン酸化膜）からなる絶縁膜２３が形成されており、各導体パターン２５ａ，２５ａ，２５ｂ，２５ｂ、接合用金属層２９、各外部接続用電極２７ａ，２７ａ，２７ｂ，２７ｂ、各放熱用パッド部２８、各貫通孔配線２４および各サーマルビア２６がシリコン基板２０ａと電気的に絶縁されている。   By the way, the base substrate 20 has a plurality of through holes 22a in which each of the above-described through-hole wirings 24 is formed inside and a plurality of through-holes in which each of the above-described thermal vias 26 is formed in the silicon substrate 20a. 22b is formed in the thickness direction, and an insulating film 23 made of a thermal oxide film (silicon oxide film) is formed across the one surface and the other surface of the silicon substrate 20a and the inner surfaces of the through holes 22a and 22b. Each conductive pattern 25a, 25a, 25b, 25b, bonding metal layer 29, each external connection electrode 27a, 27a, 27b, 27b, each heat dissipation pad 28, each through-hole wiring 24, and each thermal via 26 Is electrically insulated from the silicon substrate 20a.

ここにおいて、各導体パターン２５ａ，２５ａ，２５ｂ，２５ｂ、接合用金属層２９、各外部接続用電極２７ａ，２７ａ，２７ｂ，２７ｂ、各放熱用パッド部２８は、絶縁膜２３上に形成されたＴｉ膜と当該Ｔｉ膜上に形成されたＡｕ膜との積層膜により構成されており、シリコン基板２０ａの上記一表面側の各導体パターン２５ａ，２５ａ，２５ｂ，２５ｂ、接合用金属層２９が同時に形成され、シリコン基板２０ａの上記他表面側の各外部接続用電極２７ａ，２７ａ，２７ｂ，２７ｂ、各放熱用パッド部２８が同時に形成されている。なお、本実施形態では、絶縁膜２３上のＴｉ膜の膜厚を１５〜５０ｎｍ、Ｔｉ膜上のＡｕ膜の膜厚を５００ｎｍに設定してあるが、これらの数値は一例であって特に限定するものではない。また、各Ａｕ膜の材料は、純金に限らず不純物を添加したものでもよい。また、各Ａｕ膜と絶縁膜２３との間に密着性改善用の密着層としてＴｉ膜を介在させてあるが、密着層の材料はＴｉに限らず、例えば、Ｃｒ、Ｎｂ、Ｚｒ、ＴｉＮ、ＴａＮなどでもよい。また、貫通孔配線２４およびサーマルビア２６の材料としては、Ｃｕを採用しているが、Ｃｕに限らず、例えば、Ｎｉ、Ａｌなどを採用してもよい。   Here, each conductor pattern 25a, 25a, 25b, 25b, bonding metal layer 29, each external connection electrode 27a, 27a, 27b, 27b, and each heat radiation pad portion 28 are formed on the insulating film 23. Each of the conductor patterns 25a, 25a, 25b, 25b on the one surface side of the silicon substrate 20a and the bonding metal layer 29 are formed at the same time by a laminated film of a film and an Au film formed on the Ti film. Then, the external connection electrodes 27a, 27a, 27b, 27b and the heat radiation pad portions 28 on the other surface side of the silicon substrate 20a are formed at the same time. In this embodiment, the thickness of the Ti film on the insulating film 23 is set to 15 to 50 nm, and the thickness of the Au film on the Ti film is set to 500 nm. However, these numerical values are only examples and are particularly limited. Not what you want. Further, the material of each Au film is not limited to pure gold, and may be one added with impurities. In addition, although a Ti film is interposed as an adhesion layer for improving adhesion between each Au film and the insulating film 23, the material of the adhesion layer is not limited to Ti, for example, Cr, Nb, Zr, TiN, TaN or the like may be used. Further, although Cu is adopted as the material of the through-hole wiring 24 and the thermal via 26, it is not limited to Cu, and for example, Ni, Al, etc. may be adopted.

配光用基板３０は、シリコン基板３０ａの一表面側（図２（ａ）における下面側）に、ベース基板２０の２つの導体パターン２５ｂ，２５ｂと接合されて電気的に接続される２つの導体パターン（図示せず）が形成されるとともに、ベース基板２０の接合用金属層２９と接合される接合用金属層３６が形成されている。また、配光用基板３０は、シリコン基板３０ａの他表面側（図２（ａ）における上面側）に、貫通孔配線３４，３４を介して上記一表面側の２つの導体パターンと電気的に接続される２つの導体パターン３７，３７が形成されるとともに、光検出素子形成基板４０と接合するための接合用金属層３８が形成されている。なお、配光用基板３０は、開口窓３１の内側面にＬＥＤチップ１ａ〜１ｄから放射される光に対する反射率の高い金属材料からなる反射膜などを設けてもよい。   The light distribution substrate 30 has two conductors bonded to and electrically connected to the two conductor patterns 25b and 25b of the base substrate 20 on one surface side (the lower surface side in FIG. 2A) of the silicon substrate 30a. A pattern (not shown) is formed, and a bonding metal layer 36 to be bonded to the bonding metal layer 29 of the base substrate 20 is formed. Further, the light distribution substrate 30 is electrically connected to the two conductor patterns on the one surface side on the other surface side (the upper surface side in FIG. 2A) of the silicon substrate 30a through the through-hole wirings 34, 34. Two conductor patterns 37 and 37 to be connected are formed, and a bonding metal layer 38 for bonding to the light detection element forming substrate 40 is formed. The light distribution substrate 30 may be provided with a reflection film made of a metal material having a high reflectance with respect to the light emitted from the LED chips 1 a to 1 d on the inner surface of the opening window 31.

また、配光用基板３０は、上述の２つの貫通孔配線３４それぞれが内側に形成される２つの貫通孔３２がシリコン基板３０ａの厚み方向に貫設され、シリコン基板３０ａの上記一表面および上記他表面と各貫通孔３２の内面とに跨って熱酸化膜（シリコン酸化膜）からなる絶縁膜３３が形成されており、上記一表面側の各導体パターンおよび上記他表面側の各導体パターン３７，３７および各接合用金属層３６，３８がシリコン基板３０ａと電気的に絶縁されている。ここにおいて、上記一表面側の各導体パターンおよび上記他表面側の各導体パターン３７，３７および各接合用金属層３６，３８は、絶縁膜３３上に形成されたＴｉ膜と当該Ｔｉ膜上に形成されたＡｕ膜との積層膜により構成されており、シリコン基板３０ａの上記一表面側の各導体パターンおよび接合用金属層３６が同時に形成され、シリコン基板３０ａの上記他表面側の各導体パターン３７，３７および接合用金属層３８が同時に形成されている。なお、本実施形態では、絶縁膜３３上のＴｉ膜の膜厚を１５〜５０ｎｍ、Ｔｉ膜上のＡｕ膜の膜厚を５００ｎｍに設定してあるが、これらの数値は一例であって特に限定するものではない。ここにおいて、各Ａｕ膜の材料は、純金に限らず不純物を添加したものでもよい。また、各Ａｕ膜と絶縁膜３３との間に密着性改善用の密着層としてＴｉ膜を介在させてあるが、密着層の材料はＴｉに限らず、例えば、Ｃｒ、Ｎｂ、Ｚｒ、ＴｉＮ、ＴａＮなどでもよい。また、貫通孔配線３４の材料としては、Ｃｕを採用しているが、Ｃｕに限らず、例えば、Ｎｉ、Ａｌなどを採用してもよい。   Further, the light distribution substrate 30 has two through-holes 32 in which the above-described two through-hole wirings 34 are respectively formed in the thickness direction of the silicon substrate 30a. An insulating film 33 made of a thermal oxide film (silicon oxide film) is formed across the other surface and the inner surface of each through-hole 32, and each conductor pattern on the one surface side and each conductor pattern 37 on the other surface side. , 37 and the bonding metal layers 36, 38 are electrically insulated from the silicon substrate 30a. Here, the conductor patterns on the one surface side, the conductor patterns 37 and 37 on the other surface side, and the bonding metal layers 36 and 38 are formed on the Ti film formed on the insulating film 33 and the Ti film, respectively. Each conductive pattern on the one surface side of the silicon substrate 30a and the bonding metal layer 36 are formed at the same time, and each conductor pattern on the other surface side of the silicon substrate 30a is formed by a laminated film with the formed Au film. 37 and 37 and the bonding metal layer 38 are formed simultaneously. In this embodiment, the thickness of the Ti film on the insulating film 33 is set to 15 to 50 nm, and the thickness of the Au film on the Ti film is set to 500 nm. However, these numerical values are only examples and are particularly limited. Not what you want. Here, the material of each Au film is not limited to pure gold, and may be added with impurities. Further, although a Ti film is interposed as an adhesion improving layer for adhesion between each Au film and the insulating film 33, the material of the adhesion layer is not limited to Ti, for example, Cr, Nb, Zr, TiN, TaN or the like may be used. Further, although Cu is adopted as the material of the through-hole wiring 34, it is not limited to Cu, and for example, Ni, Al or the like may be adopted.

光検出素子形成基板４０は、シリコン基板４０ａの一表面側（図２（ａ）における下面側）に、配光用基板３０の２つの導体パターン３７，３７と接合されて電気的に接続される２つの導体パターン（図示せず）が形成されるとともに、配光用基板３０の接合用金属層３８と接合される接合用金属層４８が形成されている。ここにおいて、光検出素子形成基板４０の光検出素子４は、ｎ形のシリコン基板４０ａにｐ形領域４ａを形成することにより形成されたフォトダイオードからなり、光検出素子形成基板４０に形成された２つの導体パターンの一方の導体パターンがフォトダイオードのｐ形領域４ａに電気的に接続され、他方の導体パターンがｎ形領域（シリコン基板４０ａの一部）ｂに電気的に接続されている。本実施形態におけるパッケージ２は、実装基板２ａの平面視における外周形状が正方形状であって、収納凹所２ｂの開口形状が正方形状であり、光検出素子形成基板４０は、光取出窓４１の開口形状が円形状であり、実装基板２ａの収納凹所２ｂの投影領域へ張り出した突出部２ｃにｐ形領域４ａが形成されている。   The light detection element forming substrate 40 is joined to and electrically connected to the two conductor patterns 37 and 37 of the light distribution substrate 30 on one surface side (the lower surface side in FIG. 2A) of the silicon substrate 40a. Two conductor patterns (not shown) are formed, and a bonding metal layer 48 bonded to the bonding metal layer 38 of the light distribution substrate 30 is formed. Here, the light detection element 4 of the light detection element formation substrate 40 is formed of a photodiode formed by forming a p-type region 4a on an n-type silicon substrate 40a, and is formed on the light detection element formation substrate 40. One of the two conductor patterns is electrically connected to the p-type region 4a of the photodiode, and the other conductor pattern is electrically connected to the n-type region (a part of the silicon substrate 40a) b. In the package 2 according to the present embodiment, the outer peripheral shape of the mounting substrate 2a in a plan view is a square shape, the opening shape of the housing recess 2b is a square shape, and the photodetecting element forming substrate 40 includes the light extraction window 41. The opening shape is a circular shape, and a p-type region 4a is formed in the protruding portion 2c that protrudes to the projection region of the housing recess 2b of the mounting substrate 2a.

ここで、光検出素子４を構成するフォトダイオードのｐ形領域４ａは、光検出素子形成基板４０の円形状の光取出窓４１を取り囲むように形成されており（光取出窓４１の周部において収納凹所２ｂに臨む表面側に受光面が形成されており）、図２（ｂ）から分かるように実装基板２ａへの投影視において全てのＬＥＤチップ１ａ〜１ｄを取り囲むように形成されている。   Here, the p-type region 4a of the photodiode constituting the light detection element 4 is formed so as to surround the circular light extraction window 41 of the light detection element forming substrate 40 (at the periphery of the light extraction window 41). A light receiving surface is formed on the surface side facing the housing recess 2b), and as can be seen from FIG. 2B, it is formed so as to surround all the LED chips 1a to 1d in a projection view on the mounting substrate 2a. .

また、光検出素子形成基板４０は、シリコン基板４０ａの上記一表面側にシリコン酸化膜からなる絶縁膜４３が形成されており、当該絶縁膜４３がフォトダイオードの反射防止膜を兼ねている。また、光検出素子形成基板４０は、上記一方の導体パターンが、絶縁膜４３に形成した第１のコンタクトホール（図示せず）を通してｐ形領域４ａと電気的に接続され、上記他方の導体パターンが絶縁膜４３に形成した第２のコンタクトホール（図示せず）を通してｎ形領域４ｂと電気的に接続されている。ここにおいて、各導体パターンおよび接合用金属層４８は、絶縁膜４３上に形成されたＴｉ膜と当該Ｔｉ膜上に形成されたＡｕ膜との積層膜により構成されており、同時に形成してある。なお、本実施形態では、絶縁膜４３上のＴｉ膜の膜厚を１５〜５０ｎｍ、Ｔｉ膜上のＡｕ膜の膜厚を５００ｎｍに設定してあるが、これらの数値は一例であって特に限定するものではない。ここにおいて、各Ａｕ膜の材料は、純金に限らず不純物を添加したものでもよい。また、各Ａｕ膜と絶縁膜４３との間に密着性改善用の密着層としてＴｉ膜を介在させてあるが、密着層の材料はＴｉに限らず、例えば、Ｃｒ、Ｎｂ、Ｚｒ、ＴｉＮ、ＴａＮなどでもよい。   Further, in the photodetecting element forming substrate 40, an insulating film 43 made of a silicon oxide film is formed on the one surface side of the silicon substrate 40a, and the insulating film 43 also serves as an antireflection film of the photodiode. In the photodetecting element forming substrate 40, the one conductor pattern is electrically connected to the p-type region 4a through a first contact hole (not shown) formed in the insulating film 43, and the other conductor pattern is formed. Is electrically connected to the n-type region 4b through a second contact hole (not shown) formed in the insulating film 43. Here, each conductor pattern and the bonding metal layer 48 are composed of a laminated film of a Ti film formed on the insulating film 43 and an Au film formed on the Ti film, and are formed at the same time. . In this embodiment, the thickness of the Ti film on the insulating film 43 is set to 15 to 50 nm, and the thickness of the Au film on the Ti film is set to 500 nm. However, these numerical values are only examples and are particularly limited. Not what you want. Here, the material of each Au film is not limited to pure gold, and may be added with impurities. Further, although a Ti film is interposed as an adhesion improving layer for adhesion between each Au film and the insulating film 43, the material of the adhesion layer is not limited to Ti, for example, Cr, Nb, Zr, TiN, TaN or the like may be used.

また、上述の透光性部材３は、透光性材料（例えば、シリコーン樹脂、アクリル樹脂、エポキシ樹脂、ポリカーボネート樹脂、ガラスなど）からなる透光性基板を用いて形成してある。ここで、透光性部材３は、実装基板２ａと同じ外周形状の矩形板状に形成されており、実装基板２ａ側とは反対の光取り出し面に、ＬＥＤチップ１ａ〜１ｄから放射された光の全反射を抑制する微細凹凸構造が形成されている。ここにおいて、透光性部材３の光取り出し面に形成する微細凹凸構造は、多数の微細な凹部が２次元周期構造を有するように形成されている。なお、上述の微細凹凸構造は、例えば、レーザ加工技術やエッチング技術やインプリントリソグラフィ技術などを利用して形成すればよい。また、微細凹凸構造の周期は、ＬＥＤチップ１ａ〜１ｄの発光ピーク波長の１／４〜１００倍程度の範囲で適宜設定すればよい。   Further, the above-described translucent member 3 is formed using a translucent substrate made of a translucent material (for example, silicone resin, acrylic resin, epoxy resin, polycarbonate resin, glass, or the like). Here, the translucent member 3 is formed in the same outer peripheral rectangular plate shape as the mounting substrate 2a, and the light emitted from the LED chips 1a to 1d on the light extraction surface opposite to the mounting substrate 2a side. A fine concavo-convex structure that suppresses total reflection is formed. Here, the fine concavo-convex structure formed on the light extraction surface of the translucent member 3 is formed such that many fine concave portions have a two-dimensional periodic structure. The fine concavo-convex structure described above may be formed using, for example, a laser processing technique, an etching technique, an imprint lithography technique, or the like. The period of the fine concavo-convex structure may be set as appropriate within a range of about 1/4 to 100 times the emission peak wavelength of the LED chips 1a to 1d.

上述のパッケージ２の形成にあたっては、光検出素子４、絶縁膜４３、各導体パターン、および接合用金属層４８が形成され且つ光取出窓４１が形成されていないシリコン基板４０ａと配光用基板３０とを接合する第１の接合工程を行った後、シリコン基板４０ａを所望の厚みまで研磨する研磨工程を行い、その後、誘導結合プラズマ（ＩＣＰ）型のドライエッチング装置などを用いてシリコン基板４０ａに光取出窓４１を形成する光取出窓形成工程を行うことで光検出素子形成基板４０を完成させてから、ＬＥＤチップ１ａ〜１ｄが搭載され各ボンディングワイヤ１４の結線が行われたベース基板２０（つまり、ＬＥＤチップ１ａ〜１ｄが実装されたベース基板２０）と配光用基板３０とを接合する第２の接合工程を行うことにより実装基板２ａを完成させ、続いて、実装基板２ａの収納凹所２ｂ内に透光性材料（例えば、シリコーン樹脂、アクリル樹脂、エポキシ樹脂、ポリカーボネート樹脂、ガラスなど）を充填して封止部５を形成する封止部形成工程、封止部形成工程の後で実装基板２ａと透光性部材３とを接合する第３の接合工程を行うようにすればよい。ここにおいて、第１の接合工程、第２の接合工程では、接合前に互いの接合表面へアルゴンのプラズマ若しくはイオンビーム若しくは原子ビームを真空中で照射して各接合表面の清浄化・活性化を行ってから、接合表面同士を接触させ、常温下で直接接合する常温接合法を採用しているが、常温接合法に限らず、ＡｕＳｎや半田などの低融点共晶材料を用いた接合法を採用してもよい。   In forming the package 2 described above, the silicon substrate 40a and the light distribution substrate 30 in which the light detection element 4, the insulating film 43, each conductor pattern, and the bonding metal layer 48 are formed and the light extraction window 41 is not formed. After performing the first bonding step, the silicon substrate 40a is polished to a desired thickness, and then the silicon substrate 40a is formed using an inductively coupled plasma (ICP) type dry etching apparatus or the like. After completing the light detection element forming substrate 40 by performing the light extraction window forming step of forming the light extraction window 41, the base substrate 20 (with the LED chips 1a to 1d mounted and the bonding wires 14 connected thereto) That is, the mounting substrate is obtained by performing the second bonding step of bonding the base substrate 20) on which the LED chips 1a to 1d are mounted and the light distribution substrate 30 to each other. 2a is completed, and subsequently, a sealing portion 5 is formed by filling a light-transmitting material (for example, silicone resin, acrylic resin, epoxy resin, polycarbonate resin, glass, etc.) in the housing recess 2b of the mounting substrate 2a. What is necessary is just to make it perform the 3rd joining process which joins the mounting substrate 2a and the translucent member 3 after the sealing part formation process to perform and the sealing part formation process. Here, in the first bonding step and the second bonding step, each bonding surface is cleaned and activated by irradiating each bonding surface with argon plasma, ion beam or atomic beam in vacuum before bonding. After joining, the room-temperature bonding method is used in which the bonding surfaces are brought into contact with each other and directly bonded at room temperature. However, not only the room-temperature bonding method but also a bonding method using a low-melting eutectic material such as AuSn or solder. It may be adopted.

上述の第１の接合工程では、シリコン基板４０ａの接合用金属層４８と配光用基板３０の接合用金属層３８とが接合されるとともに、シリコン基板４０ａの導体パターンと配光用基板３０の導体パターン３７，３７とが接合され電気的に接続される。ここで、シリコン基板４０ａの導体パターンと配光用基板３０の導体パターン３７，３７との接合部位は、貫通孔配線３４に重なる領域からずらしてあるので、前者の導体パターンと後者の導体パターン３７，３７との互いの接合面の平坦度を高めることができ、特に常温接合法により接合する際の接合歩留まりを高めることができるとともに接合信頼性を高めることができる。また、上述の第２の接合工程では、ベース基板２０の接合用金属層２９と配光用基板３０の接合用金属層３６とが接合されるとともに、ベース基板２０の導体パターン２５ｂ，２５ｂと配光用基板３０の導体パターンとが接合され電気的に接続される。ここで、ベース基板２０の導体パターン２５ｂ，２５ｂと配光用基板３０の導体パターンとの接合部位は、貫通孔配線２４に重なる領域および貫通孔配線３４に重なる領域からずらしてあるので、前者の導体パターン２５ｂ，２５ｂと後者の導体パターンとの互いの接合面の平坦度を高めることができ、特に常温接合法により接合する際の接合歩留まりを高めることができるとともに接合信頼性を高めることができる。   In the first bonding step described above, the bonding metal layer 48 of the silicon substrate 40 a and the bonding metal layer 38 of the light distribution substrate 30 are bonded, and the conductor pattern of the silicon substrate 40 a and the light distribution substrate 30 are combined. Conductive patterns 37 and 37 are joined and electrically connected. Here, since the junction part of the conductor pattern of the silicon substrate 40a and the conductor patterns 37, 37 of the light distribution substrate 30 is shifted from the region overlapping the through-hole wiring 34, the former conductor pattern and the latter conductor pattern 37 are arranged. , 37, the flatness of the joint surfaces can be increased, and in particular, the bonding yield when bonding by the room temperature bonding method can be increased and the bonding reliability can be increased. Further, in the above-described second bonding step, the bonding metal layer 29 of the base substrate 20 and the bonding metal layer 36 of the light distribution substrate 30 are bonded, and the conductor patterns 25b and 25b of the base substrate 20 are arranged. The conductor pattern of the light substrate 30 is joined and electrically connected. Here, since the joint portions of the conductor patterns 25b and 25b of the base substrate 20 and the conductor pattern of the light distribution substrate 30 are shifted from the region overlapping the through-hole wiring 24 and the region overlapping the through-hole wiring 34, the former The flatness of the joint surfaces of the conductor patterns 25b and 25b and the latter conductor pattern can be increased, and in particular, the bonding yield when bonding by the room temperature bonding method can be increased and the bonding reliability can be increased. .

また、上述のパッケージ２の製造にあたっては、上述の各シリコン基板２０ａ，３０ａ，４０ａとして、それぞれベース基板２０、配光用基板３０、光検出素子形成基板４０を多数形成可能なシリコンウェハを用いるとともに、上述の透光性基板として透光性部材３を多数形成可能なウェハ状のもの（透光性ウェハ）を用い、上述の第１の接合工程、研磨工程、光取出窓形成工程、第２の接合工程、封止部形成工程、第３の接合工程などの各工程をウェハレベルで行うことでウェハレベルパッケージ構造体を形成してから、ダイシング工程によりパッケージ２のサイズに分割されている。したがって、ベース基板２０と配光用基板３０と光検出素子形成基板４０と透光性部材３とが同じ外形サイズとなり、小型のパッケージ２を実現できるとともに、製造が容易になる。   In manufacturing the above-described package 2, a silicon wafer capable of forming a large number of the base substrate 20, the light distribution substrate 30, and the light detection element forming substrate 40 is used as each of the silicon substrates 20a, 30a, and 40a. A wafer-like one (translucent wafer) capable of forming a large number of translucent members 3 is used as the above-described translucent substrate, and the above-described first bonding step, polishing step, light extraction window forming step, second The wafer level package structure is formed by performing each process such as the bonding process, the sealing part forming process, and the third bonding process at the wafer level, and then divided into the size of the package 2 by the dicing process. Therefore, the base substrate 20, the light distribution substrate 30, the light detection element formation substrate 40, and the translucent member 3 have the same outer size, so that a small package 2 can be realized and manufacturing is facilitated.

以下、上述の制御部１０について説明する。   Hereinafter, the above-described control unit 10 will be described.

制御部１０は、上述のように、光検出素子４の出力に基づいて各スイッチング素子Ｑａ〜ＱｄそれぞれをＰＷＭ制御することで各ＬＥＤチップ１ａ〜１ｄの光出力を各別に調節するものであり、各スイッチング素子Ｑａ〜Ｑｄそれぞれへ図１（ｂ）に示すようなＰＷＭ信号を与える。   As described above, the control unit 10 performs PWM control on each of the switching elements Qa to Qd based on the output of the light detection element 4, thereby adjusting the light output of each LED chip 1a to 1d separately. A PWM signal as shown in FIG. 1B is given to each of the switching elements Qa to Qd.

ここにおいて、制御部１０は、マイクロコンピュータに適宜のプログラムを搭載することにより構成されており、全てのＬＥＤチップ１ａ〜１ｄが点灯する混色期間Ｔａと光検出素子４によるモニタリング対象となる１個のＬＥＤチップ（全てのＬＥＤチップ１ａ〜１ｄのうちの１個）のみが点灯するモニタリング用期間Ｔｕとが時系列的に交互に現われモニタリング対象として点灯するＬＥＤチップが順次切り替わるように各スイッチング素子Ｑａ〜Ｑｄそれぞれへ与えるＰＷＭ信号を生成する。なお、各ＰＷＭ信号の周波数は、人が光の点滅を感じないように１００Ｈｚ以上に設定することが望ましい。   Here, the control unit 10 is configured by installing an appropriate program in the microcomputer, and the color mixture period Ta in which all the LED chips 1 a to 1 d are turned on and one object to be monitored by the light detection element 4. The switching elements Qa˜ are arranged such that only the LED chips (one of all the LED chips 1a˜1d) are lit up and the monitoring periods Tu alternately appear in time series, and the LED chips lit up as monitoring targets are sequentially switched. A PWM signal to be supplied to each Qd is generated. Note that the frequency of each PWM signal is preferably set to 100 Hz or more so that a person does not feel blinking of light.

より具体的には、制御部１０は、少なくとも混色期間Ｔａとモニタリング用期間Ｔｕとを含む単位期間Ｔ１においてモニタリング対象のＬＥＤチップ（全てのＬＥＤチップ１ａ〜１ｄのうちの１個）の点灯開始タイミング（ＰＷＭ信号におけるオン期間の立ち上がりのタイミング）を他のＬＥＤチップの点灯開始タイミングよりも早くすることでモニタリング用期間Ｔｕが周期的に現われるように各ＰＷＭ信号を生成するようになっている。ここで、制御部１０は、各モニタリング用期間Ｔｕにおいて図１（ｂ）中に上向きの矢印で示したタイミングで光検出素子４の出力を入力し、光検出素子４の出力があらかじめ各ＬＥＤチップ１ａ〜１ｄそれぞれに対応付けて１対１で設定された各別の目標値に保たれるようにＰＷＭ信号のオンデューティをフィードバック制御する（オンデューティをフィードバック制御する際には、オン期間の立ち下りのタイミングを変化させることでオンデューティを変化させる）。ここで、上述の単位期間Ｔ１は、モニタリング用期間Ｔｕと混色期間Ｔａとの他に、全てのＬＥＤチップ１ａ〜１ｄが消灯している消灯期間なども含んでいる。なお、上述の単位期間Ｔ１においては、混色期間Ｔａとモニタリング用期間Ｔｕとのうちモニタリング用期間Ｔｕを混色期間Ｔａよりも先に設定してあるが、混色期間Ｔａの後にモニタリング用期間Ｔｕを設定するようにしてもよい。   More specifically, the control unit 10 starts the lighting start timing of the LED chip to be monitored (one of all the LED chips 1a to 1d) in the unit period T1 including at least the color mixture period Ta and the monitoring period Tu. Each PWM signal is generated such that the monitoring period Tu appears periodically by making (the rise timing of the ON period in the PWM signal) earlier than the lighting start timing of the other LED chips. Here, the control unit 10 inputs the output of the light detection element 4 at the timing indicated by the upward arrow in FIG. 1B in each monitoring period Tu, and the output of the light detection element 4 is previously set to each LED chip. The on-duty of the PWM signal is feedback controlled so as to be maintained at different target values set in a one-to-one correspondence with 1a to 1d (when the on-duty is feedback-controlled, the on-period The on-duty is changed by changing the descending timing). Here, the above-described unit period T1 includes, in addition to the monitoring period Tu and the color mixture period Ta, an unlit period in which all the LED chips 1a to 1d are unlit. In the unit period T1, the monitoring period Tu is set before the color mixing period Ta out of the color mixing period Ta and the monitoring period Tu. However, the monitoring period Tu is set after the color mixing period Ta. You may make it do.

上述の図１（ｂ）に示した例では、制御部１０は、青色光（Ｂ）を放射するＬＥＤチップ１ａ、緑色光（Ｇ）を放射するＬＥＤチップ１ｂ、黄色光（Ａ）を放射するＬＥＤチップ１ｃ、赤色光（Ｒ）を放射するＬＥＤチップ１ｄ、ＬＥＤチップ１ａ、ＬＥＤチップ１ｂ、ＬＥＤチップ１ｃ、・・・の順でモニタリング対象のＬＥＤチップが順次切り替わるように各スイッチング素子Ｑａ〜Ｑｄそれぞれへ与えるＰＷＭ信号を生成しているが、モニタリング対象とするＬＥＤチップの順序は特に限定するものではない。   In the example illustrated in FIG. 1B, the control unit 10 emits the LED chip 1a that emits blue light (B), the LED chip 1b that emits green light (G), and the yellow light (A). The switching elements Qa to Qd so that the LED chips to be monitored are sequentially switched in the order of the LED chip 1c, the LED chip 1d that emits red light (R), the LED chip 1a, the LED chip 1b, the LED chip 1c,. Although the PWM signal given to each is generated, the order of the LED chips to be monitored is not particularly limited.

また、モニタリング対象とするＬＥＤチップを複数の単位期間Ｔ１に亘って同じものとしてもよく、例えば、ＬＥＤチップ１ａ、ＬＥＤチップ１ａ、ＬＥＤチップ１ｂ、ＬＥＤチップ１ｂ、ＬＥＤチップ１ｃ、ＬＥＤチップ１ｃ、ＬＥＤチップ１ｄ、ＬＥＤチップ１ｄ、ＬＥＤチップ１ａ、ＬＥＤチップ１ａ、ＬＥＤチップ１ｂ、ＬＥＤチップ１ｂ、・・・の順でモニタリング対象のＬＥＤチップが順次切り替わるように各スイッチング素子Ｑａ〜Ｑｄそれぞれへ与えるＰＷＭ信号を生成するようにしもよく、この場合には、制御部１０において、同じモニタリング対象のＬＥＤチップに関する光検出素子４からの複数の入力の平均値を求める演算を行い、当該平均値と上記目標値とを比較してオンデューティをフィードバック制御するようにしてもよい。   Further, the LED chip to be monitored may be the same over a plurality of unit periods T1, for example, LED chip 1a, LED chip 1a, LED chip 1b, LED chip 1b, LED chip 1c, LED chip 1c, LED PWM signal applied to each of the switching elements Qa to Qd so that the monitoring target LED chips are sequentially switched in the order of chip 1d, LED chip 1d, LED chip 1a, LED chip 1a, LED chip 1b, LED chip 1b,. In this case, the control unit 10 performs an operation for obtaining an average value of a plurality of inputs from the light detection elements 4 regarding the same LED chip to be monitored, and the average value and the target value are calculated. Compared with the on-duty feedback control It may be.

なお、ＬＥＤチップ１ａ〜１ｄの光出力に関しては、現状では〔青色光を放射するＬＥＤチップ１ａ〕＞〔赤色光を放射するＬＥＤチップ１ｄ〕＞〔黄色光を放射するＬＥＤチップ１ｃ〕＞〔緑色光を放射するＬＥＤチップ１ｂ〕となっており、初期状態において各ＬＥＤチップ１ａ〜１ｄそれぞれに対応するスイッチング素子Ｑａ〜Ｑｄへ与えるＰＷＭ信号のオンデューティに関しては、図１（ｂ）から分かるように、〔ＬＥＤチップ１ａに対応するスイッチング素子Ｑａ〕＜〔ＬＥＤチップ１ｄに対応するスイッチング素子Ｑｄ〕＜〔ＬＥＤチップ１ｃに対応するスイッチング素子Ｑｃ〕＜〔ＬＥＤチップ１ｂに対応するスイッチング素子Ｑｂ〕となっている。ただし、ＬＥＤチップ１ａ〜１ｄとして光出力が同じものが用意できる場合には、各スイッチング素子Ｑａ〜Ｑｄへ与えるＰＷＭ信号のオンデューティを同じに設定してもよい。   Regarding the light output of the LED chips 1a to 1d, at present, [LED chip 1a emitting blue light]> [LED chip 1d emitting red light]> [LED chip 1c emitting yellow light]> [green As shown in FIG. 1B, the on-duty of the PWM signal applied to the switching elements Qa to Qd corresponding to the LED chips 1a to 1d in the initial state is the LED chip 1b that emits light. [Switching element Qa corresponding to LED chip 1a] <[switching element Qd corresponding to LED chip 1d] <[switching element Qc corresponding to LED chip 1c] <[switching element Qb corresponding to LED chip 1b] ing. However, when LED chips 1a to 1d having the same light output can be prepared, the on-duty of the PWM signal applied to each switching element Qa to Qd may be set to be the same.

以上説明した本実施形態の発光装置では、制御部１０が、上述のように、全てのＬＥＤチップ１ａ〜１ｄが点灯する混色期間Ｔａと光検出素子４によるモニタリング対象となる１個のＬＥＤチップのみが点灯するモニタリング用期間Ｔｕとが時系列的に交互に現われモニタリング対象として点灯するＬＥＤチップが順次切り替わるように各スイッチング素子Ｑａ〜Ｑｄそれぞれへ与えるＰＷＭ信号を生成するので、パッケージ２に１つの光検出素子４を設けるだけで各発光色のＬＥＤチップ１ａ〜１ｄそれぞれの光を精度良く検出することができるとともに混色光の光色や色温度の精度を向上することができるから、信頼性が高く且つ低コスト化が可能になる。また、本実施形態の発光装置では、図４および図５に示した従来の発光装置のパッケージ２’における遮光部３９を設ける必要がなく、隣り合うＬＥＤチップ１ａ〜１ｄ間の距離を短くすることができて、ＬＥＤチップ１ａ〜１ｄをより狭い範囲内に配置することが可能になり、色むらの発生を抑制できるとともに、混色光の光色や色温度の精度を向上することができる。また、上述の遮光部３９に起因した光損失がなくなるので、外部への光取出し効率の向上も可能となる。   In the light emitting device of the present embodiment described above, the control unit 10 has only one LED chip to be monitored by the color mixture period Ta in which all the LED chips 1a to 1d are lit and the light detection element 4 as described above. Since the monitoring period Tu in which is turned on alternately appears in time series and the LED chips to be turned on as monitoring targets are sequentially switched, PWM signals to be supplied to the respective switching elements Qa to Qd are generated. By providing the detection element 4, it is possible to detect each of the light emitting color LED chips 1 a to 1 d with high accuracy and to improve the accuracy of the light color and color temperature of the mixed color light, so that the reliability is high. In addition, the cost can be reduced. Further, in the light emitting device of this embodiment, it is not necessary to provide the light shielding portion 39 in the package 2 ′ of the conventional light emitting device shown in FIGS. 4 and 5, and the distance between the adjacent LED chips 1a to 1d is shortened. Thus, the LED chips 1a to 1d can be arranged in a narrower range, the occurrence of color unevenness can be suppressed, and the accuracy of the light color and color temperature of the mixed color light can be improved. In addition, since the light loss due to the above-described light shielding portion 39 is eliminated, the light extraction efficiency to the outside can be improved.

また、本実施形態の発光装置によれば、制御部１０が、少なくとも混色期間Ｔａとモニタリング用期間Ｔｕとを含む単位期間Ｔ１においてモニタリング対象のＬＥＤチップの点灯開始タイミングを他のＬＥＤチップの点灯開始タイミングよりも早くすることでモニタリング用期間が周期的に現われるように各ＰＷＭ信号を生成するので、制御部１０において光検出素子４の出力を入力するタイミング制御が容易になり、より信頼性が向上する。   Further, according to the light emitting device of the present embodiment, the control unit 10 determines the lighting start timing of the LED chip to be monitored in the unit period T1 including at least the color mixture period Ta and the monitoring period Tu. Since each PWM signal is generated so that the monitoring period appears periodically by making it earlier than the timing, the timing control for inputting the output of the light detection element 4 in the control unit 10 becomes easy, and the reliability is further improved. To do.

ところで、上述の発光装置は、制御部１０が、パッケージ２を実装する回路基板に設けてあるが、半導体製造技術を利用してパッケージ２に制御部１０を形成するようにしてもよい。また、上述の発光装置では、各スイッチング素子Ｑａ〜ＱｄをＭＯＳＦＥＴにより構成してあるが、ＭＯＳＦＥＴに限らず、例えば、バイポーラトランジスタにより構成してもよい。   By the way, although the control part 10 is provided in the circuit board which mounts the package 2 in the above-mentioned light-emitting device, you may make it form the control part 10 in the package 2 using a semiconductor manufacturing technique. In the above-described light emitting device, each switching element Qa to Qd is configured by a MOSFET. However, the switching element Qa to Qd is not limited to a MOSFET but may be configured by, for example, a bipolar transistor.

なお、上述の実施形態では、ベース基板２０、配光用基板３０、光検出素子形成基板４０それぞれをシリコン基板２０ａ，３０ａ，４０ａを用いて形成してあるが、シリコン基板２０ａ，３０ａ，４０ａに限らず、半導体基板であればよく、例えば、シリコンカーバイド基板（ＳｉＣ基板）を用いて形成してもよい。また、ＬＥＤチップ１ａ〜１ｄとしては、例えば、結晶成長用基板の主表面側に発光部などをエピタキシャル成長した後に発光部を支持する導電性基板（例えば、Ｓｉ基板など）を発光部に固着してから、結晶成長用基板などを除去したものを用いてもよい。また、パッケージ２に実装するＬＥＤチップの数や発光色は特に限定するものではない。   In the above-described embodiment, the base substrate 20, the light distribution substrate 30, and the light detection element formation substrate 40 are formed using the silicon substrates 20a, 30a, and 40a, respectively, but the silicon substrates 20a, 30a, and 40a are formed on the silicon substrates 20a, 30a, and 40a. It is not limited to a semiconductor substrate, and may be formed using, for example, a silicon carbide substrate (SiC substrate). In addition, as the LED chips 1a to 1d, for example, a light emitting portion is epitaxially grown on the main surface side of the crystal growth substrate, and then a conductive substrate (for example, a Si substrate) that supports the light emitting portion is fixed to the light emitting portion. Then, a substrate from which a crystal growth substrate or the like is removed may be used. Further, the number of LED chips to be mounted on the package 2 and the emission color are not particularly limited.

実施形態の発光装置を示し、（ａ）は概略回路図、（ｂ）は動作説明図である。The light-emitting device of embodiment is shown, (a) is a schematic circuit diagram, (b) is operation | movement explanatory drawing. 同上の発光装置のパッケージを示し、（ａ）は概略断面図、（ｂ）は要部概略平面図である。The package of the light emitting device same as the above is shown, (a) is a schematic cross-sectional view, (b) is a schematic plan view of the main part. 同上の発光装置のパッケージの概略分解斜視図である。It is a general | schematic disassembled perspective view of the package of the light-emitting device same as the above. 従来例を示す発光装置のパッケージの概略断面図である。It is a schematic sectional drawing of the package of the light-emitting device which shows a prior art example. 同上の発光装置のパッケージの概略分解斜視図である。It is a general | schematic disassembled perspective view of the package of the light-emitting device same as the above.

符号の説明Explanation of symbols

１ａ〜１ｄ ＬＥＤチップ
２ パッケージ
４ 光検出素子
１０ 制御部
Ｑａ〜Ｑｄ スイッチング素子
Ｔ１ 単位期間
Ｔａ 混色期間
Ｔｕ モニタリング用期間 DESCRIPTION OF SYMBOLS 1a-1d LED chip 2 Package 4 Photodetection element 10 Control part Qa-Qd Switching element T1 Unit period Ta Color mixing period Tu Monitoring period

Claims (2)

発光色の異なる複数個のＬＥＤチップが実装されるとともに各ＬＥＤチップから放射される光を検出する１つの光検出素子が設けられてなり各ＬＥＤチップからの光の混色光が取り出されるパッケージと、各ＬＥＤチップそれぞれへの給電路に挿入されたスイッチング素子と、光検出素子の出力に基づいて各スイッチング素子それぞれをＰＷＭ制御することで各ＬＥＤチップの光出力を各別に調節する制御部とを備え、制御部は、全てのＬＥＤチップが点灯する混色期間と光検出素子によるモニタリング対象となる１個のＬＥＤチップのみが点灯するモニタリング用期間とが時系列的に交互に現われモニタリング対象として点灯するＬＥＤチップが順次切り替わるように各スイッチング素子それぞれへ与えるＰＷＭ信号を生成することを特徴とする発光装置。   A package in which a plurality of LED chips with different emission colors are mounted and one light detection element for detecting light emitted from each LED chip is provided, and a mixed color light from each LED chip is taken out, A switching element inserted in a power feeding path to each LED chip, and a control unit that individually adjusts the light output of each LED chip by PWM controlling each switching element based on the output of the light detection element The control unit is configured such that a mixed color period in which all LED chips are lit and a monitoring period in which only one LED chip to be monitored by the light detection element is alternately displayed in time series, and the LEDs that are lit as monitoring objects Generates a PWM signal to be supplied to each switching element so that the chips are sequentially switched. A light-emitting device to be. 制御部は、少なくとも混色期間とモニタリング用期間とを含む単位期間においてモニタリング対象のＬＥＤチップの点灯開始タイミングを他のＬＥＤチップの点灯開始タイミングよりも早くすることでモニタリング用期間が周期的に現われるように各ＰＷＭ信号を生成することを特徴とする請求項１記載の発光装置。   The control unit makes the monitoring period appear periodically by making the lighting start timing of the LED chip to be monitored earlier than the lighting start timing of the other LED chips in the unit period including at least the color mixture period and the monitoring period. The light emitting device according to claim 1, wherein each PWM signal is generated.
JP2008044862A 2008-02-26 2008-02-26 Light emitting device Pending JP2009206186A (en)

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JP2017054799A (en) * 2015-09-10 2017-03-16 パナソニックＩｐマネジメント株式会社 Illumination device, and illumination system and vehicle that have the same
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