JP2007287800A - Wiring, package parts for semiconductor device using same, and wiring board - Google Patents

Wiring, package parts for semiconductor device using same, and wiring board Download PDF

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Publication number
JP2007287800A
JP2007287800A JP2006111203A JP2006111203A JP2007287800A JP 2007287800 A JP2007287800 A JP 2007287800A JP 2006111203 A JP2006111203 A JP 2006111203A JP 2006111203 A JP2006111203 A JP 2006111203A JP 2007287800 A JP2007287800 A JP 2007287800A
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wiring
semiconductor device
housing
present
wiring board
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Takahiro Fukunaga
隆博 福永
Yoshihide Omura
義秀 大村
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Panasonic Holdings Corp
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Matsushita Electric Industrial Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/183—Connection portion, e.g. seal
    • H01L2924/18301—Connection portion, e.g. seal being an anchoring portion, i.e. mechanical interlocking between the encapsulation resin and another package part

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  • Lead Frames For Integrated Circuits (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide wiring which can keep adhesion with a protective layer and prevent the flow of a liquid to the outside of a specified area when forming the protective layer, and to provide package parts for a semiconductor device using the same and a wiring board. <P>SOLUTION: Wiring 1 is used to mount an electronic element, and a plurality of concaves 12 are separately and independently formed on the almost entire surface thereof. Thus, the adhesion with a protective layer can be kept by anchor effect. In addition, there independently exist the concaves 12 thereon, respectively, so that a sealing resin or a liquid such as a solder resist ink or the like is hard to flow out by capillary phenomenon. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

本発明は、電子素子を実装するための配線と、これを用いた半導体装置用パッケージ部品及び配線基板に関する。   The present invention relates to a wiring for mounting an electronic element, a semiconductor device package component using the wiring, and a wiring board.

従来、半導体素子やコンデンサ素子等の電子素子を実装するための配線は、例えばその表面を凹凸加工することによって、保護層（封止樹脂層やソルダレジスト層等）との密着性を向上させていた（例えば、特許文献１等参照）。
特開２００２−８３９１７号公報 Conventionally, wiring for mounting an electronic element such as a semiconductor element or a capacitor element has improved adhesion to a protective layer (such as a sealing resin layer or a solder resist layer) by, for example, processing the surface of the wiring. (See, for example, Patent Document 1).
JP 2002-83917 A

しかしながら、従来の凹凸加工した配線を用いて半導体装置を形成すると、半導体素子を封止するための封止樹脂（例えばエポキシ樹脂やシリコーン樹脂等）が、配線の表面に設けられた凹凸の凹部に沿って毛細管現象により流れ出し、外部接続箇所（例えば電気的接続箇所）が封止樹脂で被覆されてしまうことがあった。外部接続箇所が封止樹脂で被覆されると、外観不良となるため歩留まりが低下する。更に、外部接続箇所が電気的接続箇所の場合は、外部機器との導通が取れなくなるおそれがある。   However, when a semiconductor device is formed using a conventional unevenly processed wiring, a sealing resin (for example, an epoxy resin or a silicone resin) for sealing a semiconductor element is formed in the concave and convex portions provided on the surface of the wiring. In some cases, it flows out by capillary action, and external connection portions (for example, electrical connection portions) are covered with the sealing resin. If the external connection portion is covered with the sealing resin, the appearance deteriorates and the yield decreases. Furthermore, when the external connection location is an electrical connection location, there is a risk that electrical continuity with external equipment may not be achieved.

また、従来の配線上にソルダレジスト層を形成した後で、配線の端子部にスズをめっきすると、所謂「めっきの潜り込み現象」が発生するおそれがあった。この「めっきの潜り込み現象」について図面を参照して説明する。   In addition, when a solder resist layer is formed on a conventional wiring and then tin is plated on the terminal portion of the wiring, a so-called “plating phenomenon” may occur. The “sinking phenomenon of plating” will be described with reference to the drawings.

図６Ａ，Ｂは、スズめっき工程を説明するための断面図である。図６Ａは、ポリイミド等からなる電気絶縁性基材１００上に、銅等からなる配線１０１及びソルダレジスト層１０２が順次形成された断面図である。従来の凹凸加工した配線１０１上にソルダレジストインキを塗布すると、このソルダレジストインキが配線１０１の表面に設けられた凹凸の凹部に沿って毛細管現象により流れ出す（以下、「液ダレ」ともいう。）。その結果、図６Ａに示すように、ソルダレジスト層１０２の端部１０２ａの厚みが他の領域より薄くなる。この厚みが薄い端部１０２ａは、配線１０１との密着性が悪いため、図６Ｂに示すようにソルダレジスト層１０２で覆われていない配線１０１上にスズ１０３をめっきすると、端部１０２ａからスズ１０３が潜り込んで、例えば端子間がショートするおそれがあった。更に、スズ１０３をめっきする際のめっき液（図示せず）も端部１０２ａから浸入するため、スズ１０３と配線１０１との間で局部電池が形成され、端部１０２ａからスズ１０３が潜り込んだ箇所の近傍の配線１０１がエッチングされる。その結果、配線１０１の一部がめっき液へ溶出することによって溝（図示せず）が形成され、例えば配線１０１に外力が加わった際に上記溝に応力が集中し、配線１０１の折損や断裂が生じるおそれもあった。   6A and 6B are cross-sectional views for explaining the tin plating step. FIG. 6A is a cross-sectional view in which a wiring 101 made of copper or the like and a solder resist layer 102 are sequentially formed on an electrically insulating base material 100 made of polyimide or the like. When solder resist ink is applied onto the conventional unevenly processed wiring 101, this solder resist ink flows out by capillary action along the concave and convex portions provided on the surface of the wiring 101 (hereinafter also referred to as “liquid dripping”). . As a result, as shown in FIG. 6A, the thickness of the end portion 102a of the solder resist layer 102 becomes thinner than other regions. Since the thin end portion 102a has poor adhesion to the wiring 101, when tin 103 is plated on the wiring 101 not covered with the solder resist layer 102 as shown in FIG. Sunk in, for example, there was a risk of short-circuiting between terminals. Further, since a plating solution (not shown) for plating the tin 103 also enters from the end portion 102a, a local battery is formed between the tin 103 and the wiring 101, and the tin 103 has entered from the end portion 102a. The wiring 101 in the vicinity of is etched. As a result, a part of the wiring 101 elutes into the plating solution to form a groove (not shown). For example, when an external force is applied to the wiring 101, stress concentrates on the groove, and the wiring 101 is broken or broken. There was also a risk of occurrence.

本発明は、上記従来の課題を解決するもので、保護層との密着性を維持できる上、保護層を形成する際に、保護層の構成材料となる液状体（以下、単に「液状体」ともいう。）が所定の領域外へ流出することを防止できる配線と、これを用いた半導体装置用パッケージ部品及び配線基板とを提供する。   The present invention solves the above-described conventional problems, and can maintain adhesion with the protective layer, and also forms a liquid material (hereinafter simply referred to as “liquid material”) as a constituent material of the protective layer when the protective layer is formed. Also provided is a wiring that can prevent the liquid from flowing out of a predetermined region, and a package component for a semiconductor device and a wiring board using the wiring.

本発明の配線は、電子素子を実装するための配線であって、表面の略全面に、各々単独に点在する複数の窪みが形成されていることを特徴とする。   The wiring of the present invention is a wiring for mounting an electronic element, and is characterized in that a plurality of depressions that are individually scattered are formed on substantially the entire surface.

本発明の半導体装置用パッケージ部品は、配線と、前記配線上の外部接続箇所を除く領域に形成された筐体とを含む半導体装置用パッケージ部品であって、
前記配線は、上記本発明の配線であり、かつ少なくとも１対のリードを含み、
前記筐体は、前記１対のリードに跨って形成され、かつ半導体素子を収容するための収容部が設けられていることを特徴とする。 The package component for a semiconductor device of the present invention is a package component for a semiconductor device including a wiring and a housing formed in a region excluding external connection portions on the wiring,
The wiring is the wiring of the present invention, and includes at least one pair of leads,
The housing is formed across the pair of leads and is provided with a housing portion for housing a semiconductor element.

本発明の配線基板は、電気絶縁性基材と、前記電気絶縁性基材上に形成された配線とを含む配線基板であって、
前記配線は、上記本発明の配線であることを特徴とする。 The wiring board of the present invention is a wiring board including an electrically insulating base material and wiring formed on the electrically insulating base material,
The wiring is the wiring of the present invention described above.

本発明の配線によれば、その表面に各々単独に点在する複数の窪みが形成されているため、アンカー効果によって保護層との密着性を維持できる。また、窪みが各々単独に点在するため、液状体が毛細管現象によって流れ出すおそれはない。よって、保護層を形成する際に、液状体が所定の領域外へ流出することを防止できる。   According to the wiring of the present invention, since a plurality of depressions that are individually scattered on the surface are formed, the adhesion with the protective layer can be maintained by the anchor effect. Further, since the depressions are scattered individually, there is no possibility that the liquid material flows out by capillary action. Therefore, when forming the protective layer, it is possible to prevent the liquid material from flowing out of the predetermined region.

本発明の半導体装置用パッケージ部品によれば、上記本発明の配線を用いているため、配線と封止樹脂層との密着性を維持できる上、封止樹脂が外部接続箇所へ流出することを防止できる。   According to the package component for a semiconductor device of the present invention, since the wiring of the present invention is used, the adhesion between the wiring and the sealing resin layer can be maintained, and the sealing resin flows out to the external connection portion. Can be prevented.

本発明の配線基板によれば、上記本発明の配線を用いているため、配線とソルダレジスト層との密着性を維持できる上、ソルダレジストインキの液ダレを防止できる。   According to the wiring board of the present invention, since the wiring of the present invention is used, the adhesion between the wiring and the solder resist layer can be maintained, and the dripping of the solder resist ink can be prevented.

本発明の配線は、電子素子を実装するための配線として使用される。実装する電子部品は特に限定されず、例えば半導体素子等の能動素子や、コンデンサ素子等の受動素子を実装することができる。そして、本発明の配線は、その表面の略全面に、各々単独に点在する複数の窪みが形成されている。これにより、アンカー効果によって保護層との密着性を維持できる。また、窪みが各々単独に点在するため、封止樹脂やソルダレジストインキ等の液状体が毛細管現象によって流れ出すおそれはない。また、配線の表面の略全面に窪みが形成されているため、従来のように配線の表面の一部に選択的に凹凸を形成する場合（特許文献１参照）に比べ、製造工程が簡略化する。なお、従来のように配線上に突起が存在している場合は、機械的な衝撃によって突起の先端が欠落する可能性があるため、配線の機械的強度が低下するおそれがあった。本発明の配線の表面は、窪みと平面とからなるため、機械的強度が低下するおそれはない。   The wiring of the present invention is used as wiring for mounting an electronic element. The electronic component to be mounted is not particularly limited, and for example, an active element such as a semiconductor element or a passive element such as a capacitor element can be mounted. In the wiring of the present invention, a plurality of depressions that are individually scattered are formed on substantially the entire surface of the wiring. Thereby, adhesiveness with a protective layer can be maintained by the anchor effect. Further, since the depressions are scattered individually, there is no possibility that a liquid material such as sealing resin or solder resist ink flows out due to a capillary phenomenon. In addition, since the depression is formed on almost the entire surface of the wiring, the manufacturing process is simplified as compared with the case where unevenness is selectively formed on a part of the surface of the wiring as in the past (see Patent Document 1). To do. In the case where there are protrusions on the wiring as in the prior art, there is a possibility that the tip of the protrusion may be lost due to a mechanical impact, which may reduce the mechanical strength of the wiring. Since the surface of the wiring of the present invention consists of a depression and a flat surface, there is no possibility that the mechanical strength is lowered.

上記窪みの形成方法は特に限定されず、例えば表面が平坦な配線の表面に公知のフォトリソグラフィー法でレジストパターンを形成した後、レジストパターンで覆われていない配線の表面をエッチングして上記窪みを形成することができる。この場合のエッチングは、ブラスト処理等による機械的エッチングや、マイクロエッチング剤処理等による化学的エッチング等であればよい。また、上記窪みの形状を模った凸部を有する金型を用いてプレス加工することにより上記窪みを形成してもよいし、レーザー加工により上記窪みを形成してもよい。   The method for forming the depression is not particularly limited. For example, after forming a resist pattern on the surface of the wiring with a flat surface by a known photolithography method, the surface of the wiring not covered with the resist pattern is etched to form the depression. Can be formed. Etching in this case may be mechanical etching by blasting or the like, chemical etching by microetching agent processing, or the like. Moreover, the said hollow may be formed by pressing using the metal mold | die which has the convex part imitating the shape of the said hollow, and the said hollow may be formed by laser processing.

配線の構成材料としては、例えば銅や銅合金等の金属が使用できる。また、銅や銅合金を基材とし、この基材表面の一部又は全面が導電性被膜で覆われた配線を使用してもよい。上記導電性被膜を構成する材料としては、例えばＡｇ、Ｎｉ、Ｐｄ、Ａｕ、Ｒｈ、Ｐｔ、半田等の金属が使用できる。また、配線の厚みは、例えば４〜４０００μｍ程度である。   As a constituent material of the wiring, for example, a metal such as copper or a copper alloy can be used. Moreover, you may use the wiring which made copper or a copper alloy a base material, and covered one part or the whole surface of this base material with the electroconductive film. As a material constituting the conductive film, for example, metals such as Ag, Ni, Pd, Au, Rh, Pt, and solder can be used. Further, the thickness of the wiring is, for example, about 4 to 4000 μm.

次に、本発明の半導体装置用パッケージ部品について説明する。本発明の半導体装置用パッケージ部品は、配線と、この配線上の外部接続箇所（例えば電気的接続箇所）を除く領域に形成された筐体とを含む。そして、上記配線は、上記本発明の配線であり、かつ少なくとも１対のリードを含む。また、上記筐体は、上記１対のリードに跨って形成され、かつ半導体素子を収容するための収容部が設けられている。本発明の半導体装置用パッケージ部品によれば、上記本発明の配線を用いているため、配線と封止樹脂層との密着性を維持できる上、封止樹脂が外部接続箇所へ流出することを防止できる。   Next, the semiconductor device package component of the present invention will be described. The package component for a semiconductor device of the present invention includes a wiring and a housing formed in a region excluding an external connection location (for example, an electrical connection location) on the wiring. The wiring is the wiring according to the present invention and includes at least one pair of leads. The housing is formed across the pair of leads and is provided with a housing portion for housing the semiconductor element. According to the package component for a semiconductor device of the present invention, since the wiring of the present invention is used, the adhesion between the wiring and the sealing resin layer can be maintained, and the sealing resin flows out to the external connection portion. Can be prevented.

上記筐体を構成する材料は特に限定されず、樹脂、セラミック、金属等が使用できる。特に、ポリフタルアミド樹脂、液晶ポリマー等の熱可塑性樹脂を使用すると、成形性が良好なため所望の形状の筐体を容易に形成することができる上、低コスト化が可能となる。通常、熱可塑性樹脂を用いて上記筐体を上記配線に設けると、熱可塑性樹脂の熱収縮によって上記筐体と上記配線との間に空隙が発生する。この空隙に封止樹脂が浸入すると、上記配線に形成された上記窪みに封止樹脂が溜まるため、アンカー効果により上記筐体と上記配線との密着性が向上する。   The material which comprises the said housing | casing is not specifically limited, Resin, a ceramic, a metal, etc. can be used. In particular, when a thermoplastic resin such as a polyphthalamide resin or a liquid crystal polymer is used, a casing having a desired shape can be easily formed because of good moldability, and the cost can be reduced. Usually, when the casing is provided on the wiring using a thermoplastic resin, a gap is generated between the casing and the wiring due to thermal contraction of the thermoplastic resin. When the sealing resin enters the gap, the sealing resin accumulates in the recess formed in the wiring, and thus the adhesion between the housing and the wiring is improved by the anchor effect.

次に、本発明の配線基板について説明する。本発明の配線基板は、電気絶縁性基材と、この電気絶縁性基材上に形成された配線とを含み、この配線は上記本発明の配線である。本発明の配線基板によれば、上記本発明の配線を用いているため、配線とソルダレジスト層との密着性を維持できる上、ソルダレジストインキの液ダレを防止できる。なお、上記電気絶縁性基材の厚みは、例えば２５〜１５０μｍ程度である。   Next, the wiring board of the present invention will be described. The wiring board of the present invention includes an electrically insulating base material and a wiring formed on the electrically insulating base material, and this wiring is the wiring of the present invention. According to the wiring board of the present invention, since the wiring of the present invention is used, the adhesion between the wiring and the solder resist layer can be maintained, and the dripping of the solder resist ink can be prevented. In addition, the thickness of the said electrically insulating base material is about 25-150 micrometers, for example.

上記電気絶縁性基材は特に限定されないが、可撓性を有する基材を使用すると折り曲げ可能な配線基板として使用できるため、例えば折りたたみ式携帯電話用の回路基板や、液晶駆動用の半導体チップを搭載したテープキャリアパッケージ等への適用が可能となる。特に、可撓性を有する基材がポリイミドからなる場合は、機械的強度や耐熱性が高い可撓性配線基板を提供できる。   The electrical insulating substrate is not particularly limited, but if a flexible substrate is used, it can be used as a foldable wiring board. For example, a circuit board for a folding mobile phone or a semiconductor chip for driving a liquid crystal is used. Application to the mounted tape carrier package or the like becomes possible. In particular, when the flexible substrate is made of polyimide, a flexible wiring board having high mechanical strength and heat resistance can be provided.

以下、本発明の実施形態について図面を参照しながら説明する。なお、参照する図面においては、実質的に同一の機能を有する構成要素を同一の符号で示し、重複する説明を省略する場合がある。   Hereinafter, embodiments of the present invention will be described with reference to the drawings. Note that in the drawings to be referred to, components having substantially the same function are denoted by the same reference numerals, and redundant description may be omitted.

（第１実施形態）
まず、本発明の第１実施形態に係る配線の一例として、リードフレームについて図１Ａ，Ｂを参照して説明する。図１Ａは、本発明の第１実施形態に係るリードフレームの平面図である。また、図１Ｂは、本発明の第１実施形態に係るリードフレームの表面の部分拡大図である。 (First embodiment)
First, a lead frame will be described with reference to FIGS. 1A and 1B as an example of wiring according to the first embodiment of the present invention. FIG. 1A is a plan view of a lead frame according to the first embodiment of the present invention. FIG. 1B is a partially enlarged view of the surface of the lead frame according to the first embodiment of the present invention.

図１Ａに示すように、リードフレーム１は、対をなすインナーリード１１ａ，１１ｂを複数組含む。また、図１Ｂに示すように、リードフレーム１の表面の略全面には、各々単独に点在する複数の窪み１２が形成されている。これにより、アンカー効果によって、保護層（図示せず）との密着性を維持できる。また、窪み１２が各々単独に点在するため、封止樹脂やソルダレジストインキ等の液状体（図示せず）が、毛細管現象によって外部接続箇所となるアウターリード１１ｃ（図１Ａ参照）へと流れ出すおそれはない。   As shown in FIG. 1A, the lead frame 1 includes a plurality of pairs of inner leads 11a and 11b. As shown in FIG. 1B, a plurality of dents 12 that are individually scattered are formed on substantially the entire surface of the lead frame 1. Thereby, adhesiveness with a protective layer (not shown) can be maintained by an anchor effect. Further, since the depressions 12 are scattered individually, a liquid material (not shown) such as sealing resin or solder resist ink flows out to the outer lead 11c (see FIG. 1A) which becomes an external connection portion by capillary action. There is no fear.

以上、本発明の第１実施形態に係る配線について説明したが、本発明の配線は上記実施形態には限定されない。例えば上記実施形態ではリードフレームを例に説明したが、本発明の配線はリードフレームに限定されず、電子素子を実装できる限り広範な用途の配線に適用できる。   As mentioned above, although the wiring which concerns on 1st Embodiment of this invention was demonstrated, the wiring of this invention is not limited to the said embodiment. For example, although the lead frame has been described as an example in the above embodiment, the wiring of the present invention is not limited to the lead frame, and can be applied to wiring of a wide range of uses as long as an electronic element can be mounted.

（第２実施形態）
次に、本発明の第２実施形態に係る半導体装置用パッケージ部品について図２Ａ，Ｂを参照して説明する。図２Ａは、本発明の第２実施形態に係る半導体装置用パッケージ部品の平面図である。また、図２Ｂは、図２ＡのI-I線断面図である。 (Second Embodiment)
Next, a semiconductor device package component according to a second embodiment of the present invention will be described with reference to FIGS. FIG. 2A is a plan view of a package component for a semiconductor device according to a second embodiment of the present invention. 2B is a cross-sectional view taken along line II of FIG. 2A.

図２Ａに示すように、半導体装置用パッケージ部品２は、上述したリードフレーム１と、リードフレーム１のアウターリード１１ｃを除く領域に形成された複数の筐体２１とを含む。   As shown in FIG. 2A, the semiconductor device package component 2 includes the lead frame 1 described above and a plurality of housings 21 formed in a region excluding the outer leads 11 c of the lead frame 1.

図２Ｂに示すように、筐体２１は、後述する半導体素子２５（図３参照）を収容するための収容部２１１ａを有する収容体２１ａと、基体２１ｂとを含む。また、筐体２１は、対をなすインナーリード１１ａ，１１ｂに跨って形成されている。   As shown in FIG. 2B, the housing 21 includes a housing body 21a having a housing portion 211a for housing a semiconductor element 25 (see FIG. 3) described later, and a base body 21b. Moreover, the housing | casing 21 is formed ranging over the inner leads 11a and 11b which make a pair.

半導体装置用パッケージ部品２によれば、各々単独に点在する窪み１２が形成されたリードフレーム１を用いているため、リードフレーム１と封止樹脂層（図示せず）との密着性を維持できる上、封止樹脂がアウターリード１１ｃへ流出することを防止できる。   According to the package component 2 for a semiconductor device, since the lead frame 1 in which the dents 12 scattered individually are used is used, the adhesion between the lead frame 1 and the sealing resin layer (not shown) is maintained. In addition, the sealing resin can be prevented from flowing out to the outer lead 11c.

次に、上述の半導体装置用パッケージ部品２を用いた半導体装置について図３を参照して説明する。図３は、半導体装置用パッケージ部品２を用いた半導体装置の断面図である。   Next, a semiconductor device using the above-described semiconductor device package component 2 will be described with reference to FIG. FIG. 3 is a cross-sectional view of a semiconductor device using the semiconductor device package component 2.

図３に示すように、半導体装置２０は、上述した半導体装置用パッケージ部品２と、半導体装置用パッケージ部品２の収容部２１１ａに収容された半導体素子２５と、収容部２１１ａに充填され、かつ半導体素子２５を封止する封止樹脂層２６とを含む。半導体素子２５は、ワイヤ２７を介してインナーリード１１ａ，１１ｂに設けられた端子２８上に実装されている。半導体装置２０は、半導体装置用パッケージ部品２を使用しているため、上述したように、リードフレーム１と封止樹脂層２６との密着性を維持できる上、封止樹脂層２６を構成する封止樹脂がアウターリード１１ｃへ流出することを防止できる。これにより、アウターリード１１ｃと外部機器（図示せず）との電気的接続を良好に維持することができる。   As shown in FIG. 3, the semiconductor device 20 includes the above-described semiconductor device package component 2, the semiconductor element 25 housed in the housing portion 211 a of the semiconductor device package component 2, and the housing portion 211 a. And a sealing resin layer 26 for sealing the element 25. The semiconductor element 25 is mounted on terminals 28 provided on the inner leads 11a and 11b via wires 27. Since the semiconductor device 20 uses the semiconductor device package component 2, as described above, the adhesiveness between the lead frame 1 and the sealing resin layer 26 can be maintained, and the sealing resin constituting the sealing resin layer 26 can be maintained. It is possible to prevent the stop resin from flowing into the outer lead 11c. Thereby, the electrical connection between the outer lead 11c and the external device (not shown) can be maintained well.

筐体２１の構成材料には、例えばポリフタルアミド樹脂、液晶ポリマー等の熱可塑性樹脂を使用することができる。熱可塑性樹脂を使用すると、成形性が良好なため所望の形状の筐体２１を容易に形成することができる上、低コスト化が可能となる。通常、熱可塑性樹脂を用いて筐体２１をリードフレーム１に設けると、熱可塑性樹脂の熱収縮によって筐体２１とリードフレーム１との間に空隙が発生する。この空隙に封止樹脂が浸入すると、図３に示すようにリードフレーム１に形成された窪み１２に上記封止樹脂が溜まるため、アンカー効果により筐体２１とリードフレーム１との密着性が向上する。   As the constituent material of the housing 21, for example, a thermoplastic resin such as polyphthalamide resin or liquid crystal polymer can be used. When a thermoplastic resin is used, since the moldability is good, the casing 21 having a desired shape can be easily formed, and the cost can be reduced. Normally, when the casing 21 is provided on the lead frame 1 using a thermoplastic resin, a gap is generated between the casing 21 and the lead frame 1 due to thermal contraction of the thermoplastic resin. When the sealing resin enters the gap, the sealing resin accumulates in the depressions 12 formed in the lead frame 1 as shown in FIG. 3, so that the adhesion between the casing 21 and the lead frame 1 is improved by the anchor effect. To do.

半導体素子２５としては、例えば発光ダイオード、受光ダイオード、レーザーダイオード等の光半導体素子を使用することができる。   As the semiconductor element 25, for example, an optical semiconductor element such as a light emitting diode, a light receiving diode, or a laser diode can be used.

封止樹脂層２６を構成する封止樹脂としては、例えばエポキシ樹脂やシリコーン樹脂等の熱硬化性樹脂が使用できる。なかでもシリコーン樹脂は耐光性が高いため、光半導体素子を使用する場合に、封止樹脂層２６の劣化を防止できる。また、シリコーン樹脂は弾性率が比較的低いため、半導体素子２５とリードフレーム１との間の電気的接続箇所に加わる応力を緩和することもできる。   As the sealing resin constituting the sealing resin layer 26, for example, a thermosetting resin such as an epoxy resin or a silicone resin can be used. In particular, since the silicone resin has high light resistance, the sealing resin layer 26 can be prevented from deteriorating when the optical semiconductor element is used. In addition, since the elastic modulus of the silicone resin is relatively low, the stress applied to the electrical connection portion between the semiconductor element 25 and the lead frame 1 can be relaxed.

（第３実施形態）
次に、本発明の第３実施形態に係る配線基板について図４を参照して説明する。図４は、本発明の第３実施形態に係る配線基板の断面図である。 (Third embodiment)
Next, a wiring board according to a third embodiment of the present invention will be described with reference to FIG. FIG. 4 is a cross-sectional view of a wiring board according to the third embodiment of the present invention.

図４に示すように、配線基板３は、ポリイミド等からなる電気絶縁性基材３０と、電気絶縁性基材３０上に形成された配線３１とを含む。配線３１の表面の略全面には、上述したリードフレーム１の表面（図１Ｂ参照）と同様に各々単独に点在する窪み１２が形成されている。これにより、配線３１とソルダレジスト層（図示せず）との密着性を維持できる上、ソルダレジスト層を構成するソルダレジストインキの液ダレを防止できる。   As shown in FIG. 4, the wiring board 3 includes an electrically insulating base material 30 made of polyimide or the like, and wirings 31 formed on the electrically insulating base material 30. Similar to the surface of the lead frame 1 described above (see FIG. 1B), the depressions 12 that are individually scattered are formed on substantially the entire surface of the wiring 31. As a result, the adhesion between the wiring 31 and the solder resist layer (not shown) can be maintained, and the dripping of the solder resist ink constituting the solder resist layer can be prevented.

次に、上述の配線基板３を用いたスズめっき工程について、図５Ａ，Ｂを参照して説明する。図５Ａ，Ｂは、配線基板３を用いたスズめっき工程を説明するための断面図である。   Next, a tin plating process using the above-described wiring board 3 will be described with reference to FIGS. 5A and 5B. 5A and 5B are cross-sectional views for explaining a tin plating process using the wiring board 3.

まず、図５Ａに示すように、配線基板３上の所望の箇所にソルダレジストインキ３２を塗布してソルダレジスト層３３を形成する。この際、配線基板３に形成された窪み１２が単独に点在しているため、ソルダレジストインキ３２の液ダレを防止できる。これにより、ソルダレジスト層３３は、その端部３３ａを含む略全領域において厚みが均一となる。よって、従来の配線基板を用いた場合に比べて、ソルダレジスト層３３の端部３３ａと配線３１とが強固に密着する。   First, as shown in FIG. 5A, a solder resist ink 32 is applied to a desired location on the wiring substrate 3 to form a solder resist layer 33. At this time, since the depressions 12 formed in the wiring substrate 3 are scattered independently, the dripping of the solder resist ink 32 can be prevented. Thereby, the thickness of the solder resist layer 33 is uniform in substantially the entire region including the end portion 33a. Therefore, the end portion 33a of the solder resist layer 33 and the wiring 31 are firmly adhered as compared with the case where a conventional wiring substrate is used.

そして、図５Ｂに示すように、ソルダレジスト層３３で覆われていない配線３１上にスズ３４をめっきする。この際、ソルダレジスト層３３の端部３３ａと配線３１とが強固に密着しているため、スズ３４の潜り込み現象を防止できる。   Then, as shown in FIG. 5B, tin 34 is plated on the wiring 31 that is not covered with the solder resist layer 33. At this time, since the end portion 33a of the solder resist layer 33 and the wiring 31 are in close contact with each other, it is possible to prevent the tin 34 from entering.

本発明は、例えば発光装置や受光装置等の光半導体装置や、テープキャリアパッケージ等に有用である。   The present invention is useful for optical semiconductor devices such as a light emitting device and a light receiving device, a tape carrier package, and the like.

Ａは本発明の第１実施形態に係るリードフレームの平面図であり、Ｂは本発明の第１実施形態に係るリードフレームの表面の部分拡大図である。A is a plan view of the lead frame according to the first embodiment of the present invention, and B is a partially enlarged view of the surface of the lead frame according to the first embodiment of the present invention. Ａは本発明の第２実施形態に係る半導体装置用パッケージ部品の平面図であり、ＢはＡのI-I線断面図である。A is a plan view of a package component for a semiconductor device according to a second embodiment of the present invention, and B is a cross-sectional view taken along line II of A. FIG. 本発明の第２実施形態に係る半導体装置用パッケージ部品を用いた半導体装置の断面図である。It is sectional drawing of the semiconductor device using the package component for semiconductor devices which concerns on 2nd Embodiment of this invention. 本発明の第３実施形態に係る配線基板の断面図である。It is sectional drawing of the wiring board which concerns on 3rd Embodiment of this invention. Ａ，Ｂは、本発明の第３実施形態に係る配線基板を用いたスズめっき工程を説明するための断面図である。A and B are sectional views for explaining a tin plating process using the wiring board according to the third embodiment of the present invention. Ａ，Ｂは、従来のスズめっき工程を説明するための断面図である。A and B are sectional views for explaining a conventional tin plating process.

符号の説明Explanation of symbols

１ リードフレーム（配線）
２ 半導体装置用パッケージ部品
３ 配線基板
１１ａ，１１ｂ インナーリード
１１ｃ アウターリード
１２ 窪み
２０ 半導体装置
２１ 筐体
２１ａ 収容体
２１ｂ 基体
２５ 半導体素子
２６ 封止樹脂層
２７ ワイヤ
２８ 端子
３０ 電気絶縁性基材
３１ 配線
３２ ソルダレジストインキ
３３ ソルダレジスト層
３３ａ 端部
３４ スズ
２１１ａ 収容部 1 Lead frame (wiring)
2 Semiconductor Device Package Parts 3 Wiring Boards 11a, 11b Inner Lead 11c Outer Lead 12 Dimple 20 Semiconductor Device 21 Housing 21a Housing 21b Base 25 Semiconductor Element 26 Sealing Resin Layer 27 Wire 28 Terminal 30 Electrical Insulating Base Material 31 Wiring 32 Solder resist ink 33 Solder resist layer 33a End 34 Tin 211a Housing

Claims (6)

電子素子を実装するための配線であって、
表面の略全面に、各々単独に点在する複数の窪みが形成されていることを特徴とする配線。 Wiring for mounting electronic elements,
A wiring characterized in that a plurality of depressions that are individually scattered are formed on substantially the entire surface. 配線と、前記配線上の外部接続箇所を除く領域に形成された筐体とを含む半導体装置用パッケージ部品であって、
前記配線は、請求項１に記載の配線であり、かつ少なくとも１対のリードを含み、
前記筐体は、前記１対のリードに跨って形成され、かつ半導体素子を収容するための収容部が設けられていることを特徴とする半導体装置用パッケージ部品。 A package component for a semiconductor device including a wiring and a housing formed in a region excluding external connection portions on the wiring,
The wiring is the wiring according to claim 1 and includes at least one pair of leads,
The package part for a semiconductor device, wherein the housing is formed across the pair of leads and provided with a housing part for housing a semiconductor element. 前記筐体は、熱可塑性樹脂からなる請求項２に記載の半導体装置用パッケージ部品。   The package part for a semiconductor device according to claim 2, wherein the casing is made of a thermoplastic resin. 電気絶縁性基材と、前記電気絶縁性基材上に形成された配線とを含む配線基板であって、
前記配線は、請求項１に記載の配線であることを特徴とする配線基板。 A wiring board including an electrically insulating substrate and wiring formed on the electrically insulating substrate,
The wiring board according to claim 1, wherein the wiring is the wiring according to claim 1. 前記電気絶縁性基材は、可撓性を有する基材である請求項４に記載の配線基板。   The wiring board according to claim 4, wherein the electrically insulating substrate is a flexible substrate. 前記可撓性を有する基材は、ポリイミドからなる請求項５に記載の配線基板。   The wiring substrate according to claim 5, wherein the flexible base material is made of polyimide.
JP2006111203A 2006-04-13 2006-04-13 Wiring, package parts for semiconductor device using same, and wiring board Withdrawn JP2007287800A (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9412923B2 (en) 2010-11-02 2016-08-09 Dai Nippon Printing Co., Ltd. Lead frame for mounting LED elements, lead frame with resin, method for manufacturing semiconductor devices, and lead frame for mounting semiconductor elements
US9824950B2 (en) 2012-12-19 2017-11-21 Fuji Electric Co., Ltd. Semiconductor device
US9887331B2 (en) 2010-03-30 2018-02-06 Dai Nippon Printing Co., Ltd. LED leadframe or LED substrate, semiconductor device, and method for manufacturing LED leadframe or LED substrate

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9887331B2 (en) 2010-03-30 2018-02-06 Dai Nippon Printing Co., Ltd. LED leadframe or LED substrate, semiconductor device, and method for manufacturing LED leadframe or LED substrate
US9412923B2 (en) 2010-11-02 2016-08-09 Dai Nippon Printing Co., Ltd. Lead frame for mounting LED elements, lead frame with resin, method for manufacturing semiconductor devices, and lead frame for mounting semiconductor elements
US9773960B2 (en) 2010-11-02 2017-09-26 Dai Nippon Printing Co., Ltd. Lead frame for mounting LED elements, lead frame with resin, method for manufacturing semiconductor devices, and lead frame for mounting semiconductor elements
US9824950B2 (en) 2012-12-19 2017-11-21 Fuji Electric Co., Ltd. Semiconductor device

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