JP2007266457A - Ceramic electronic component - Google Patents

Ceramic electronic component Download PDF

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JP2007266457A
JP2007266457A JP2006091650A JP2006091650A JP2007266457A JP 2007266457 A JP2007266457 A JP 2007266457A JP 2006091650 A JP2006091650 A JP 2006091650A JP 2006091650 A JP2006091650 A JP 2006091650A JP 2007266457 A JP2007266457 A JP 2007266457A
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plating
ceramic
electronic component
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JP5000912B2 (en
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Takashi Kajino
隆 楫野
Hisashi Ota
尚志 太田
Toshiyuki Abe
寿之 阿部
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TDK Corp
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a ceramic electronic component, for which the peeling of an external electrode after being left under an initial high-temperature and high-humidity environment is fully suppressed, and mass productivity is improved. <P>SOLUTION: The ceramic electronic component 1 comprises a ceramic element 5 having a ceramic element body 2; and external electrodes 20a and 20b, having base electrode layers 6a and 6b formed on the outer surface of the ceramic element 5; and terminal electrode layers 12a and 12b formed on the base electrode layers 6a and 6b. The elongation of the length 5 to 30 μm is formed, in a direction along the surface of the ceramic element body 2 at the end parts of the terminal electrode layers 12a and 12b. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

本発明は、セラミック素体を備えるセラミック電子部品に関する。   The present invention relates to a ceramic electronic component including a ceramic body.

バリスタ、サーミスタ等の耐薬品性の乏しいセラミック電子部品は、一般に、セラミック素体の表面にガラス等の耐薬品性の高いコーティング層を形成して用いられている。しかし、コーティング層を形成するために工程が複雑となり、量産性に劣るという問題がある。一方耐薬品性の乏しいセラミック電子部品をコーティング層なしで形成すると、工程が簡略で量産性には優れるものの、素体の外表面に形成された外部電極の信頼性に問題が生じる。   Ceramic electronic components having poor chemical resistance such as varistors and thermistors are generally used by forming a coating layer having high chemical resistance such as glass on the surface of a ceramic body. However, the process is complicated to form the coating layer, and there is a problem that the productivity is inferior. On the other hand, when a ceramic electronic component having poor chemical resistance is formed without a coating layer, the process is simple and excellent in mass productivity, but there is a problem in the reliability of the external electrode formed on the outer surface of the element body.

多くの場合、外部電極はその少なくとも一部がめっき法により形成される。しかし、コーティング層が無い場合にはセラミック素体の電気抵抗が比較的低いと、めっき工程においてめっき層が目標とする厚さ以上の長さになるまでセラミック素体の表面に沿って成長する、いわゆるめっき伸びが発生する傾向にある。このめっき伸びが大きくなると端子電極同士の短絡が生じる場合がある。   In many cases, at least a part of the external electrode is formed by a plating method. However, when there is no coating layer, if the electrical resistance of the ceramic body is relatively low, the plating layer grows along the surface of the ceramic body until the plating layer becomes longer than the target thickness in the plating process. So-called plating elongation tends to occur. When this plating elongation increases, a short circuit between the terminal electrodes may occur.

そこで、例えば、セラミック素体の表面にLi、Na等のアルカリ金属をドープして、素体表面を高抵抗化する方法によってめっき伸びを抑制することが検討されている(特許文献1)。
特開平9−246017号公報
Therefore, for example, it has been studied to suppress plating elongation by a method of doping the surface of the ceramic body with an alkali metal such as Li or Na to increase the resistance of the surface of the body (Patent Document 1).
Japanese Patent Laid-Open No. 9-246017

しかし、耐薬品性の乏しいセラミック電子部品をコーティング層なしで形成する場合、外部電極の剥離強度が必ずしも十分でなく、特に高温高湿環境下に放置した後に外部電極の剥離を生じ易いという問題があった。   However, when a ceramic electronic component with poor chemical resistance is formed without a coating layer, the peel strength of the external electrode is not necessarily sufficient, and the external electrode is liable to peel off especially after being left in a high temperature and high humidity environment. there were.

そこで、本発明は、初期及び高温高湿環境下に放置した後における外部電極の剥離が十分に抑制されたセラミック電子部品を提供することを目的とする。   Accordingly, an object of the present invention is to provide a ceramic electronic component in which peeling of an external electrode is sufficiently suppressed after being left in an initial stage and a high temperature and high humidity environment.

本発明は、セラミック素体を有するセラミック素子と、該セラミック素子の外表面に形成された下地電極層及び当該下地電極層上に形成された端子電極層を有する外部電極とを備え、端子電極層の端部においてセラミック素体の表面に沿う方向に5〜30μmの長さの伸びが形成されている、セラミック電子部品である。   The present invention comprises a ceramic element having a ceramic body, a base electrode layer formed on the outer surface of the ceramic element, and an external electrode having a terminal electrode layer formed on the base electrode layer, and a terminal electrode layer This is a ceramic electronic component in which an extension having a length of 5 to 30 μm is formed in a direction along the surface of the ceramic body.

端部においてセラミック素体の表面に沿う方向に上記特定範囲の長さの伸びが形成されていることにより、上記本発明に係るセラミック電子部品は初期及び高温高湿環境下に放置した後における外部電極の剥離が十分に抑制されたものとなった。本発明者らは、上記課題を解決すべく鋭意検討の結果、初期及び高温高湿環境下に放置後の外部電極の剥離強度が伸びの長さの影響を大きく受けることを見出し、この知見に基づいて更なる検討を重ねた結果、上記本発明の完成に至ったものである。なお、この伸びは、端子電極層がめっき法により形成されたものである場合はいわゆるめっき伸びに相当するものである。   By extending the length of the specific range in the direction along the surface of the ceramic body at the end, the ceramic electronic component according to the present invention is externally exposed after being left in an initial and high temperature and high humidity environment. The electrode peeling was sufficiently suppressed. As a result of intensive studies to solve the above-mentioned problems, the present inventors have found that the peel strength of the external electrode after being left in the initial and high-temperature and high-humidity environment is greatly affected by the length of elongation. As a result of further studies based on this, the present invention has been completed. This elongation corresponds to so-called plating elongation when the terminal electrode layer is formed by plating.

端子電極とセラミック素体の界面の密着性は比較的低いことから、上記伸びが30μmよりも大きいと外部電極の剥離強度が低下すると考えられる。一方、上記伸びが5μmよりも小さいと、高温高湿環境下でセラミック素体と端子電極の界面に水が浸入して、下部電極層やセラミック素体が進行し易くなるために、外部電極の剥離強度が低下すると考えられる。   Since the adhesiveness at the interface between the terminal electrode and the ceramic body is relatively low, it is considered that the peel strength of the external electrode is lowered when the elongation is larger than 30 μm. On the other hand, if the elongation is smaller than 5 μm, water penetrates into the interface between the ceramic body and the terminal electrode in a high temperature and high humidity environment, and the lower electrode layer and the ceramic body are likely to advance. It is considered that the peel strength decreases.

上記端子電極層はめっき法により形成された電極層であることが好ましい。めっき法により形成された端子電極層はセラミック素体との密着性が特に弱くなる傾向にあり、本発明による剥離強度向上が特に有用である。   The terminal electrode layer is preferably an electrode layer formed by a plating method. The terminal electrode layer formed by the plating method tends to have particularly weak adhesion to the ceramic body, and the peel strength improvement according to the present invention is particularly useful.

上記端子電極層は、下部電極層上に形成されたNiめっき層と、当該Niめっき層上に形成されたSnめっき層とを有することが好ましい。また、上記セラミック素体はZnOを含むセラミック材料からなることが好ましい。   The terminal electrode layer preferably has a Ni plating layer formed on the lower electrode layer and a Sn plating layer formed on the Ni plating layer. The ceramic body is preferably made of a ceramic material containing ZnO.

本発明によれば、初期及び高温高湿環境下に放置した後における外部電極の剥離が十分に抑制されたセラミック電子部品が提供される。   ADVANTAGE OF THE INVENTION According to this invention, the ceramic electronic component by which peeling of the external electrode after leaving it in an initial stage and a high-temperature, high-humidity environment was fully suppressed is provided.

以下、本発明の好適な実施形態について詳細に説明する。ただし、本発明は以下の実施形態に限定されるものではない。   Hereinafter, preferred embodiments of the present invention will be described in detail. However, the present invention is not limited to the following embodiments.

図1は、本発明に係るセラミック電子部品の一実施形態を示す断面図である。図1に示すセラミック電子部品1は、外部に露出しているセラミック素体2及びこれの内部に設けられた内部導電体層4a,4bを有するセラミック素子5と、内部導電体層4a又は4bとそれぞれ電気的に接続されるようにセラミック素子5の外表面に設けられた1対の外部電極20a,20bと、を備える。セラミック電子部品1は、チップバリスタ等として好適に用いられる。その場合、内部導電体層は一般に内部電極と称される。すなわち、内部導電体層4a,4bは一対の内部電極を構成している。外部電極20aは内部導電体層4aに、外部電極20bは内部導電体層4bにそれぞれ接続されている。   FIG. 1 is a cross-sectional view showing an embodiment of a ceramic electronic component according to the present invention. A ceramic electronic component 1 shown in FIG. 1 includes a ceramic body 2 exposed to the outside, a ceramic element 5 having internal conductor layers 4a and 4b provided therein, an internal conductor layer 4a or 4b, A pair of external electrodes 20a and 20b provided on the outer surface of the ceramic element 5 so as to be electrically connected to each other. The ceramic electronic component 1 is preferably used as a chip varistor or the like. In that case, the internal conductor layer is generally referred to as an internal electrode. That is, the internal conductor layers 4a and 4b constitute a pair of internal electrodes. The external electrode 20a is connected to the internal conductor layer 4a, and the external electrode 20b is connected to the internal conductor layer 4b.

セラミック素体2は、金属酸化物等のセラミック材料で構成される。金属酸化物としてはAlに代表されるアルミナや、ZnOに代表される酸化亜鉛が挙げられる。例えばチップバリスタの場合、セラミック素体2はZnOを主成分として含むセラミック材料からなることが好ましい。ZnOを用いる場合、Li等のアルカリ金属をppmオーダーの微量添加物として表面にドープして、セラミック素体2の電気抵抗を高めてもよい。 The ceramic body 2 is made of a ceramic material such as a metal oxide. Examples of the metal oxide include alumina typified by Al 2 O 3 and zinc oxide typified by ZnO. For example, in the case of a chip varistor, the ceramic body 2 is preferably made of a ceramic material containing ZnO as a main component. In the case of using ZnO, the surface of the ceramic element body 2 may be increased by doping the surface with an alkali metal such as Li as a trace amount additive in the order of ppm.

セラミック素体2の外表面上には、セラミック素体2を構成する材料と異なる材料(ガラス等)からなる保護層は形成されておらず、外表面のうち外部電極20a,20bによって覆われていない部分が外部に露出している。   On the outer surface of the ceramic body 2, a protective layer made of a material (glass or the like) different from the material constituting the ceramic body 2 is not formed and is covered with the external electrodes 20 a and 20 b on the outer surface. No part is exposed to the outside.

内部導電体層4a,4bの厚さは、通常0.5〜5μm程度である。内部導電体層4a,4bを構成する材料としては、セラミック電子部品の内部電極やコイルに通常用いられる導電性材料が特に制限なく用いられる。導電性材料の具体例としては、Pd又はPdを含む合金、Pt,Ni等が挙げられる。   The thickness of the internal conductor layers 4a and 4b is usually about 0.5 to 5 μm. As a material constituting the internal conductor layers 4a and 4b, a conductive material usually used for internal electrodes and coils of ceramic electronic components is used without particular limitation. Specific examples of the conductive material include Pd or an alloy containing Pd, Pt, Ni, and the like.

外部電極20a,20bは、内部導電体層4a又は4bと接する下地電極層6a,6b及びこれら下地電極層上に形成された端子電極層12a,12bを含む。端子電極層12a,12bは、Niめっき層8a,8b及びSnめっき層10a,10bがこの順に積層された構成を有する。   The external electrodes 20a and 20b include base electrode layers 6a and 6b in contact with the internal conductor layer 4a or 4b and terminal electrode layers 12a and 12b formed on the base electrode layers. The terminal electrode layers 12a and 12b have a configuration in which Ni plating layers 8a and 8b and Sn plating layers 10a and 10b are laminated in this order.

下地電極層6a,6bは内部導電体層4a,4bとオーミック接続を形成しており、また、めっき法で端子電極層12a,12bを形成する際の下地になる。下地電極層6a,6bは、例えば、金属微粉とガラス粉末(フリット)を含む。金属材料としては、例えばAg、Ag−Pd合金、Cu、Ni等が挙げられる。フリットは、いわゆる鉛フリーであることが好ましい。   The base electrode layers 6a and 6b form ohmic connections with the internal conductor layers 4a and 4b, and serve as bases for forming the terminal electrode layers 12a and 12b by plating. The base electrode layers 6a and 6b include, for example, metal fine powder and glass powder (frit). Examples of the metal material include Ag, Ag—Pd alloy, Cu, and Ni. The frit is preferably so-called lead-free.

フリットを含む下地電極層は、例えば、金属粒子及びフリットを含む無機の導電性ペーストの焼き付けにより形成される。導電性ペーストの焼き付けによる方法の場合、形成される下地電極層6a,6bの厚さは通常1〜50μm程度である。あるいは、マスクスパッタ法や樹脂導電性ペースト等により下地電極層を形成させてもよい。マスクスパッタ法は素体の温度を上げられない場合等に好適に用いられ、このとき形成される下地電極層の膜厚は通常0.1〜1μm程度である。マスクスパッタ法の場合、金属材料としてはCr/Cu、Ti/Cu等が用いられ、典型的には、Cr、Ti等の素体との密着性に優れる金属層を形成し、その上にCu等の電気抵抗の低い金属層を形成して、2層構造の下地電極層が形成される。一方、樹脂導電性ペーストは、上記無機の導電ペーストにおいてフリットを樹脂に置き換えたものである。この樹脂導電性ペーストは主としてコストダウンの目的で用いられる。これらの中でも、無機の導電性ペーストの焼き付けで下地電極層を形成する方法が現在最も一般的に用いられている。   The base electrode layer containing frit is formed, for example, by baking an inorganic conductive paste containing metal particles and frit. In the case of the method by baking conductive paste, the thickness of the base electrode layers 6a and 6b to be formed is usually about 1 to 50 μm. Alternatively, the base electrode layer may be formed by a mask sputtering method, a resin conductive paste, or the like. The mask sputtering method is preferably used when the temperature of the element body cannot be raised, and the thickness of the base electrode layer formed at this time is usually about 0.1 to 1 μm. In the case of the mask sputtering method, Cr / Cu, Ti / Cu or the like is used as the metal material. Typically, a metal layer having excellent adhesion with an element body such as Cr or Ti is formed, and Cu is formed thereon. A metal layer having a low electrical resistance such as a base layer is formed to form a base electrode layer having a two-layer structure. On the other hand, the resin conductive paste is obtained by replacing the frit in the inorganic conductive paste with a resin. This resin conductive paste is mainly used for the purpose of cost reduction. Among these methods, a method of forming a base electrode layer by baking an inorganic conductive paste is currently most commonly used.

端子電極層12a,12bは、その端部においてセラミック素体2の表面に沿って伸びている部分を有する。端子電極層12a,12bの伸びの長さTは、これらの端部におけるセラミック素体2の表面に沿う長さをtとし、下地電極層6a,6bの端部における端子電極層12a,12bの厚さをtとしたとき、T=t−tと定義される。 The terminal electrode layers 12a and 12b have portions extending along the surface of the ceramic body 2 at their ends. Terminal electrode layer 12a, the length T of the elongation 12b, and the length along the surface of the ceramic body 2 at the ends and t 1, the base electrode layer 6a, a terminal electrode layer 12a at the end of 6b, 12b when the thickness of the t 0, is defined as T = t 1 -t 0.

上記伸びの長さTは5〜30μmである。長さTが30μmを超えると外部電極20a,20bのセラミック素体2からの剥離を生じ易くなったり、端子電極層12a,12bが互いに接触して短絡が生じたりする場合がある。一方、本発明者による知見によれば、長さTを5μm以上とすることにより、特に高温高湿下に放置後の外部電極20a,20bのセラミック素体2からの剥離が効果的に抑制される。長さTはより好ましくは20μm以下であり、更に好ましくは10μm以下である。また、長さTはより好ましくは6μm以上であり、更に好ましくは7μm以上である。   The elongation length T is 5 to 30 μm. If the length T exceeds 30 μm, the external electrodes 20a and 20b may be easily peeled off from the ceramic body 2, or the terminal electrode layers 12a and 12b may come into contact with each other to cause a short circuit. On the other hand, according to the knowledge of the present inventor, by setting the length T to 5 μm or more, peeling of the external electrodes 20a and 20b from the ceramic body 2 after being left under high temperature and high humidity is effectively suppressed. The The length T is more preferably 20 μm or less, and even more preferably 10 μm or less. The length T is more preferably 6 μm or more, and further preferably 7 μm or more.

Niめっき層8a,8b及びSnめっき層10a,10bから構成される端子電極層12a,12bは、下地電極層6を覆うように形成されている。端子電極層12a,12bの端部の伸びている部分以外においては、Niめっき層8a,8bの厚さは通常0.5〜3μm程度であり、Snめっき層10a,10bの厚さは通常2〜6μm程度である。   Terminal electrode layers 12 a and 12 b composed of the Ni plating layers 8 a and 8 b and the Sn plating layers 10 a and 10 b are formed so as to cover the base electrode layer 6. Except for the extended portions of the end portions of the terminal electrode layers 12a and 12b, the thickness of the Ni plating layers 8a and 8b is usually about 0.5 to 3 μm, and the thickness of the Sn plating layers 10a and 10b is usually 2 About 6 μm.

セラミック電子部品1は、例えば、少なくとも一部の表面が外部に露出しているセラミック素体2及びこれの内部に設けられた内部導電体層4a,4bを有するセラミック素子5の外表面に、下地電極層6a,6bを内部導電体層4a又は4bと電気的に接続されるように形成する下地電極層形成工程と、下地電極層6a,6b上に端子電極層12a,12bを形成して、下地電極層6a,6b及び端子電極層12a,12bを有する外部電極20a,20bを備えるセラミック電子部品1を得る端子電極層形成工程と、を備える製造方法により、得ることができる。   The ceramic electronic component 1 includes, for example, a ceramic base body 2 having at least a part of the surface exposed to the outside and an outer surface of a ceramic element 5 having internal conductor layers 4a and 4b provided therein, A base electrode layer forming step of forming the electrode layers 6a and 6b so as to be electrically connected to the internal conductor layer 4a or 4b, and forming the terminal electrode layers 12a and 12b on the base electrode layers 6a and 6b, And a terminal electrode layer forming step of obtaining a ceramic electronic component 1 including external electrodes 20a and 20b having base electrode layers 6a and 6b and terminal electrode layers 12a and 12b.

セラミック素子5は、当業者には理解されるように、セラミック電子部品の製造において通常行われている方法に従って得ることができる。具体的には、例えば、金属酸化物等を含有するセラミックグリーンシート及び金属粒子等を含有する導電体ペースト層が交互に積層された積層体を含む積層構造体を焼成する焼成工程により、セラミック素子5が得られる。   As understood by those skilled in the art, the ceramic element 5 can be obtained in accordance with a method commonly used in the production of ceramic electronic components. Specifically, for example, a ceramic element is formed by a firing step of firing a laminated structure including a laminate in which a ceramic green sheet containing a metal oxide or the like and a conductive paste layer containing metal particles or the like are alternately laminated. 5 is obtained.

下地電極層6a,6bは、Ag粒子等の金属微粉及びガラス粉末(好ましくは鉛フリーのガラスフリット)を含む導電体ペーストをサーミスタ素子5の両側面に塗布し、これを加熱して焼き付け処理を行うことにより形成することができる。   For the base electrode layers 6a and 6b, a conductive paste containing fine metal powder such as Ag particles and glass powder (preferably lead-free glass frit) is applied to both side surfaces of the thermistor element 5, and this is heated and baked. It can be formed by doing.

端子電極層12a,12bは、電気めっき又は無電解めっきによって形成させることができる。めっきの際の電流密度やめっき時間、温度、錯化剤の種類及びその濃度、めっき液のpHや導電率等の条件を適宜適正化することにより、端子電極層12a,12bの端部における伸びの長さTが5〜30μmの範囲内にあるセラミック電子部品を得ることが可能である。通常、複数のチップについて同時にめっき処理を行うが、この場合、得られたセラミック電子部品の中から長さTが5〜30μmであるものを選択して抜き出すことができる。   The terminal electrode layers 12a and 12b can be formed by electroplating or electroless plating. By appropriately optimizing conditions such as current density, plating time, temperature, type and concentration of complexing agent, pH of plating solution, conductivity, etc. during plating, elongation at the end portions of the terminal electrode layers 12a and 12b It is possible to obtain a ceramic electronic component having a length T of 5 to 30 μm. Usually, a plurality of chips are simultaneously plated. In this case, a ceramic electronic component having a length T of 5 to 30 μm can be selected and extracted.

Niめっき層8a,8bは、例えば、Niイオン及びアンモニア等の錯化剤を含有するNiめっき液を用いた電気めっきによって形成される。Niイオンは、スルファミン酸Ni、硫酸Ni、塩化Ni等のNi塩の溶解により、めっき液中に導入される。   The Ni plating layers 8a and 8b are formed by electroplating using a Ni plating solution containing a complexing agent such as Ni ions and ammonia, for example. Ni ions are introduced into the plating solution by dissolving Ni salts such as Ni sulfamate, Ni sulfate, Ni chloride and the like.

Niめっき液のpHは5.5〜7であることが好ましい。このpHが5.5未満であると素体の溶出量及びエッチング量が大きくなる傾向にあり、また、外部電極20a,20bの剥離強度が低下する傾向にある。一方、めっき液のpHが7を超えるとめっき伸びが大きくなって、得られるセラミック電子部品における長さTを30μm以下とすることが困難になる傾向にある。同様の観点から、Niめっき液のpHはより好ましくは5.7以上であり、また、より好ましくは6.5以下である。   The pH of the Ni plating solution is preferably 5.5-7. If the pH is less than 5.5, the amount of elution and etching of the element body tend to increase, and the peel strength of the external electrodes 20a, 20b tends to decrease. On the other hand, when the pH of the plating solution exceeds 7, the plating elongation increases, and it tends to be difficult to make the length T of the obtained ceramic electronic component 30 μm or less. From the same viewpoint, the pH of the Ni plating solution is more preferably 5.7 or higher, and more preferably 6.5 or lower.

Niめっき液の導電率は、めっき伸びの抑制や、1回の工程でより多くのチップのめっき処理が可能になるという点から、電気めっきを行う温度において70mS/cm以上であることが好ましい。めっき液に塩化アンモニウム等を含有させることにより、めっき液の導電率を70mS/cm以上とすることができる。この場合、めっき液における塩化アンモニウムの濃度は10g/L以上とすることが好ましい。   The electrical conductivity of the Ni plating solution is preferably 70 mS / cm or more at the temperature at which electroplating is performed, from the viewpoint of suppressing plating elongation and enabling more chips to be plated in one step. By including ammonium chloride or the like in the plating solution, the conductivity of the plating solution can be set to 70 mS / cm or more. In this case, the concentration of ammonium chloride in the plating solution is preferably 10 g / L or more.

めっき液においてアンモニア以外の錯化剤を用いる場合、そのNiイオンに対するモル比は0.1以下であることが好ましい。錯化剤としてアンモニアを用いる場合には、通常、アンモニアによってめっき液のpHも調整される。すなわち、アンモニアはpH調整剤としても機能させることができる。アンモニア以外の錯化剤としては、グリシン、クエン酸ナトリウム、グルコン酸ナトリウム等がある。   When a complexing agent other than ammonia is used in the plating solution, the molar ratio to Ni ions is preferably 0.1 or less. When ammonia is used as the complexing agent, the pH of the plating solution is usually adjusted with ammonia. That is, ammonia can function as a pH adjuster. Examples of complexing agents other than ammonia include glycine, sodium citrate, and sodium gluconate.

Niめっき層8a,8bを形成させる際には、めっき液の温度を20〜50℃とすることが好ましい。めっき液の温度を20〜50℃の間に維持することにより、素体やフリットの溶出抑制や、めっき伸び抑制といった効果が得られる。   When forming the Ni plating layers 8a and 8b, the temperature of the plating solution is preferably set to 20 to 50 ° C. By maintaining the temperature of the plating solution between 20 ° C. and 50 ° C., effects such as suppression of elution of the element body and frit and suppression of plating elongation can be obtained.

Snめっき層10a,10bは、Snめっき層を形成する方法として通常行われている条件で電気めっき又は無電解めっき行うことにより形成される。   The Sn plating layers 10a and 10b are formed by performing electroplating or electroless plating under conditions normally performed as a method for forming the Sn plating layer.

なお、本実施形態のように端子電極層12a,12bがNiめっき層8a,8b及びSnめっき層10a,10bから構成されるのに代えて、他の金属のめっき層を設けてもよい。例えば、Niめっき層8a,8bに代えて、半田付けの際の食われを防止する金属(バリアメタル)であるPt、Pd、Ni−P合金、Ni−B合金等により形成されるめっき層が好ましく用いられる。また、Snめっき層に代えて、半田付け性の良好な金属、例えば共晶半田、高温半田、Au等により形成されるめっき層が好ましく用いられる。また、Niめっき層等の単層から端子電極層が構成されていてもよい。   Instead of the terminal electrode layers 12a, 12b being composed of the Ni plating layers 8a, 8b and the Sn plating layers 10a, 10b as in the present embodiment, other metal plating layers may be provided. For example, instead of the Ni plating layers 8a and 8b, a plating layer formed of Pt, Pd, Ni—P alloy, Ni—B alloy or the like, which is a metal (barrier metal) that prevents erosion during soldering, is used. Preferably used. Moreover, it replaces with Sn plating layer, and the plating layer formed with a metal with favorable solderability, for example, eutectic solder, high temperature solder, Au etc., is used preferably. Moreover, the terminal electrode layer may be comprised from single layers, such as Ni plating layer.

外部電極は、図1のようにセラミック素体の側面から両主面にかけて形成されるのに代えて、セラミック素体のいずれか一方の主面のみに形成されていてもよいし、側面のみに形成されていてもよい。   The external electrode may be formed only on one of the main surfaces of the ceramic body instead of being formed from the side surface of the ceramic body to both main surfaces as shown in FIG. It may be formed.

本発明に係るセラミック電子部品は、チップバリスタの他、チップコンデンサ、チップコイル、NTCサーミスタ等のチップ部品、またこれらを複合してなるローパスフィルター、ハイパスフィルター等のモジュール等のセラミック部に適用することができる。   The ceramic electronic component according to the present invention is applied to a chip part such as a chip capacitor, a chip coil, and an NTC thermistor in addition to a chip varistor, and a ceramic part such as a module such as a low-pass filter and a high-pass filter formed by combining them. Can do.

以下、実施例を挙げて本発明についてより具体的に説明する。ただし、本発明は以下の実施例に限定されるものではない。   Hereinafter, the present invention will be described more specifically with reference to examples. However, the present invention is not limited to the following examples.

実施例1
ZnOを主成分とする素体を有する素体上に下地電極層としてCu焼付電極を形成させたバリスタチップ100000個を容積1Lのバレルに投入し、下地電極層上に厚さ1μmのNiめっき層を形成させた。めっき液は、硫酸Ni濃度を100g/L、塩化Ni濃度を10g/Lとし、KOHでpHを6.5に調整したものを用いた。バレル回転数は10rpm、液温度は22℃とし、電流値は成膜レートが0.5μm/時になるように調整した。
Example 1
Thousands of varistor chips each having a Cu-baked electrode formed as a base electrode layer on a base body having a base body containing ZnO as a base electrode layer are placed in a 1 L barrel, and a Ni plating layer having a thickness of 1 μm is formed on the base electrode layer. Formed. The plating solution used was a sulfuric acid Ni concentration of 100 g / L, a Ni chloride concentration of 10 g / L, and a pH adjusted to 6.5 with KOH. The barrel rotation speed was 10 rpm, the liquid temperature was 22 ° C., and the current value was adjusted so that the film formation rate was 0.5 μm / hour.

続いて、石原薬品(株)製のめっき液NB−RZを使用して、Niめっき層上に厚さ2μmのSnめっき層を形成させた。Snめっきは、バリスタチップ100000個を投入し、バレル回転数は10rpm、液温度は22℃、電流値は成膜レートが1.0μm/時になるように調整した条件で行った。   Subsequently, an Sn plating layer having a thickness of 2 μm was formed on the Ni plating layer using a plating solution NB-RZ manufactured by Ishihara Pharmaceutical Co., Ltd. Sn plating was performed under the conditions that 100,000 varistor chips were charged, the barrel rotation speed was 10 rpm, the liquid temperature was 22 ° C., and the current value was adjusted so that the film formation rate was 1.0 μm / hour.

0603、1005、1608の3種類のチップサイズの場合について同様のめっき処理を行った。   The same plating process was performed for three types of chip sizes 0603, 1005, and 1608.

めっき後のチップをめっき伸びの長さに応じて表1に示すランクに分類し、各ランクごとにランダムに抜き取られた100個のチップについて、セロテープ(登録商標)を用いて電極のピール試験を行った。電極片がテープへの付着により剥ぎ取られたチップを不良としてカウントした。更に、ランク1〜12のチップについては、85℃、85%RHの高温高湿環境下に1000時間放置する長期信頼性試験を行った後、上記と同様のピール試験を行って不良数をカウントした。   The chip after plating is classified into the ranks shown in Table 1 according to the length of plating elongation, and the peel test of the electrode is performed using cello tape (registered trademark) on 100 chips randomly extracted for each rank. went. The chip from which the electrode piece was peeled off due to adhesion to the tape was counted as defective. Furthermore, for rank 1 to 12 chips, after performing a long-term reliability test for 1000 hours in a high-temperature and high-humidity environment at 85 ° C. and 85% RH, the same peel test as above is performed to count the number of defects. did.

表1に示す結果から、めっき伸びの長さが大きくなるほどピール試験不良数が増加する傾向にあり、めっき伸びの長さが30μm以下の場合に電極剥離を生じないことがわかる。一方、長期信頼性試験後のピール試験においては、めっき伸びの長さが5μmを下回ったときに電極剥離が生じることがわかる。すなわち、めっき伸びの長さが5〜30μmであるときに、初期及び長期信頼性試験後のいずれにおいても十分な電極剥離強度が得られることが確認された。   From the results shown in Table 1, it can be seen that the number of peel test defects tends to increase as the length of plating elongation increases, and that electrode peeling does not occur when the length of plating elongation is 30 μm or less. On the other hand, in the peel test after the long-term reliability test, it can be seen that electrode peeling occurs when the length of plating elongation is less than 5 μm. That is, it was confirmed that when the length of the plating elongation is 5 to 30 μm, sufficient electrode peel strength can be obtained both in the initial stage and after the long-term reliability test.

Figure 2007266457
Figure 2007266457

実施例2
Niめっき用のめっき液としてスルファミン酸Ni濃度が100g/L、塩化Niが10g/Lであり、KOHでpHを6.5に調整した液を用いた他は実施例1と同様にして、めっき層の形成及びそのピール試験を行った。表2に示されるように、めっき伸びの長さが大きくなるほど電極剥離を生じ易くなる傾向にあり、めっき伸びの長さが30μm以下の場合に電極剥離を生じないことがわかる。
Example 2
Plating was performed in the same manner as in Example 1 except that the plating solution for Ni plating was a sulfamic acid Ni concentration of 100 g / L, Ni chloride of 10 g / L, and a pH adjusted to 6.5 with KOH. Layer formation and its peel test were performed. As shown in Table 2, it can be seen that electrode peeling tends to occur more easily as the length of plating elongation increases, and electrode peeling does not occur when the length of plating elongation is 30 μm or less.

Figure 2007266457
Figure 2007266457

実施例3
めっき液として奥野製薬工業社製「ケミアロイ66」(商品名)を用い、奥野製薬工業社NNPプロセスの標準条件で前処理を行って、無電解めっきによってNiめっき層を形成させた。無電解めっきは、容積1Lのバレルにチップを100000個投入して、バレル回転数は10rpm、液温度は22℃、電流値は成膜レートが1μm/時になるように調整した条件で行った。Snめっきは実施例1と同様にして行った。
Example 3
Using “Kemialloy 66” (trade name) manufactured by Okuno Pharmaceutical Co., Ltd. as the plating solution, pretreatment was performed under the standard conditions of the NNP process of Okuno Pharmaceutical Co., Ltd., and an Ni plating layer was formed by electroless plating. The electroless plating was performed under the conditions that 100,000 chips were put into a 1 L barrel, the barrel rotation speed was 10 rpm, the liquid temperature was 22 ° C., and the current value was adjusted so that the film formation rate was 1 μm / hour. Sn plating was performed in the same manner as in Example 1.

めっき後のチップについて、実施例1と同様にしてピール試験を行った。表3に示されるように、めっき伸びの長さが大きくなるほど電極剥離を生じ易くなる傾向にあり、めっき伸びの長さが30μm以下の場合に電極剥離を生じないことがわかる。   About the chip | tip after plating, the peel test was done like Example 1. FIG. As shown in Table 3, it can be seen that electrode peeling tends to occur more easily as the length of plating elongation increases, and electrode peeling does not occur when the length of plating elongation is 30 μm or less.

Figure 2007266457
Figure 2007266457

実施例4
NiCuZnからなる素体を有するチップコイルについて、実施例1と同様にしてめっき層の形成及びピール試験を行った。表4に示されるように、めっき伸びの長さが大きくなるほど電極剥離を生じ易くなる傾向にあり、めっき伸びの長さが30μm以下の場合に電極剥離を生じないことがわかる。
Example 4
For the chip coil having the element body made of NiCuZn, the formation of the plating layer and the peel test were performed in the same manner as in Example 1. As shown in Table 4, it can be seen that electrode peeling tends to easily occur as the length of plating elongation increases, and that electrode peeling does not occur when the length of plating elongation is 30 μm or less.

Figure 2007266457
Figure 2007266457

実施例5
ZnOを1質量%含むコンデンサ材料からなる素体を有するチップコンデンサについて、実施例1と同様にしてめっき層の形成及びピール試験を行った。表5に示されるように、めっき伸びの長さが大きくなるほど電極剥離を生じ易くなる傾向にあり、めっき伸びの長さが30μm以下の場合に電極剥離を生じないことがわかる。
Example 5
For a chip capacitor having an element body made of a capacitor material containing 1% by mass of ZnO, a plating layer was formed and a peel test was conducted in the same manner as in Example 1. As shown in Table 5, it can be seen that electrode peeling tends to easily occur as the length of plating elongation increases, and electrode peeling does not occur when the length of plating elongation is 30 μm or less.

Figure 2007266457
Figure 2007266457

実施例6
ZnOを主成分とし、表面にLiをドープして表面抵抗を上げたチップバリスタについて、実施例1と同様にしてめっき層の形成及びピール試験を行った。表5に示されるように、めっき伸びの長さが大きくなるほど電極剥離を生じ易くなる傾向にあり、めっき伸びの長さが30μm以下の場合に電極剥離を生じないことがわかる。
Example 6
For the chip varistor whose surface resistance was increased by doping Li on the surface with ZnO as a main component, the formation of a plating layer and the peel test were performed in the same manner as in Example 1. As shown in Table 5, it can be seen that electrode peeling tends to easily occur as the length of plating elongation increases, and electrode peeling does not occur when the length of plating elongation is 30 μm or less.

Figure 2007266457
Figure 2007266457

以上の実験結果より、本発明に係るセラミック電子部品は、外部電極の剥離強度が十分に高いことが確認された。   From the above experimental results, it was confirmed that the ceramic electronic component according to the present invention has a sufficiently high peel strength of the external electrode.

本発明の製造方法により得られるセラミック電子部品の一実施形態を示す断面図である。It is sectional drawing which shows one Embodiment of the ceramic electronic component obtained by the manufacturing method of this invention.

符号の説明Explanation of symbols

1…セラミック電子部品、2…セラミック素体、4a,4b…内部導電体層、5…サーミスタ素子、6a,6b…下地電極層、8a,8b…Niめっき層、10a,10b…Snめっき層、12a,12b…端子電極層、20a,20b…外部電極、T…伸びの長さ。   DESCRIPTION OF SYMBOLS 1 ... Ceramic electronic component, 2 ... Ceramic body, 4a, 4b ... Internal conductor layer, 5 ... Thermistor element, 6a, 6b ... Base electrode layer, 8a, 8b ... Ni plating layer, 10a, 10b ... Sn plating layer, 12a, 12b ... terminal electrode layer, 20a, 20b ... external electrode, T ... length of extension.

Claims (4)

セラミック素体を有するセラミック素子と、
該セラミック素子の外表面に形成された下地電極層及び当該下地電極層上に形成された端子電極層を有する外部電極とを備え、
前記端子電極層の端部において前記セラミック素体の表面に沿う方向に5〜30μmの長さの伸びが形成されている、セラミック電子部品。
A ceramic element having a ceramic body;
An external electrode having a base electrode layer formed on the outer surface of the ceramic element and a terminal electrode layer formed on the base electrode layer;
A ceramic electronic component in which an extension having a length of 5 to 30 μm is formed in a direction along a surface of the ceramic body at an end portion of the terminal electrode layer.
前記端子電極層はめっき法により形成された電極層である、請求項1記載のセラミック電子部品。   The ceramic electronic component according to claim 1, wherein the terminal electrode layer is an electrode layer formed by a plating method. 前記端子電極層が、前記下部電極層上に形成されたNiめっき層と、当該Niめっき層上に形成されたSnめっき層とを有する、請求項1記載のセラミック電子部品。   The ceramic electronic component according to claim 1, wherein the terminal electrode layer has a Ni plating layer formed on the lower electrode layer and a Sn plating layer formed on the Ni plating layer. 前記セラミック素体がZnOを含むセラミック材料からなる、請求項1〜3のいずれか一項に記載のセラミック電子部品。   The ceramic electronic component according to claim 1, wherein the ceramic body is made of a ceramic material containing ZnO.
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012038917A (en) * 2010-08-06 2012-02-23 Murata Mfg Co Ltd Ceramic electronic component and method for manufacturing the same
KR20140119645A (en) * 2013-04-01 2014-10-10 가부시키가이샤 무라타 세이사쿠쇼 Monolithic ceramic electronic component
JP2015079897A (en) * 2013-10-18 2015-04-23 株式会社村田製作所 Method of manufacturing inductor, and inductor

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000058306A (en) * 1998-08-11 2000-02-25 Murata Mfg Co Ltd Chip-shaped electronic component
JP2001076929A (en) * 1999-09-03 2001-03-23 Murata Mfg Co Ltd Laminated type inductor
JP2003068508A (en) * 2001-08-24 2003-03-07 Murata Mfg Co Ltd Method for manufacturing multilayer chip varistor
JP2005002380A (en) * 2003-06-10 2005-01-06 Oizumi Seisakusho:Kk Method of applying nickel plating to electroconductive film on metallic oxide compacted sintered matter and nickel plating liquid composition for electrically conductive film
JP2005038901A (en) * 2003-07-15 2005-02-10 Mitsubishi Materials Corp Thermistor device and its manufacturing method
JP2006213946A (en) * 2005-02-02 2006-08-17 Murata Mfg Co Ltd Nickel plating solution, method for producing electronic parts, and electronic parts

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000058306A (en) * 1998-08-11 2000-02-25 Murata Mfg Co Ltd Chip-shaped electronic component
JP2001076929A (en) * 1999-09-03 2001-03-23 Murata Mfg Co Ltd Laminated type inductor
JP2003068508A (en) * 2001-08-24 2003-03-07 Murata Mfg Co Ltd Method for manufacturing multilayer chip varistor
JP2005002380A (en) * 2003-06-10 2005-01-06 Oizumi Seisakusho:Kk Method of applying nickel plating to electroconductive film on metallic oxide compacted sintered matter and nickel plating liquid composition for electrically conductive film
JP2005038901A (en) * 2003-07-15 2005-02-10 Mitsubishi Materials Corp Thermistor device and its manufacturing method
JP2006213946A (en) * 2005-02-02 2006-08-17 Murata Mfg Co Ltd Nickel plating solution, method for producing electronic parts, and electronic parts

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012038917A (en) * 2010-08-06 2012-02-23 Murata Mfg Co Ltd Ceramic electronic component and method for manufacturing the same
KR20140119645A (en) * 2013-04-01 2014-10-10 가부시키가이샤 무라타 세이사쿠쇼 Monolithic ceramic electronic component
JP2014212298A (en) * 2013-04-01 2014-11-13 株式会社村田製作所 Multilayer ceramic electronic component
US9343234B2 (en) 2013-04-01 2016-05-17 Murata Manufacturing Co., Ltd. Monolithic ceramic electronic component
KR101640534B1 (en) * 2013-04-01 2016-07-18 가부시키가이샤 무라타 세이사쿠쇼 Monolithic ceramic electronic component
JP2015079897A (en) * 2013-10-18 2015-04-23 株式会社村田製作所 Method of manufacturing inductor, and inductor

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