JP2006286724A - Wiring board and its manufacturing method - Google Patents

Wiring board and its manufacturing method Download PDF

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JP2006286724A
JP2006286724A JP2005101495A JP2005101495A JP2006286724A JP 2006286724 A JP2006286724 A JP 2006286724A JP 2005101495 A JP2005101495 A JP 2005101495A JP 2005101495 A JP2005101495 A JP 2005101495A JP 2006286724 A JP2006286724 A JP 2006286724A
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conductor layer
layer
wiring board
insulating
roughened
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JP4846258B2 (en
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Tomohiro Nitao
智広 仁田尾
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Kyocera SLC Technologies Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15172—Fan-out arrangement of the internal vias
    • H01L2924/15174—Fan-out arrangement of the internal vias in different layers of the multilayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Abstract

<P>PROBLEM TO BE SOLVED: To form a surface conductor layer which requires fine wiring precisely in a fine pattern, to suppress delamination by increasing the adhesive strength between conductor layers and an insulating substrate, and to achieve a good electric connection with a semiconductor element and an external electric circuit substrate. <P>SOLUTION: The insulating substrate 2 is made by stacking a plurality of insulation layers 1. In the surface of the insulation substrate and between the insulation layers 1, conductor layers 3 consisting of metal foils are embedded. The surface conductor layer 3A embedded in the surface of the insulating substrate 2 has a crystal grain diameter smaller than that of an inner conductor layer 3B embedded between the insulation layers 1. The surface conductor layer 3A and the inner conductor layer 3B are both formed by electrolytic plating. In the surface conductor layer 3A, a principal plane on the side embedded in the insulation layer 1 is a matted surface and an exposed principal plane is a shiny surface. In the inner conductor layer 3B, a principal plane in the embedded side is a shiny surface roughed by a liquid treatment by acid, etc. and a principal plane on the opposite side is a matted surface. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明は、半導体集積回路素子等の半導体素子を搭載する用途に好適な配線基板及びその製造方法に関するものである。   The present invention relates to a wiring board suitable for a purpose of mounting a semiconductor element such as a semiconductor integrated circuit element and a method for manufacturing the same.

一般に、現在の電子機器は、移動体通信機器に代表されるように小型化、薄型化、高機能化が要求されてきており、このような電子機器に使用される半導体素子を搭載するための配線基板にも小型化、薄型化、高密度配線化が求められてきている。そして、それを実現するために配線基板における信号導体等を含む配線導体の幅を細くするとともにその間隔を狭くし、更に配線導体形成用の導体層と絶縁層とを交互に多層に積層して配線することにより高密度配線化が図られている。   In general, current electronic devices are required to be downsized, thinned, and highly functional, as represented by mobile communication devices, and for mounting semiconductor elements used in such electronic devices. There is also a demand for wiring boards that are smaller, thinner, and denser. In order to achieve this, the width of the wiring conductor including the signal conductor in the wiring board is narrowed and the interval is narrowed, and the conductor layers for forming the wiring conductor and the insulating layers are alternately laminated in multiple layers. High-density wiring is achieved by wiring.

このような配線基板としては、ガラス繊維基材にエポキシ樹脂を含浸させるとともに硬化させて成る絶縁層の上下面に金属箔から成る配線導体用の導体層を被着し、これら導体層を被着した絶縁層を、接着層を介して複数層積層圧着して多層化することにより製作された配線基板が知られている。しかしながら、この配線基板は、絶縁層の表面と導体層の表面との高さの相違により表面が凹凸状態になってしまうとともに、導体層のパターン間に接着層が十分に充填されずに隙間が生じてしまい、その隙間に湿気が浸入し配線導体間の絶縁性が低下してしまうという問題点があった。   As such a wiring board, a conductive layer for a wiring conductor made of metal foil is deposited on the upper and lower surfaces of an insulating layer formed by impregnating and curing a glass fiber base material with an epoxy resin, and these conductive layers are deposited. There is known a wiring board manufactured by laminating a plurality of laminated insulating layers via an adhesive layer to form a multilayer. However, in this wiring board, the surface becomes uneven due to the difference in height between the surface of the insulating layer and the surface of the conductor layer, and the adhesive layer is not sufficiently filled between the patterns of the conductor layer, and there is no gap. As a result, there is a problem that moisture enters the gap and the insulation between the wiring conductors decreases.

そこで、このような問題点を解決するために、転写フィルム表面に形成された銅箔等の金属箔から成る配線導体用の導体層を未硬化の熱硬化性樹脂を含有する絶縁シートの表面に圧接して埋入させた後、転写フィルムを除去することによって導体層が転写された未硬化の絶縁層を複数枚作成し、これらを積層圧着後、一括して熱硬化させる一括硬化によって製作した多層配線基板が提案されている（特許文献１の「従来技術」欄）。当該多層配線基板は、工程を簡略化することを可能にするとともに、転写時に金属箔から成る導体層を未硬化状態の絶縁層に両者の表面が略同一面となるように埋入することを可能にするので、導体層と絶縁層との間に積層不良を生じることがない等の多くの利点を有するものである。   Therefore, in order to solve such problems, a conductor layer for a wiring conductor made of a metal foil such as a copper foil formed on the surface of a transfer film is formed on the surface of an insulating sheet containing an uncured thermosetting resin. After pressing and embedding, the transfer film was removed to create a plurality of uncured insulating layers onto which the conductor layer was transferred. A multilayer wiring board has been proposed ("Prior Art" column of Patent Document 1). The multilayer wiring board makes it possible to simplify the process and to embed a conductor layer made of a metal foil in an uncured insulating layer so that both surfaces are substantially flush with each other at the time of transfer. Therefore, it has many advantages such as no occurrence of poor stacking between the conductor layer and the insulating layer.

このような多層配線基板において導体層用に用いられる金属箔は、一般的には表面が平滑な電着ドラムの表面に電解めっき法によって金属膜を析出させる方法により形成されるものであり、その結晶粒径は0.2〜2.6μｍ程度である。そして金属箔のめっき液に触れる一方の面が、金属めっきの粒成長によって十点平均粗さ（Ｒｚ）が1.0〜7.0μｍの凹凸のついたマット面と呼ばれる粗化面となり、ドラム表面に接触する他方の面が、十点平均粗さ（Ｒｚ）が0.5〜3.5μｍのドラム表面に対応したシャイニー面と呼ばれる平滑面となる。また、転写フィルムに対して平滑面側が接着されてエッチングされることにより所定パターンの配線導体が形成されており、そのため導体層の絶縁層に埋入される側の主面は、凹凸のついた粗化面となっている。それにより、導体層が絶縁層に強固に接着される。なお、導体層は、配線パターン状にエッチング処理されることにより形成されるため、その側面はその粗さが1.0〜3.0μｍの平滑面となっている。   The metal foil used for the conductor layer in such a multilayer wiring board is generally formed by a method of depositing a metal film on the surface of an electrodeposition drum having a smooth surface by an electrolytic plating method. The crystal grain size is about 0.2 to 2.6 μm. Then, one surface that touches the plating solution of the metal foil becomes a roughened surface called an uneven mat surface having a ten-point average roughness (Rz) of 1.0 to 7.0 μm due to the growth of metal plating grains, and comes into contact with the drum surface. The other surface becomes a smooth surface called a shiny surface corresponding to the drum surface having a 10-point average roughness (Rz) of 0.5 to 3.5 μm. In addition, a wiring conductor having a predetermined pattern is formed by adhering and etching the smooth surface side with respect to the transfer film. Therefore, the main surface on the side embedded in the insulating layer of the conductor layer is uneven. It is a roughened surface. Thereby, the conductor layer is firmly bonded to the insulating layer. Since the conductor layer is formed by etching into a wiring pattern, its side surface is a smooth surface with a roughness of 1.0 to 3.0 μm.

ところで上記の多層配線基板においては、一般的に内層の導体層よりも表層の導体層に微細配線が要求され、近時は40μｍ以下の線幅の極めて微細なパターンが要求されるようになってきている。しかしながら、銅箔を凹凸のついた粗化面側から微細なパターンでエッチングすると、エッチング用のマスクと銅箔表面の凹部との間に微小な隙間が発生するため微細なパターンを精度良く形成することができず、パターンの形状が崩れて電気抵抗が増大したり、断線が発生したりしてしまうという問題点を有していた。また、粗化面と反対側の主面は平滑面であるため、内層の絶縁層に転写された導体層においては、この平滑な主面と当該導体層の上に積層される別の絶縁層との間の接着強度が小さく、そのため、配線基板に半導体素子を実装するための熱や半導体素子が作動時に発生する熱が加えられると、導体層の平滑な主面と絶縁層との間で剥離が発生し、その剥離を起点としたクラックが発生して周囲の配線導体を切断してしまうという問題点も有していた。   By the way, in the above-mentioned multilayer wiring board, fine wiring is generally required for the surface conductor layer rather than the inner conductor layer, and recently, an extremely fine pattern having a line width of 40 μm or less has been required. ing. However, if the copper foil is etched with a fine pattern from the roughened surface side with unevenness, a fine gap is generated between the etching mask and the concave portion of the copper foil surface, so that a fine pattern is formed with high accuracy. In other words, the pattern shape is broken, and the electrical resistance is increased or the wire breakage occurs. In addition, since the main surface opposite to the roughened surface is a smooth surface, in the conductor layer transferred to the inner insulating layer, another insulating layer laminated on the smooth main surface and the conductor layer. Therefore, when heat for mounting the semiconductor element on the wiring board or heat generated during operation of the semiconductor element is applied, the conductive layer between the smooth main surface of the conductor layer and the insulating layer There was also a problem that peeling occurred and a crack originated from the peeling to cut the surrounding wiring conductor.

当該問題点を解決するものとして、特許文献１は、転写フィルムに対して金属箔のマット面側を接着するとともに、金属箔のシャイニー面側をエッチング処理することにより粗化面とし、その後に金属箔を選択的にエッチングすることにより配線パターン状に導体層を形成する技術を開示している。形成された導体層は、絶縁シートに転写される。   As a solution to the problem, Patent Document 1 discloses that a matte surface side of a metal foil is bonded to a transfer film, and a shiny surface side of the metal foil is etched to form a roughened surface. A technique for forming a conductor layer in a wiring pattern by selectively etching a foil is disclosed. The formed conductor layer is transferred to the insulating sheet.

しかしながら当該技術では、転写フィルムと金属箔との間に微小な隙間が発生し易いため、多層配線基板の表層の導体に必要とされる微細なパターンを精度良く形成することは困難であるという問題点があった。また、導体層のマット面が多層配線基板の表面に露出することとなるので、マット面に形成された凹凸により導体層と半導体素子や外部電気回路基板との良好な接続が困難となってしまうという問題点があった。
特許第３０３７６６２号公報 However, in this technique, since a minute gap is easily generated between the transfer film and the metal foil, it is difficult to accurately form a fine pattern required for the conductor on the surface layer of the multilayer wiring board. There was a point. Further, since the mat surface of the conductor layer is exposed on the surface of the multilayer wiring board, the unevenness formed on the mat surface makes it difficult to connect the conductor layer to the semiconductor element or the external electric circuit board. There was a problem.
Japanese Patent No. 3037662

本発明は、かかる従来技術の問題点に鑑み完成されたものであり、その目的は、一般的に微細配線が要求される表層の導体層を微細なパターンで精度よく形成することを可能にするとともに、導体層と絶縁基板との間の接着強度を高めて剥離を抑え、且つ半導体素子や外部電気回路基板との良好な電気的接続を実現する多層構造の配線基板、及びその製造方法を提供することにある。   The present invention has been completed in view of the problems of the prior art, and an object thereof is to make it possible to accurately form a surface conductor layer that requires fine wiring with a fine pattern. In addition, a wiring board having a multilayer structure that enhances the adhesive strength between the conductor layer and the insulating substrate to suppress peeling and realizes good electrical connection with a semiconductor element or an external electric circuit board, and a method for manufacturing the same are provided. There is to do.

上記課題を解決し上記目的を達成するために、本発明のうち第１の態様に係るものは、複数層の導体層を有する多層構造の配線基板であって、絶縁基板と、前記絶縁基板の表面に埋設された金属箔から成る表面導体層と、前記絶縁基板の内部に埋設された金属箔から成る内部導体層と、を備えている。そして、前記表面導体層の結晶粒径が前記内部導体層の結晶粒径よりも小さく、前記表面導体層は、その埋設された側の主面がマット面又は粗化されたマット面から成る粗化面であるとともに、露出する側の主面がシャイニー面から成る非粗化面又は粗化されたシャイニー面から成る粗化面であり、前記内部導体層は、一主面がマット面から成る粗化面であり、他主面が粗化されたシャイニー面から成る粗化面となっている。   In order to solve the above-described problems and achieve the above object, a first aspect of the present invention is a wiring board having a multilayer structure having a plurality of conductive layers, the insulating substrate, and the insulating substrate. A surface conductor layer made of a metal foil embedded in the surface; and an inner conductor layer made of a metal foil embedded in the insulating substrate. The crystal grain size of the surface conductor layer is smaller than the crystal grain size of the internal conductor layer, and the surface conductor layer has a rough surface in which the main surface on the embedded side is a mat surface or a roughened mat surface. And the exposed main surface is a non-roughened surface made of a shiny surface or a roughened surface made of a roughened shiny surface, and the inner conductor layer has one main surface made of a matte surface. It is a roughened surface, and the other main surface is a roughened surface consisting of a roughened shiny surface.

この構成によれば、絶縁基板の表面に埋設された導体層である表面導体層の結晶粒径が絶縁基板の内部に埋設された導体層である内部導体層の結晶粒径よりも小さいことから、一般に微細配線が要求される表面導体層において、マット面の凹凸が小さいものとなる。それにより、表面導体層を微細なパターンで精度良く形成することが可能となる。また、表面導体層の埋設された側の主面がマット面又は粗化されたマット面から成る粗化面であるので、表面導体層と絶縁基板との間の接着強度を高めて剥離を抑えることができる。更に、表面導体層の露出する側の主面がシャイニー面から成る非粗化面又は粗化されたシャイニー面から成る粗化面であるので、凹凸が小さく、表面導体層と半導体素子や外部電気回路基板とを良好に接続することができる。また、内部導体層は、一主面がマット面から成る粗化面であり、他主面が粗化されたシャイニー面から成る粗化面であるので、内部導体層と絶縁基板との間の接着強度を高めて剥離を抑えることができる。   According to this configuration, the crystal grain size of the surface conductor layer, which is a conductor layer embedded in the surface of the insulating substrate, is smaller than the crystal grain size of the internal conductor layer, which is a conductor layer embedded in the insulating substrate. In general, the surface conductor layer that requires fine wiring has small mat surface irregularities. As a result, the surface conductor layer can be accurately formed with a fine pattern. In addition, since the main surface on the side where the surface conductor layer is embedded is a rough surface formed of a mat surface or a roughened mat surface, the adhesion strength between the surface conductor layer and the insulating substrate is increased to suppress peeling. be able to. Furthermore, since the main surface on the exposed side of the surface conductor layer is a non-roughened surface consisting of a shiny surface or a roughened surface consisting of a roughened shiny surface, the unevenness is small, and the surface conductor layer and the semiconductor element or external electric The circuit board can be satisfactorily connected. Further, the inner conductor layer is a roughened surface in which one main surface is a matte surface and the other main surface is a roughened shiny surface, so that it is between the inner conductor layer and the insulating substrate. It is possible to suppress peeling by increasing the adhesive strength.

本発明のうち第２の態様に係るものは、第１の態様に係る配線基板であって、前記表面導体層の埋設された側の前記主面の表面粗さが、前記内部導体層の前記他主面の表面粗さに略同一であることを特徴とするものである。   According to a second aspect of the present invention, there is provided a wiring board according to the first aspect, wherein the surface roughness of the main surface on the side where the surface conductor layer is embedded is the surface of the inner conductor layer. It is characterized by substantially the same surface roughness as the other main surface.

この構成によれば、表面導体層の埋設された側の主面の表面粗さが、内部導体層のエッチング処理により粗化されたシャイニー面の表面粗さと略同一であるので、絶縁基板に対する表面導体層の接着強度と内部導体層の接着強度とを同等程度とすることができる。すなわち、表面導体層の接着強度を内部導体層の接着強度と同等程度に実現しつつ、表面導体層を微細パターン化することが可能となる。   According to this configuration, since the surface roughness of the main surface on the side where the surface conductor layer is embedded is substantially the same as the surface roughness of the shiny surface roughened by the etching process of the inner conductor layer, The adhesive strength of the conductor layer and the adhesive strength of the internal conductor layer can be made comparable. That is, the surface conductor layer can be made into a fine pattern while realizing the adhesive strength of the surface conductor layer to the same level as the adhesive strength of the internal conductor layer.

本発明のうち第３の態様に係るものは、第１又は第２の態様に係る配線基板であって、前記表面導体層は、その埋設された側面が粗化面であることを特徴とするものである。   According to a third aspect of the present invention, there is provided the wiring substrate according to the first or second aspect, wherein the surface conductor layer has a roughened surface embedded therein. Is.

この構成によれば、表面導体層の絶縁基板に埋設された側面が粗化面であるので、表面導体層と絶縁基板との間の接着強度が更に高められる。   According to this configuration, since the side surface embedded in the insulating substrate of the surface conductor layer is a roughened surface, the adhesive strength between the surface conductor layer and the insulating substrate is further increased.

本発明のうち第４の態様に係るものは、第３の態様に係る配線基板であって、前記表面導体層の前記側面の十点平均粗さ（Ｒｚ）が1.5〜3.5μｍであることを特徴とするものである。   According to a fourth aspect of the present invention, there is provided the wiring board according to the third aspect, wherein a ten-point average roughness (Rz) of the side surface of the surface conductor layer is 1.5 to 3.5 μm. It is a feature.

この構成によれば、表面導体層の側面の十点平均粗さ（Ｒｚ）が1.5〜3.5μｍであるので、表面導体層と絶縁基板との接合強度を保ちつつ、表面導体層をより微細なパターンとして形成することができる。   According to this configuration, since the 10-point average roughness (Rz) of the side surface of the surface conductor layer is 1.5 to 3.5 μm, the surface conductor layer is made finer while maintaining the bonding strength between the surface conductor layer and the insulating substrate. It can be formed as a pattern.

本発明のうち第５の態様に係るものは、第１ないし第４の何れかの態様に係る配線基板であって、前記内部導体層は、その埋設された側面が粗化面であることを特徴とするものである。   According to a fifth aspect of the present invention, there is provided the wiring board according to any one of the first to fourth aspects, wherein the inner conductor layer has a roughened surface embedded therein. It is a feature.

この構成によれば、内部導体層の絶縁基板に埋設された側面が粗化面であるので、内部導体層と絶縁基板との間の接着強度が更に高められる。   According to this configuration, since the side surface embedded in the insulating substrate of the inner conductor layer is a roughened surface, the adhesive strength between the inner conductor layer and the insulating substrate is further increased.

本発明のうち第６の態様に係るものは、第１ないし第５の何れかの態様に係る配線基板であって、前記表面導体層の結晶粒径が0.2〜1.0μｍであり、前記内部導体層の結晶粒径が0.6〜1.8μｍであることを特徴とするものである。   According to a sixth aspect of the present invention, there is provided the wiring board according to any one of the first to fifth aspects, wherein the surface conductor layer has a crystal grain size of 0.2 to 1.0 μm, and the internal conductor The crystal grain size of the layer is 0.6 to 1.8 μm.

この構成によれば、表面導体層の結晶粒径が0.2〜1.0μｍであり内部導体層の結晶粒径が0.6〜1.8μｍであるので、表面導体層をより一層微細なパターンとして形成することができるとともに表面導体層と絶縁層との間に十分な接着強度が得られる。   According to this configuration, since the crystal grain size of the surface conductor layer is 0.2 to 1.0 μm and the crystal grain size of the internal conductor layer is 0.6 to 1.8 μm, the surface conductor layer can be formed as a finer pattern. In addition, sufficient adhesive strength can be obtained between the surface conductor layer and the insulating layer.

本発明のうち第７の態様に係るものは、第１ないし第６の何れかの態様に係る配線基板であって、前記表面導体層は、その埋設された側の前記主面の十点平均粗さ（Ｒｚ）が2.0〜4.0μｍであることを特徴とするものである。   According to a seventh aspect of the present invention, there is provided the wiring board according to any one of the first to sixth aspects, wherein the surface conductor layer has a ten-point average of the main surface on the side where the surface conductor layer is embedded. The roughness (Rz) is 2.0 to 4.0 μm.

この構成によれば、表面導体層の埋設された側の主面の十点平均粗さ（Ｒｚ）が2.0〜4.0μｍであるので、表面導体層と絶縁基板とが更に強固に接合される。   According to this configuration, since the ten-point average roughness (Rz) of the main surface on the side where the surface conductor layer is embedded is 2.0 to 4.0 μm, the surface conductor layer and the insulating substrate are more firmly bonded.

本発明のうち第８の態様に係るものは、第１ないし第７の何れかの態様に係る配線基板であって、前記表面導体層の露出する側の前記主面の十点平均粗さ（Ｒｚ）が1.0〜3.0μｍであることを特徴とするものである。   According to an eighth aspect of the present invention, there is provided the wiring board according to any one of the first to seventh aspects, wherein the ten-point average roughness of the main surface on the exposed side of the surface conductor layer ( Rz) is 1.0 to 3.0 μm.

この構成によれば、表面導体層の露出する側の主面の十点平均粗さ（Ｒｚ）が1.0〜3.0μｍであるので、表面導体層と半導体素子や外部電気回路との接続が更に良好に実現する。   According to this configuration, since the ten-point average roughness (Rz) of the main surface on the exposed side of the surface conductor layer is 1.0 to 3.0 μm, the connection between the surface conductor layer and the semiconductor element or the external electric circuit is further improved. Realize.

本発明のうち第９の態様に係るものは、第１ないし第８の何れかの態様に係る配線基板であって、前記内部導体層の前記一主面の十点平均粗さ（Ｒｚ）が1.0〜5.0μｍであることを特徴とするものである。   According to a ninth aspect of the present invention, there is provided the wiring board according to any one of the first to eighth aspects, wherein a ten-point average roughness (Rz) of the one main surface of the inner conductor layer is set. It is characterized by being 1.0 to 5.0 μm.

この構成によれば、内部導体層の一主面の十点平均粗さ（Ｒｚ）が1.0〜5.0μｍであるので、内部導体層と絶縁基板との接着強度が更に向上する。   According to this configuration, since the ten-point average roughness (Rz) of one main surface of the inner conductor layer is 1.0 to 5.0 μm, the adhesive strength between the inner conductor layer and the insulating substrate is further improved.

本発明のうち第１０の態様に係るものは、複数層の導体層を有する多層構造の配線基板を製造する方法であって、第１金属箔をめっきにより形成する第１工程と、前記第１金属箔のマット面が接着面となるように前記第１金属箔を第１フィルムに接着させる第２工程と、前記第１金属箔をパターニングすることにより第１導体層を形成する第３工程と、前記第２工程と前記第３工程との間、又は前記第３工程の後に、前記第１金属箔のシャイニー面を溶液処理により粗化する第４工程と、前記第３工程及び前記第４工程の後に、前記第１フィルムを未硬化ないし半硬化の第１絶縁層に圧力を加えつつ積層することにより前記第１導体層を前記第１絶縁層の表面に埋設する第５工程と、前記第５工程の後に、前記第１フィルムを剥離することにより前記第１導体層を前記第１絶縁層の表面に転写する第６工程と、前記第１金属箔よりも結晶粒径が小さくなるように第２金属箔をめっきにより形成する第７工程と、前記第２金属箔のシャイニー面が接着面となるように前記第２金属箔を第２フィルムに接着させる第８工程と、前記第２金属箔をパターニングすることにより第２導体層を形成する第９工程と、前記第９工程の後に、前記第２フィルムを未硬化ないし半硬化の第２絶縁層に圧力を加えつつ積層することにより前記第２導体層を前記第２絶縁層の表面に埋設する第１０工程と、前記第１０工程の後に、前記第２フィルムを剥離することにより前記第２導体層を前記第２絶縁層の表面に転写する第１１工程と、前記第６工程及び前記第１１工程の後に、前記第１導体層が内部に位置し前記第２導体層が表面に位置するように、前記第１絶縁層と前記第２絶縁層とを積層して硬化させる第１２工程と、を備えるものである。   According to a tenth aspect of the present invention, there is provided a method of manufacturing a multilayered wiring board having a plurality of conductive layers, the first step of forming a first metal foil by plating, and the first step A second step of bonding the first metal foil to the first film so that the matte surface of the metal foil becomes an adhesive surface; and a third step of forming the first conductor layer by patterning the first metal foil; The fourth step of roughening the shiny surface of the first metal foil by solution treatment between the second step and the third step or after the third step, the third step and the fourth step After the step, a fifth step of burying the first conductor layer on the surface of the first insulating layer by laminating the first film while applying pressure to the uncured or semi-cured first insulating layer; and To peel off the first film after the fifth step. A sixth step of transferring the first conductor layer to the surface of the first insulating layer; and a seventh step of forming a second metal foil by plating so that the crystal grain size is smaller than that of the first metal foil; And an eighth step of bonding the second metal foil to the second film so that the shiny surface of the second metal foil becomes an adhesive surface, and patterning the second metal foil to form a second conductor layer. After the ninth step and the ninth step, the second conductive layer is laminated on the surface of the second insulating layer by laminating the second film while applying pressure to the uncured or semi-cured second insulating layer. A tenth step of burying, an eleventh step of transferring the second conductor layer to the surface of the second insulating layer by peeling the second film after the tenth step, the sixth step, and the After the eleventh step, the first conductor layer is inside As location and the second conductor layer is located on the surface, and the twelfth step of curing by laminating a second insulating layer and the first insulating layer, those comprising a.

この構成によれば、積層された第１絶縁層と第２絶縁層とが硬化されて成る絶縁基板の表面に埋設された表面導体層である第２導体層の結晶粒径が、絶縁基板の内部に埋設された内部導体層である第１導体層の結晶粒径よりも小さくなる。このため、一般に微細配線が要求される表面導体層において、マット面の凹凸が小さいものとなる。それにより、表面導体層を微細なパターンで精度良く形成することが可能となる。また、表面導体層の埋設された側の主面がマット面となるので、表面導体層と絶縁基板との間の接着強度を高めて剥離を抑えることができる。更に、表面導体層の露出する側の主面がシャイニー面となるので、表面導体層と半導体素子や外部電気回路基板とを良好に接続することができる。また、内部導体層は、一主面がマット面であり、他主面が溶液処理により粗化されたシャイニー面となるので、双方の主面が粗化された状態で絶縁基板に接触する。それにより、内部導体層と絶縁基板との間の接着強度を高めて剥離を抑えることができる。   According to this configuration, the crystal grain size of the second conductor layer, which is a surface conductor layer embedded in the surface of the insulating substrate formed by curing the laminated first insulating layer and second insulating layer, is equal to that of the insulating substrate. This is smaller than the crystal grain size of the first conductor layer, which is an internal conductor layer embedded inside. For this reason, in the surface conductor layer in which fine wiring is generally required, the unevenness of the mat surface is small. This makes it possible to form the surface conductor layer with a fine pattern with high accuracy. In addition, since the main surface on the side where the surface conductor layer is embedded becomes the mat surface, it is possible to increase the adhesive strength between the surface conductor layer and the insulating substrate and suppress peeling. Furthermore, since the main surface on the exposed side of the surface conductor layer is a shiny surface, the surface conductor layer and the semiconductor element or the external electric circuit board can be connected well. The inner conductor layer has a matte surface on one main surface and a shiny surface roughened by solution treatment on the other main surface, so that both main surfaces are in contact with the insulating substrate in a roughened state. Thereby, it is possible to increase the adhesive strength between the internal conductor layer and the insulating substrate and suppress peeling.

本発明のうち第１１の態様に係るものは、第１０の態様に係る配線基板の製造方法であって、Ｎを１以上の整数として、前記第１工程ないし第６工程を、Ｎ回反復する反復工程を更に備え、前記第１２工程は、Ｎ＋１回の前記第６工程及び前記第１１工程の後に、全ての前記第１導体層が内部に位置し前記第２導体層が表面に位置するように、Ｎ＋１枚の前記第１絶縁層と前記第２絶縁層とを積層して硬化させるものである。   According to an eleventh aspect of the present invention, there is provided a method for manufacturing a wiring board according to the tenth aspect, wherein the first to sixth steps are repeated N times, where N is an integer of 1 or more. The twelfth step may further include an iterative process, and after the sixth and eleventh steps of N + 1 times, all the first conductor layers are located inside and the second conductor layers are located on the surface. In addition, N + 1 sheets of the first insulating layer and the second insulating layer are stacked and cured.

この構成によれば、第１工程ないし第６工程が更に１回以上反復して行われ、全ての第１導体層が内部に位置し第２導体層が表面に位置するように、全３枚以上の絶縁層が積層され且つ硬化される。このため、複数層の内部導体層を有し、且つ表面導体層の微細パターン化、表面導体層と半導体素子や外部電気回路との良好な接続、及び内部及び表面導体層と絶縁層との接着強度の向上を同時に達成する配線基板が得られる。   According to this configuration, the first step to the sixth step are further repeated one or more times, so that all the first conductor layers are located inside and the second conductor layers are located on the surface. The above insulating layers are laminated and cured. For this reason, it has a plurality of internal conductor layers, and the surface conductor layer is finely patterned, the surface conductor layer and the semiconductor element and the external electric circuit are well connected, and the internal and surface conductor layers are bonded to the insulating layer. A wiring board that simultaneously achieves improvement in strength can be obtained.

本発明のうち第１２の態様に係るものは、第１０ないし第１１の何れかの態様に係る配線基板の製造方法であって、前記第８工程と前記第９工程との間、又は前記第９工程の後に、前記第２金属箔のマット面を溶液処理により更に粗化する第１３工程を更に備えるものである。   According to a twelfth aspect of the present invention, there is provided a method of manufacturing a wiring board according to any one of the tenth to eleventh aspects, wherein the method is between the eighth step and the ninth step, or After the ninth step, a thirteenth step of further roughening the mat surface of the second metal foil by solution treatment is further provided.

この構成によれば、第２金属箔のマット面が溶液処理により更に粗化されるので、表面導体層である第２導体層と絶縁基板との間の接着強度が更に高められる。特に、第１３工程が第９工程の後に行われる場合には、第２金属箔のパターニングによって得られた第２導体層の側面が同時に粗化されるので、第２導体層と絶縁基板との間の接着強度が更に高められる。   According to this configuration, since the mat surface of the second metal foil is further roughened by the solution treatment, the adhesive strength between the second conductor layer, which is the surface conductor layer, and the insulating substrate is further increased. In particular, when the thirteenth step is performed after the ninth step, the side surfaces of the second conductor layer obtained by patterning the second metal foil are simultaneously roughened, so that the second conductor layer and the insulating substrate The adhesive strength between them is further increased.

以上のように本発明によれば、一般的に微細配線が要求される表層の導体層を微細なパターンで精度よく形成することが可能となるとともに、導体層と絶縁基板との間の接着強度が向上し剥離が抑えられ、且つ半導体素子や外部電気回路基板との良好な電気的接続が実現する。   As described above, according to the present invention, it is possible to accurately form a surface conductor layer, which generally requires fine wiring, with a fine pattern, and adhesion strength between the conductor layer and the insulating substrate. Is improved, peeling is suppressed, and good electrical connection with a semiconductor element and an external electric circuit board is realized.

（１．配線基板の構成）
図１は、本発明の一実施の形態による配線基板の構成を示す断面図である。また、図２は、図１の配線基板の一部拡大断面図である。この配線基板１００は、積層された複数の絶縁層１が一体化されてなる絶縁基板２、各絶縁層１の表面に埋設されることにより複数層にわたる導体層３、及び、各絶縁層１を貫通することにより異なる層に位置する導体層３どうしを電気的に接続する貫通導体４を、主要な要素として備えている。また、配線基板１００は、導体層３の一部を露出させるように絶縁基板２の上下の二主面に被着されたソルダーレジスト層５を更に備えている。なお、この実施の形態による配線基板１００では、ソルダーレジスト層５を備えている例を示しているが、本発明の配線基板は必ずしもソルダーレジスト層５を備えていることを要しない。 (1. Configuration of wiring board)
FIG. 1 is a cross-sectional view showing a configuration of a wiring board according to an embodiment of the present invention. FIG. 2 is a partially enlarged cross-sectional view of the wiring board of FIG. The wiring substrate 100 includes an insulating substrate 2 in which a plurality of laminated insulating layers 1 are integrated, a conductor layer 3 extending over a plurality of layers by being embedded in the surface of each insulating layer 1, and each insulating layer 1. A penetrating conductor 4 that electrically connects the conductor layers 3 located in different layers by penetrating is provided as a main element. In addition, the wiring substrate 100 further includes a solder resist layer 5 attached to the upper and lower main surfaces of the insulating substrate 2 so as to expose a part of the conductor layer 3. In addition, although the example provided with the soldering resist layer 5 is shown in the wiring board 100 by this embodiment, the wiring board of this invention does not necessarily need to be provided with the soldering resist layer 5.

絶縁基板２を構成する各絶縁層１は、耐熱繊維基材に熱硬化性樹脂を含浸させて成り、それぞれが導体層３を支持するとともに上下に位置する導体層３間の絶縁を保持する機能を有する。絶縁基板２は、例えばガラス繊維束を縦横に編み込んだ耐熱繊維基材に未硬化の熱硬化性樹脂組成物を含浸させ、通常においては更に半硬化状態とされて成り、厚みが50〜150μｍ程度の絶縁層１の素材としての絶縁シート（プリプレグ(Prepreg)と称される）を積層し、一括して熱硬化させることにより形成されている。すなわち、絶縁基板２は、一体化された絶縁層１の積層体として形成されている。   Each insulating layer 1 constituting the insulating substrate 2 is formed by impregnating a heat-resistant fiber base material with a thermosetting resin, and each of them supports the conductor layer 3 and maintains insulation between the conductor layers 3 positioned above and below. Have The insulating substrate 2 is formed, for example, by impregnating a heat-resistant fiber base material in which glass fiber bundles are knitted vertically and horizontally with an uncured thermosetting resin composition, and is usually further semi-cured and has a thickness of about 50 to 150 μm. An insulating sheet (referred to as a prepreg) as a material of the insulating layer 1 is laminated and thermally cured at once. That is, the insulating substrate 2 is formed as a laminated body of integrated insulating layers 1.

なお、絶縁層１の素材としての絶縁シートは、アラミド繊維やガラス繊維の不織布又は織布を、熱硬化性樹脂、架橋剤、エラストマー及び適当な溶剤を混合してなる液状の熱硬化性樹脂組成物に浸漬することによって、あるいはこの組成物をアラミド繊維やガラス繊維の不織布又は織布に塗布し含浸させることによって製作される。絶縁シートを構成する熱硬化性樹脂組成物に含有される熱硬化性樹脂としては、アリル変性ポリフェニレンエーテル樹脂やエポキシ樹脂、変性ポリオレフィン樹脂等が用いられ、後述する導体層３の転写及び埋入が行ないやすいように、その分子量は10000〜500000に調整されている。   The insulating sheet as the material of the insulating layer 1 is a liquid thermosetting resin composition obtained by mixing an aramid fiber or glass fiber non-woven fabric or woven fabric with a thermosetting resin, a crosslinking agent, an elastomer and an appropriate solvent. It is manufactured by dipping in an object, or by applying and impregnating the composition to a nonwoven fabric or woven fabric of aramid fiber or glass fiber. As the thermosetting resin contained in the thermosetting resin composition constituting the insulating sheet, allyl-modified polyphenylene ether resin, epoxy resin, modified polyolefin resin or the like is used, and transfer and embedding of the conductor layer 3 described later is performed. The molecular weight is adjusted to 10,000 to 500,000 for easy operation.

また、架橋剤としては、トリアリルイソシアヌレート等のトリアジン化合物が用いられ、その含有率は熱硬化性樹脂100質量部に対して、1〜10質量部であることが好ましい。架橋剤の含有率が熱硬化性樹脂100質量部に対して1質量部より少ないと架橋密度が低下し吸湿し易くなる傾向があり、10質量部より多いと絶縁層１が脆くなる傾向にある。従って、架橋剤の含有率は熱硬化性樹脂100質量部に対して1〜10質量部であることが好ましい。   As the crosslinking agent, a triazine compound such as triallyl isocyanurate is used, and the content thereof is preferably 1 to 10 parts by mass with respect to 100 parts by mass of the thermosetting resin. When the content of the cross-linking agent is less than 1 part by mass with respect to 100 parts by mass of the thermosetting resin, the cross-linking density tends to decrease and moisture absorption tends to occur. When the content exceeds 10 parts by mass, the insulating layer 1 tends to become brittle. . Therefore, it is preferable that the content rate of a crosslinking agent is 1-10 mass parts with respect to 100 mass parts of thermosetting resins.

更に、エラストマーとしては、スチレン−エチレン−ブチレン−スチレン（ＳＥＢＳ）やスチレン−エチレン−プロピレン−スチレン（ＳＥＰＳ）等の熱可塑性エラストマーが用いられ、その含有率は熱硬化性樹脂100質量部に対して、10〜40質量部が好ましい。エラストマーの含有率が熱硬化性樹脂100質量部に対して10質量部より少ないと絶縁層１が脆くなる傾向にあり、40質量部を超えると絶縁層１の剛性が低くなる傾向にある。従って、エラストマーの含有率は熱硬化性樹脂100質量部に対して10〜40質量部が好ましい。   Further, as the elastomer, a thermoplastic elastomer such as styrene-ethylene-butylene-styrene (SEBS) or styrene-ethylene-propylene-styrene (SEPS) is used, and its content is based on 100 parts by mass of the thermosetting resin. 10 to 40 parts by mass is preferable. When the elastomer content is less than 10 parts by mass with respect to 100 parts by mass of the thermosetting resin, the insulating layer 1 tends to become brittle, and when it exceeds 40 parts by mass, the rigidity of the insulating layer 1 tends to decrease. Therefore, the content of the elastomer is preferably 10 to 40 parts by mass with respect to 100 parts by mass of the thermosetting resin.

また、耐熱繊維基材は、アラミド繊維やガラス繊維等の繊維の不織布又は織布から成り、織布の場合その織り方は特に制限されず、一般に用いられる平織、綾織、朱子織等の織布が用いられる。このような耐熱繊維基材の含有率は、熱硬化性樹脂100質量部に対して50〜130質量部が好ましい。耐熱性繊維基材の含有率が熱硬化性樹脂100質量部に対して50質量部より少ないと、絶縁層１の積層・硬化時に熱硬化性樹脂が流動し、絶縁層１表面の導体層３が歪んでしまい易くなる傾向があり、130質量部より多いと耐熱性繊維基材に熱硬化性樹脂を良好に含浸できなくなる傾向にある。従って、耐熱性繊維基材の含有率は、熱硬化性樹脂100質量部に対して、50〜130質量部が好ましい。   Further, the heat-resistant fiber base material is composed of a nonwoven fabric or a woven fabric of fibers such as aramid fibers and glass fibers. In the case of a woven fabric, the weaving method is not particularly limited, and a commonly used woven fabric such as plain weave, twill weave, satin weave, etc. Is used. As for the content rate of such a heat-resistant fiber base material, 50-130 mass parts is preferable with respect to 100 mass parts of thermosetting resins. If the content of the heat-resistant fiber base material is less than 50 parts by mass with respect to 100 parts by mass of the thermosetting resin, the thermosetting resin flows when the insulating layer 1 is laminated and cured, and the conductor layer 3 on the surface of the insulating layer 1 Tends to be distorted, and if it exceeds 130 parts by mass, the heat-resistant fiber base material tends to be unable to be satisfactorily impregnated with the thermosetting resin. Therefore, the content of the heat resistant fiber base material is preferably 50 to 130 parts by mass with respect to 100 parts by mass of the thermosetting resin.

また、絶縁基板２の表面及び各絶縁層１の間に埋設された導体層３は、厚みが5〜50μｍ程度の銅やアルミニウム、銀等の金属箔から成り、配線基板に搭載される半導体素子の各電極を外部電気回路基板の配線導体に電気的に接続する導電路の一部として機能する。これらの導体層３は、幅が20〜200μｍ程度の信号用導体や広面積の接地又は電源用導体を含んでおり、一般的には絶縁基板２の表面において微細な高密度配線が施されている。   Further, the conductor layer 3 embedded between the surface of the insulating substrate 2 and each insulating layer 1 is made of a metal foil such as copper, aluminum or silver having a thickness of about 5 to 50 μm, and is mounted on the wiring substrate. Each of these electrodes functions as a part of a conductive path that electrically connects to the wiring conductor of the external electric circuit board. These conductor layers 3 include a signal conductor having a width of about 20 to 200 μm and a large-area ground or power supply conductor. Generally, fine high-density wiring is applied on the surface of the insulating substrate 2. Yes.

絶縁基板２の上主面（図中上方に向いた一方主面を上主面、下方に向いた他方主面を下主面と仮称する）に埋設された導体層３のうち、ソルダーレジスト層５に覆われることなく露出する部分は半導体素子接続パッド３ａとして機能し、絶縁基板２の下主面に埋設された導体層３のうち露出する部分は外部接続パッド３ｂとして機能する。半導体素子接続パッド３ａは、半田バンプ７ａを通じて、例えばベアチップの形態を有する半導体素子６に接続される。他方の外部接続パッド３ｂは、半田バンプ７ｂを通じて不図示のマザーボード等の電気回路基板に接続される。   Of the conductive layer 3 embedded in the upper main surface of the insulating substrate 2 (the one main surface facing upward in the drawing is referred to as the upper main surface and the other main surface facing downward is referred to as the lower main surface), the solder resist layer The portion exposed without being covered by 5 functions as the semiconductor element connection pad 3a, and the exposed portion of the conductor layer 3 embedded in the lower main surface of the insulating substrate 2 functions as the external connection pad 3b. The semiconductor element connection pad 3a is connected to the semiconductor element 6 having, for example, a bare chip shape through the solder bumps 7a. The other external connection pad 3b is connected to an electric circuit board such as a mother board (not shown) through solder bumps 7b.

なお、このような導体層３は、転写フィルム上に接着剤を介して剥離可能に貼着した金属箔を所定パターンにエッチングすることにより形成した導体層３を、絶縁層１用の絶縁シートの表面に熱プレスを用いて熱圧着して埋入させておくことにより、絶縁基板２の表面すなわち上下両主面、及び絶縁基板２の内部である絶縁層１の間に埋設される。また、このような導体層３は、絶縁層１との接着強度を高めるために、絶縁層１用の絶縁シートに埋設される側の主面や側面を転写フィルム上で溶液処理することにより粗化しておくことが望ましい。   In addition, such a conductor layer 3 is a conductor layer 3 formed by etching a metal foil that is detachably attached to a transfer film via an adhesive into a predetermined pattern. By embedding the surface by thermocompression bonding using a hot press, the surface is embedded between the surface of the insulating substrate 2, that is, the upper and lower main surfaces and the insulating layer 1 inside the insulating substrate 2. Further, in order to increase the adhesive strength with the insulating layer 1, such a conductor layer 3 is roughened by subjecting the main surface and side surface embedded in the insulating sheet for the insulating layer 1 to solution treatment on a transfer film. It is desirable to make it.

配線基板１００では、導体層３のうち、絶縁基板２の表面に埋設された導体層である表面導体層３Ａの結晶粒径が、絶縁層１の間に埋設された導体層である内部導体層３Ｂの結晶粒径よりも小さく設定されている。このように、表面導体層３Ａの結晶粒径が内部導体層３Ｂの結晶粒径より小さいことから、一般に微細配線が要求される表面導体層３Ａにおいて、粗化面の凹凸が小さいものとなり、その結果、表面導体層３Ａのパターンに大きな形状の崩れや断線が発生することが回避されるとともに、内部導体層３Ｂにおいては十分に大きな粗化面が形成され、絶縁層１との強固な密着が実現する。   In the wiring substrate 100, the inner conductor layer which is a conductor layer embedded in between the insulating layers 1 has a crystal grain size of the surface conductor layer 3 </ b> A which is a conductor layer embedded in the surface of the insulating substrate 2 in the conductor layer 3. It is set smaller than the crystal grain size of 3B. As described above, since the crystal grain size of the surface conductor layer 3A is smaller than the crystal grain size of the internal conductor layer 3B, in the surface conductor layer 3A in which fine wiring is generally required, the roughness of the roughened surface is small. As a result, it is avoided that a large shape collapse or disconnection occurs in the pattern of the surface conductor layer 3A, and a sufficiently large roughened surface is formed in the internal conductor layer 3B. Realize.

なお、絶縁基板２の表面に埋設された表面導体層３Ａは、その結晶粒径が0.2μｍ未満であると、その埋設された側の主面に絶縁層１との間の強固な接合に必要な凹凸を十分に形成することが困難となる傾向にあり、他方、1.0μｍを超えると、表面導体層３Ａをエッチングして微細なパターンを形成する際にそのパターンを精度良く形成することが困難となる傾向にある。従って、表面導体層３Ａの結晶粒径は、0.2〜1.0μｍの範囲が好ましい。   The surface conductor layer 3A embedded in the surface of the insulating substrate 2 is necessary for strong bonding between the main surface on the embedded side and the insulating layer 1 when the crystal grain size is less than 0.2 μm. However, when the thickness exceeds 1.0 μm, it is difficult to accurately form the pattern when the surface conductor layer 3A is etched to form a fine pattern. It tends to be. Therefore, the crystal grain size of the surface conductor layer 3A is preferably in the range of 0.2 to 1.0 μm.

更に、表面導体層３Ａは、その埋設された側の主面がマット面又は粗化されたマット面から成る粗化面であるとともに、露出する主面はシャイニー面から成る非粗化面又は粗化されたシャイニー面から成る粗化面であり、且つ内部導体層３Ｂは、その一方の主面がマット面から成る粗化面であり、他方の主面が粗化されたシャイニー面から成る粗化面とされていることが好ましい。表面導体層３Ａは、その埋設された側の主面がマット面又は粗化されたマット面から成る粗化面であると、粗化面の微小な凹凸と絶縁層１中の樹脂とが機械的に噛み合うことにより絶縁層１に強固に密着する。また、露出する他方の主面はシャイニー面から成る非粗化面又は粗化されたシャイニー面から成る粗化面となっていると、表面導体層３Ａと半導体素子や外部電気回路基板とを良好に接続することができる。更に、内部導体層３Ｂは、その一方の主面がマット面から成る粗化面であり、他方の主面が粗化されたシャイニー面から成る粗化面であると、双方の主面に形成された粗化面の微小な凹凸と絶縁層１中の樹脂とが機械的に噛み合うことにより絶縁層１に強固に密着する。従って、半導体素子６を実装する際の熱や半導体素子６が動作時に発生する熱が加えられた場合においても、導体層３と絶縁層１との間の剥離が抑えられ、半導体素子６や外部電気回路基板との電気的な接続に関して信頼性に優れる配線基板として、配線基板１００を提供することができる。   Further, the surface conductor layer 3A is a roughened surface whose main surface on the embedded side is a mat surface or a roughened mat surface, and the exposed main surface is a non-roughened surface or rough surface formed of a shiny surface. The inner conductor layer 3B is a roughened surface composed of a roughened shiny surface, and one of the main surfaces is a roughened surface formed of a matte surface, and the other main surface is a roughened surface formed of a roughened shiny surface. It is preferable that the surface is a chemical surface. In the surface conductor layer 3A, if the embedded main surface is a roughened surface formed of a matte surface or a roughened matte surface, the minute unevenness of the roughened surface and the resin in the insulating layer 1 are machined. By being meshed with each other, the insulating layer 1 is firmly adhered. Further, when the other main surface to be exposed is a non-roughened surface made of a shiny surface or a roughened surface made of a roughened shiny surface, the surface conductor layer 3A and the semiconductor element or external electric circuit board are excellent. Can be connected to. Further, the inner conductor layer 3B is formed on both main surfaces when one main surface is a roughened surface made of a matte surface and the other main surface is a roughened surface made of a rough shiny surface. The fine irregularities of the roughened surface and the resin in the insulating layer 1 are mechanically engaged with each other, so that the roughened surface firmly adheres to the insulating layer 1. Therefore, even when heat is applied when the semiconductor element 6 is mounted or heat generated when the semiconductor element 6 is in operation, peeling between the conductor layer 3 and the insulating layer 1 is suppressed, and the semiconductor element 6 and the external The wiring board 100 can be provided as a wiring board having excellent reliability with respect to electrical connection with the electric circuit board.

なお、表面導体層３Ａは、その埋設された側の主面の十点平均粗さ（Ｒｚ）が2.0μｍ未満であると、絶縁層１との密着力、すなわち接着強度が弱いものとなり、表面導体層３Ａに半導体素子６や外部電気回路基板を接続する際等に応力が加えられると、絶縁基板２から剥離してしまう危険性が大きくなる。他方、上記十点平均粗さ（Ｒｚ）が4.0μｍを超えると、表面導体層３Ａをエッチングして微細なパターンを形成する際に、そのパターンを精度良く形成することが困難となったり、表面導体層３Ａの埋設される側の主面を粗化する際に微細なパターンに断線が発生したりする可能性がある。従って、表面導体層３Ａの埋設された側の主面の十点平均粗さ（Ｒｚ）は、2.0〜4.0μｍの範囲であることが好ましい。   The surface conductor layer 3A has a low adhesion strength to the insulating layer 1, that is, an adhesive strength, when the ten-point average roughness (Rz) of the main surface on the embedded side is less than 2.0 μm. If stress is applied when the semiconductor element 6 or an external electric circuit board is connected to the conductor layer 3A, the risk of peeling from the insulating board 2 increases. On the other hand, when the ten-point average roughness (Rz) exceeds 4.0 μm, it becomes difficult to form the pattern with high accuracy when the surface conductor layer 3A is etched to form a fine pattern, When the main surface on the side where the conductor layer 3A is embedded is roughened, there is a possibility that the fine pattern may be disconnected. Accordingly, the ten-point average roughness (Rz) of the main surface on the side where the surface conductor layer 3A is embedded is preferably in the range of 2.0 to 4.0 μm.

更に、表面導体層３Ａは、その埋設された側面が粗化面であると、粗化された側面の微小な凹凸と絶縁層１中の樹脂とが機械的に噛み合うことにより絶縁層１との接合力、言い換えると接着強度をより高いものとすることができる。従って、表面導体層３Ａの側面は粗化されていることが好ましい。表面導体層３Ａは、その側面が粗化面となっている場合、側面の十点平均粗さ（Ｒｚ）が1.5μｍ未満であると、側面と絶縁層１との接合力、すなわち接着強度を向上させることが困難であり、3.5μｍを越えると、粗化する際に微細なパターンに断線が発生する危険性がある。従って、表面導体層３Ａは、その側面が粗化面となっている場合、側面の十点平均粗さ（Ｒｚ）を1.5〜3.5μｍの範囲としておくことが好ましい。   Further, when the buried side surface of the surface conductor layer 3A is a roughened surface, the minute unevenness on the roughened side surface mechanically meshes with the resin in the insulating layer 1 so that the surface conductor layer 3A is in contact with the insulating layer 1. The bonding strength, in other words, the adhesive strength can be made higher. Therefore, the side surface of the surface conductor layer 3A is preferably roughened. When the side surface of the surface conductor layer 3A is a roughened surface, when the ten-point average roughness (Rz) of the side surface is less than 1.5 μm, the bonding strength between the side surface and the insulating layer 1, that is, the adhesive strength is increased. It is difficult to improve, and if it exceeds 3.5 μm, there is a risk of disconnection in a fine pattern when roughening. Accordingly, when the side surface of the surface conductor layer 3A is a roughened surface, it is preferable that the ten-point average roughness (Rz) of the side surface be in the range of 1.5 to 3.5 μm.

また、表面導体層３Ａは、その露出する側の主面の十点平均粗さ（Ｒｚ）が1.0μｍ未満であると、表面導体層３Ａの露出する側の主面とソルダーレジスト層５との接合力を向上させることが困難となる。また、上記十点平均粗さ（Ｒｚ）が3.0μｍを超えると、表面導体層３Ａを選択的にエッチングすることにより微細パターンを形成する際に、転写フィルムと表面導体層３Ａとの間に隙間が発生し易く、微細なパターンを精度良く形成することができず、パターンの形状が崩れて電気抵抗が増大したり、断線が発生したりしてしまう。それにより、半導体素子６や外部電気回路基板との接続の信頼性が低下する傾向が現れることとなる。従って、表面導体層３Ａの露出する主面の十点平均粗さ（Ｒｚ）は、1.0〜3.0μｍの範囲であることが好ましい。   Further, in the surface conductor layer 3A, when the ten-point average roughness (Rz) of the main surface on the exposed side is less than 1.0 μm, the main surface on the exposed side of the surface conductor layer 3A and the solder resist layer 5 It becomes difficult to improve the bonding force. If the ten-point average roughness (Rz) exceeds 3.0 μm, a gap is formed between the transfer film and the surface conductor layer 3A when a fine pattern is formed by selectively etching the surface conductor layer 3A. Therefore, a fine pattern cannot be formed with high precision, and the shape of the pattern is lost, resulting in an increase in electrical resistance or a disconnection. Thereby, the tendency for the reliability of connection with the semiconductor element 6 or an external electric circuit board to fall will appear. Accordingly, the ten-point average roughness (Rz) of the exposed main surface of the surface conductor layer 3A is preferably in the range of 1.0 to 3.0 μm.

更に、絶縁層１の間に埋設された内部導体層３Ｂは、その双方の主面の十点平均粗さ（Ｒｚ）が1.0μｍ未満であると、絶縁層１との接合力すなわち接着強度が小さく、絶縁層１との間で剥離してしまう危険性が大きくなる。内部導体層３Ｂの双方の主面のうち、絶縁層１に埋設される側とは反対側の主面について、上記十点平均粗さ（Ｒｚ）が5.0μｍを超えると、導体層３を絶縁層１用の絶縁シートに埋入して転写する際に、転写フィルムと内部導体層３Ｂとを接着している接着剤が内部導体層３Ｂの上記主面に残留してしまい、残留した接着剤が内部導体層３Ｂと絶縁層１との強固な密着を阻害してしまう危険性がある。従って、内部導体層３Ｂの双方の主面のうち、絶縁層１に埋設される側とは反対側の主面については、その十点平均粗さ（Ｒｚ）は1.0〜5.0μｍの範囲であることが好ましい。   Furthermore, the inner conductor layer 3B embedded between the insulating layers 1 has a bonding strength with the insulating layer 1, that is, an adhesive strength, when the ten-point average roughness (Rz) of both main surfaces thereof is less than 1.0 μm. The risk of peeling off from the insulating layer 1 increases. If the ten-point average roughness (Rz) of the main surface opposite to the side embedded in the insulating layer 1 out of both main surfaces of the inner conductor layer 3B exceeds 5.0 μm, the conductor layer 3 is insulated. When embedded in the insulating sheet for layer 1 and transferred, the adhesive bonding the transfer film and the internal conductor layer 3B remains on the main surface of the internal conductor layer 3B, and the residual adhesive However, there is a risk of hindering the strong adhesion between the inner conductor layer 3B and the insulating layer 1. Therefore, the ten-point average roughness (Rz) of the main surface opposite to the side embedded in the insulating layer 1 among both main surfaces of the inner conductor layer 3B is in the range of 1.0 to 5.0 μm. It is preferable.

内部導体層３Ｂの側面も、粗化面として形成されていることが更に望ましい。それにより、内部導体層３Ｂと絶縁層１との間の接着強度が更に高められる。   It is further desirable that the side surface of the inner conductor layer 3B is also formed as a roughened surface. Thereby, the adhesive strength between the inner conductor layer 3B and the insulating layer 1 is further increased.

また、絶縁層１を貫通して設けられた貫通導体４は、各絶縁層１を挟んで上下に位置する導体層３同士を互いに電気的に接続する層間接続導体として機能する。貫通導体４は、その直径が好ましくは30〜200μｍであり、絶縁層１に設けられた貫通孔内に金属粉末とトリアジン系熱硬化性樹脂等とから成る導電性材料を埋め込み熱硬化することにより形成されている。貫通導体４は、その直径が30μｍ未満になると貫通導体４の形成が困難となる傾向があり、200μｍを超えると高密度配線が形成できなくなる傾向がある。従って、貫通導体４の直径は30〜200μｍであることが好ましい。   In addition, the through conductor 4 provided through the insulating layer 1 functions as an interlayer connection conductor that electrically connects the conductor layers 3 positioned above and below each other with the insulating layers 1 interposed therebetween. The diameter of the through conductor 4 is preferably 30 to 200 μm, and a conductive material made of a metal powder and a triazine-based thermosetting resin is embedded in the through hole provided in the insulating layer 1 and thermoset. Is formed. When the diameter of the through conductor 4 is less than 30 μm, the formation of the through conductor 4 tends to be difficult, and when it exceeds 200 μm, there is a tendency that high density wiring cannot be formed. Therefore, the diameter of the through conductor 4 is preferably 30 to 200 μm.

また、貫通導体４を形成する導電性材料の金属粉末の含有量は80〜95質量％が好ましい。金属粉末の含有量が80質量％より少ないと、トリアジン系熱硬化性樹脂により金属粉末同士の接続が妨げられ導通抵抗が上昇してしまう傾向があり、95質量％を超えると導電性材料の粘度が上がり過ぎて良好に埋め込みできない傾向がある。従って、導電性材料の金属粉末の含有量は、80〜95質量％であることが好ましい。   Further, the content of the metal powder of the conductive material forming the through conductor 4 is preferably 80 to 95% by mass. If the content of the metal powder is less than 80% by mass, the triazine-based thermosetting resin tends to hinder the connection between the metal powders and increase the conduction resistance. If the content exceeds 95% by mass, the viscosity of the conductive material Tends to be too high to embed well. Therefore, the content of the metal powder of the conductive material is preferably 80 to 95% by mass.

なお、貫通導体４用の導電性材料に含有される金属粉末は、錫と銀とビスマスと銅とを含有する合金から成り、錫を70〜90質量％含有することが好ましい。また、金属粉末の平均粒径は5〜10μｍであることが好ましい。平均粒径が5μｍより小さいと導電性材料の粘度が上がり過ぎて良好に埋め込みできない傾向があり、10μｍより大きいと金属粉末が高充填できず導通抵抗が高くなってしまう傾向がある。従って、貫通導体４用の導電性材料に含有される金属粉末の平均粒径は、5〜10μｍであることが好ましい。   The metal powder contained in the conductive material for the through conductor 4 is made of an alloy containing tin, silver, bismuth, and copper, and preferably contains 70 to 90% by mass of tin. Moreover, it is preferable that the average particle diameter of a metal powder is 5-10 micrometers. If the average particle size is smaller than 5 μm, the viscosity of the conductive material tends to increase too much to be embedded well, and if it is larger than 10 μm, the metal powder cannot be highly filled and the conduction resistance tends to increase. Therefore, the average particle diameter of the metal powder contained in the conductive material for the through conductor 4 is preferably 5 to 10 μm.

また、貫通導体４の熱硬化性樹脂は、トリアリルシアヌレートやトリアリルイソシアヌレート、トリスエポキシプロピルイソシアヌレート、トリス（２−ヒドロキシエチル）イソシアヌレート等のトリアジン系熱硬化性樹脂であることが好ましい。   The thermosetting resin of the through conductor 4 is preferably a triazine-based thermosetting resin such as triallyl cyanurate, triallyl isocyanurate, trisepoxypropyl isocyanurate, or tris (2-hydroxyethyl) isocyanurate. .

更に、絶縁基板２の上下両主面にはエポキシ樹脂等の熱硬化性樹脂から成るソルダーレジスト層５が、導体層３の半導体素子接続パッド３ａや外部接続パッド３ｂの中央部を露出させるようにして被着されている。ソルダーレジスト層５は、半導体素子接続パッド３ａ同士や外部接続パッド３ｂ同士が半田バンプ７ａや７ｂにより互いに電気的に短絡するのを防止するための短絡防止手段として機能し、感光性を有する未硬化の熱硬化性樹脂のシートを絶縁基板２の上下両主面に貼着するとともに露光及び現像した後、紫外線及び熱硬化させることによって形成される。   Furthermore, solder resist layers 5 made of a thermosetting resin such as epoxy resin are exposed on the upper and lower main surfaces of the insulating substrate 2 so that the central portions of the semiconductor element connection pads 3a and the external connection pads 3b of the conductor layer 3 are exposed. Is attached. The solder resist layer 5 functions as a short-circuit prevention means for preventing the semiconductor element connection pads 3a and the external connection pads 3b from being electrically short-circuited to each other by the solder bumps 7a and 7b, and is uncured having photosensitivity. A sheet of the thermosetting resin is attached to the upper and lower main surfaces of the insulating substrate 2 and is exposed and developed, followed by ultraviolet curing and thermosetting.

なお、配線基板１００がソルダーレジスト層５を有する場合、表面導体層３Ａの露出する側の主面とソルダーレジスト層５をとの接合力を高めるため、絶縁層１に埋設された表面導体層３Ａの露出する側の主面を溶液処理やブラスト研磨等により粗化し、その上にソルダーレジスト層５を形成するようにしてもよい。この場合、ソルダーレジスト層５を形成した後、ソルダーレジスト層５から露出する表面導体層３Ａの表面を選択的にソフトエッチングしてその十点平均粗さ（Ｒｚ）を1.0〜3.0μｍに調整することが好ましい。   When the wiring substrate 100 has the solder resist layer 5, the surface conductor layer 3 </ b> A embedded in the insulating layer 1 in order to increase the bonding force between the exposed main surface of the surface conductor layer 3 </ b> A and the solder resist layer 5. The main surface on the exposed side may be roughened by solution treatment, blast polishing or the like, and the solder resist layer 5 may be formed thereon. In this case, after the solder resist layer 5 is formed, the surface of the surface conductor layer 3A exposed from the solder resist layer 5 is selectively soft-etched to adjust the ten-point average roughness (Rz) to 1.0 to 3.0 μm. It is preferable.

かくして、本発明の一実施の形態による配線基板１００によれば、絶縁基板２の表面、すなわち両主面に埋設された表面導体層３Ａの結晶粒径が、絶縁層１の間に埋設された内部導体層３Ｂの結晶粒径よりも小さいことから、一般に微細配線が要求される表面導体層３Ａにおいて、粗化面の凹凸が小さいものとなり、その結果、表面導体層３Ａのパターンに大きな形状の崩れや断線が発生することが回避される。同時に、内部導体層３Ｂにおいては十分に大きな粗化面が形成されるので、内部導体層３Ｂが絶縁層１と強固に密着する。従って、表層に精度良く形成された微細なパターンの配線導体を有するとともに、半導体素子６を実装する際の熱や半導体素子６が作動時に発生する熱が加えられても、導体層３と絶縁層１との間の剥離が抑えられ、半導体素子６や外部電気回路基板との電気的な接続に対する信頼性に優れる高密度配線の配線基板として、配線基板１００を得ることができる。   Thus, according to the wiring substrate 100 according to the embodiment of the present invention, the crystal grain size of the surface conductor layer 3A embedded in the surface of the insulating substrate 2, that is, both main surfaces, is embedded between the insulating layers 1. Since it is smaller than the crystal grain size of the internal conductor layer 3B, in the surface conductor layer 3A that generally requires fine wiring, the roughness of the roughened surface is small. As a result, the pattern of the surface conductor layer 3A has a large shape. The occurrence of collapse and disconnection is avoided. At the same time, since a sufficiently large roughened surface is formed in the inner conductor layer 3B, the inner conductor layer 3B is firmly adhered to the insulating layer 1. Therefore, the conductor layer 3 and the insulating layer have a fine pattern of wiring conductors formed on the surface layer with high accuracy, and even when heat is generated when the semiconductor element 6 is mounted or heat generated when the semiconductor element 6 is activated. The wiring substrate 100 can be obtained as a wiring substrate of high-density wiring that is prevented from being peeled off from the substrate 1 and has excellent reliability for electrical connection with the semiconductor element 6 and an external electric circuit substrate.

通常において、絶縁基板２の両主面のうち、半導体素子６が接続される側の主面に埋設される表面導体層３Ａの方が、他方の主面に埋設される表面導体層３Ａに比べて、より微細なパターン形状であることを要する。従って、絶縁基板２の両主面に埋設された表面導体層３Ａのうち、一方主面に埋設されたもの、例えば半導体素子６が接続される側の主面に埋設されたものについてのみ、結晶粒径が内部導体層３Ｂの結晶粒径よりも小さく設定され、絶縁層１に埋設される側の主面が粗化面とされ、その反対主面が非粗化面とされてもよい。   Normally, the surface conductor layer 3A embedded in the main surface on the side to which the semiconductor element 6 is connected out of both main surfaces of the insulating substrate 2 is compared with the surface conductor layer 3A embedded in the other main surface. Therefore, it is necessary to have a finer pattern shape. Accordingly, only the surface conductor layer 3A embedded in both main surfaces of the insulating substrate 2 is embedded in one main surface, for example, the one embedded in the main surface on the side to which the semiconductor element 6 is connected. The grain size may be set smaller than the crystal grain size of the inner conductor layer 3B, the main surface on the side embedded in the insulating layer 1 may be a roughened surface, and the opposite main surface may be a non-roughened surface.

（２．製造方法）
図３及び図４は、配線基板１００を製造する好ましい方法を示す製造工程図である。以下に図３及び図４を参照しつつ、配線基板１００を製造するための好ましい方法について説明する。 (2. Manufacturing method)
3 and 4 are manufacturing process diagrams showing a preferred method for manufacturing the wiring board 100. FIG. Hereinafter, a preferred method for manufacturing the wiring substrate 100 will be described with reference to FIGS. 3 and 4.

配線基板１００を製造するには、まず、絶縁層１の間に埋設される内部導体層３Ｂの元になる金属箔（「第１金属箔」と仮称する）と、絶縁基板２の表面に埋設される表面導体層３Ａの元になる金属箔（「第２金属箔」と仮称する）とが準備される。これらの金属箔は、図３（ａ）に例示するように電解めっきにより形成される。以下、金属箔が銅箔である場合を例に挙げる。銅箔を形成する場合には、銅イオンを含有する電解液であるめっき液２０に浸漬した電着ドラム（カソード体）２１と鉛容器（アノード体）２２との間に、電流密度が数10〜数100Ａ／ｄｍ２の電流を通電して電着ドラム２１の表面に、厚さ10〜30μｍ程度の銅箔２３を析出させる。電着ドラム２１の表面に析出した銅箔２３は、電着ドラム２１から連続して剥離され、巻き取りロール２４に巻き取られる。 To manufacture the wiring substrate 100, first, a metal foil (tentatively referred to as “first metal foil”) serving as a base of the internal conductor layer 3 B embedded between the insulating layers 1 and the surface of the insulating substrate 2 are embedded. A metal foil (tentatively referred to as “second metal foil”) that is the basis of the surface conductor layer 3A to be prepared is prepared. These metal foils are formed by electrolytic plating as illustrated in FIG. Hereinafter, the case where metal foil is copper foil is mentioned as an example. In the case of forming a copper foil, a current density of several tens of thousands is present between an electrodeposition drum (cathode body) 21 and a lead container (anode body) 22 immersed in a plating solution 20 that is an electrolytic solution containing copper ions. A copper foil 23 having a thickness of about 10 to 30 μm is deposited on the surface of the electrodeposition drum 21 by applying a current of ˜100 A / dm 2 . The copper foil 23 deposited on the surface of the electrodeposition drum 21 is continuously peeled off from the electrodeposition drum 21 and taken up by a take-up roll 24.

このとき、表面導体層３Ａ用の銅箔であれば、その結晶粒径が0.2〜1.0μｍとなるように、内部導体層３Ｂ用の銅箔であれば、その結晶粒径が0.6〜1.8μｍとなるように析出させる。銅箔の結晶粒径を制御するには、電着ドラム２１の回転速度を調整すればよい。回転速度を高くすれば結晶粒径が0.2〜1.0μｍと小さくなり、回転速度を低くすれば結晶粒径が0.6〜1.8μｍと大きくなる。また、電着ドラム２１の表面に接着する側の銅箔２３の主面は、十点平均粗さ（Ｒｚ）が電着ドラム２１の表面に対応した1.0〜3.0μｍであるシャイニー面と呼ばれる平滑面となる。一方、銅箔２３の反対側の面、すなわち、めっき液２０に接触する側の主面は、銅の結晶が析出するに伴ってこぶ状、すなわち複数の結晶が塊になったノジュール(Nodule)状の微細な突起の集合体として成長することにより形成されるマット面と呼ばれる粗化面となる。なお、この粗化面の十点平均粗さ（Ｒｚ）は、表面導体層３Ａ用の銅箔であれば、1.5〜3.5μｍとなり、内部導体層３Ｂ用の銅箔であれば、1.0〜5.0μｍとなる。   At this time, if it is a copper foil for the surface conductor layer 3A, its crystal grain size is 0.6 to 1.8 μm if it is a copper foil for the internal conductor layer 3B so that its crystal grain size is 0.2 to 1.0 μm. It is made to precipitate so that it may become. In order to control the crystal grain size of the copper foil, the rotational speed of the electrodeposition drum 21 may be adjusted. When the rotation speed is increased, the crystal grain size is reduced to 0.2 to 1.0 μm, and when the rotation speed is decreased, the crystal grain size is increased to 0.6 to 1.8 μm. The main surface of the copper foil 23 on the side to be bonded to the surface of the electrodeposition drum 21 is a smooth surface called a shiny surface having a ten-point average roughness (Rz) of 1.0 to 3.0 μm corresponding to the surface of the electrodeposition drum 21. It becomes a surface. On the other hand, the opposite surface of the copper foil 23, that is, the main surface in contact with the plating solution 20, is bumpy as the copper crystals are deposited, that is, a nodule in which a plurality of crystals are agglomerated. It becomes a roughened surface called a mat surface formed by growing as an aggregate of fine projections in the shape of a ring. The ten-point average roughness (Rz) of the roughened surface is 1.5 to 3.5 μm for the copper foil for the surface conductor layer 3A, and 1.0 to 5.0 for the copper foil for the internal conductor layer 3B. μm.

次に、図３（ｂ）及び図３（ｃ）が示すように、厚みが20〜50μｍ程度のポリエチレンテレフタレート等の耐熱性樹脂から成る転写フィルム３０の片面に接着剤を介して上記の銅箔２３をそれぞれ貼着する。このとき、表面導体層３Ａ用の銅箔２３Ａは、その平滑面、すなわちシャイニー面が転写フィルムの主面に接触するように貼着され、内部導体層３Ｂ用の銅箔２３Ｂは、その粗化面、すなわちマット面が転写フィルムの主面に接触するように貼着される。図４（ａ）は、図３（ｂ）及び図３（ｃ）の何れかの工程によって得られた銅箔２３が貼着、すなわち接着された転写フィルム３０を示している。   Next, as shown in FIGS. 3 (b) and 3 (c), the copper foil is placed on one side of a transfer film 30 made of a heat-resistant resin such as polyethylene terephthalate having a thickness of about 20 to 50 μm via an adhesive. 23 is pasted. At this time, the copper foil 23A for the surface conductor layer 3A is stuck so that the smooth surface, that is, the shiny surface is in contact with the main surface of the transfer film, and the copper foil 23B for the inner conductor layer 3B is roughened. It sticks so that a surface, ie, a mat | matte surface, may contact the main surface of a transfer film. FIG. 4A shows the transfer film 30 to which the copper foil 23 obtained by any one of the steps of FIG. 3B and FIG.

次に、転写フィルム３０に貼着された銅箔２３の上に、レジストマスクとしての耐エッチング樹脂を被着し、この耐エッチング樹脂を選択的に露光及び現像することにより、図４（ｂ）に示すように、銅箔２３を導体層３の配線パターン状に被覆する耐エッチング樹脂層３１を形成する。その後、この工程で得られた構造体を、塩化第二鉄溶液中に浸漬することにより、銅箔２３の露出部をエッチング除去した後、耐エッチング樹脂層３１を剥離することにより、図４（ｃ）に示すように、転写フィルム３０上に導体層３を形成する。このとき、導体層３が表面導体層３Ａである場合には、導体層３はその結晶粒径が0.2〜1.0μｍと小さいため粗化面の十点平均粗さ（Ｒｚ）が1.5〜3.5μｍである。このため、粗化面と耐エッチング樹脂３１とが隙間なく密着するので、例えば幅が40μｍ以下の微細なパターンを精度よく形成することができる。   Next, an etching resistant resin as a resist mask is deposited on the copper foil 23 adhered to the transfer film 30, and the etching resistant resin is selectively exposed and developed, thereby obtaining the structure shown in FIG. As shown in FIG. 2, an etching resistant resin layer 31 that covers the copper foil 23 in the wiring pattern of the conductor layer 3 is formed. Thereafter, the structure obtained in this step is immersed in a ferric chloride solution to remove the exposed portion of the copper foil 23, and then the etching-resistant resin layer 31 is peeled off, whereby FIG. As shown in c), the conductor layer 3 is formed on the transfer film 30. At this time, when the conductor layer 3 is the surface conductor layer 3A, the conductor layer 3 has a crystal grain size as small as 0.2 to 1.0 μm, so that the ten-point average roughness (Rz) of the roughened surface is 1.5 to 3.5 μm. It is. For this reason, since the roughened surface and the etching-resistant resin 31 are in close contact with each other without a gap, for example, a fine pattern with a width of 40 μm or less can be formed with high accuracy.

次に、導体層３の露出表面を酸処理により粗化することにより、十点平均粗さ（Ｒｚ）が1.5〜4.0μｍの粗化面とする。このとき、表面導体層３Ａは転写フィルム３０側の主面が粗化されていない平滑面として残るとともに露出する主面が十点平均粗さ（Ｒｚ）で2.0〜4.0μｍの粗化面となり、側面が十点平均粗さ（Ｒｚ）で1.5〜3.5μｍの粗化面となる。また、内部導体層３Ｂは、転写フィルム３０側の主面が1.0〜5.0μｍの粗化面として残るとともに、露出する主面及び側面が十点平均粗さ（Ｒｚ）で1.5〜4.0μｍの粗化面となる。なお、この粗化処理は、塩酸や硫酸、硝酸、酢酸、蟻酸等の酸処理による化学的な薬品処理によって行うことができ、それによって多数の尖頭状の微細な突起を形成することができる。中でも、酸溶液を導体層３に噴霧することが望ましい。   Next, the exposed surface of the conductor layer 3 is roughened by acid treatment to obtain a roughened surface having a 10-point average roughness (Rz) of 1.5 to 4.0 μm. At this time, the surface conductor layer 3A remains as a non-roughened smooth surface on the main surface on the transfer film 30 side, and the exposed main surface becomes a roughened surface with a 10-point average roughness (Rz) of 2.0 to 4.0 μm, The side surface becomes a roughened surface having a 10-point average roughness (Rz) of 1.5 to 3.5 μm. Further, the inner conductor layer 3B remains as a roughened surface having a main surface on the transfer film 30 side of 1.0 to 5.0 μm, and the exposed main surface and side surfaces have a ten-point average roughness (Rz) of 1.5 to 4.0 μm. It becomes a conversion surface. This roughening treatment can be performed by chemical chemical treatment by acid treatment such as hydrochloric acid, sulfuric acid, nitric acid, acetic acid, formic acid, etc., whereby a large number of pointed fine protrusions can be formed. . Among these, it is desirable to spray the acid solution onto the conductor layer 3.

この粗化処理は、図４（ａ）の工程後であって、図４（ｂ）の工程前、すなわち耐エッチング樹脂層３１を被覆する前に行っても良い。それにより、銅箔２３の露出する側の主面に粗化処理を施すことができる。エッチング液を用いて銅箔２３を選択的にエッチングする図４（ｃ）の工程によって、導体層３の側面がある程度に粗化される。   This roughening treatment may be performed after the step of FIG. 4A and before the step of FIG. 4B, that is, before the etching resistant resin layer 31 is coated. Thereby, a roughening process can be performed to the main surface of the copper foil 23 exposed side. The side surface of the conductor layer 3 is roughened to some extent by the step of FIG. 4C in which the copper foil 23 is selectively etched using an etching solution.

なお、表面導体層３Ａの場合、これらの粗化処理は必ずしも要しない。その場合、表面導体層３Ａの前記露出する側の主面は、マット面から成る粗化面として残る。   In the case of the surface conductor layer 3A, these roughening treatments are not necessarily required. In that case, the exposed main surface of the surface conductor layer 3A remains as a roughened surface formed of a mat surface.

また、表面導体層３Ａの粗化面の表面粗さと、内部導体層３Ｂの粗化されたシャイニー面の表面粗さとは、略同一に設定されるのが望ましい。それにより、絶縁層１に対する表面導体層３Ａの接着強度を内部導体層３Ｂの接着強度と同等程度に実現しつつ、表面導体層３Ａを微細パターン化することが可能となる。   Further, it is desirable that the surface roughness of the roughened surface of the surface conductor layer 3A and the surface roughness of the roughened shiny surface of the inner conductor layer 3B are set to be substantially the same. Thereby, the surface conductor layer 3A can be finely patterned while realizing the adhesion strength of the surface conductor layer 3A to the insulating layer 1 to be comparable to the adhesion strength of the internal conductor layer 3B.

次に、耐熱繊維基材に未硬化の熱硬化性樹脂組成物を含浸させて成る絶縁層１用の絶縁シート４０、すなわちプリプレグを複数枚準備する（図４（ｄ））。次に、これらの絶縁シート４０にレーザ光を選択的に照射することにより、貫通導体４を形成するための貫通孔４１を穿孔する（図４（ｅ））。貫通孔４１は、絶縁シート４０の表面に保護フィルムを貼着した後、その上から炭酸ガスレーザやＹＡＧレーザ等のレーザ光を照射することにより形成される。   Next, a plurality of insulating sheets 40 for the insulating layer 1, that is, a plurality of prepregs, prepared by impregnating a heat resistant fiber base material with an uncured thermosetting resin composition is prepared (FIG. 4D). Next, by selectively irradiating these insulating sheets 40 with laser light, through holes 41 for forming the through conductors 4 are drilled (FIG. 4E). The through-hole 41 is formed by applying a protective film on the surface of the insulating sheet 40 and then irradiating a laser beam such as a carbon dioxide laser or a YAG laser from above.

次に、絶縁シート４０に形成された貫通孔４１内に、導電性粉末と未硬化の熱硬化性樹脂とから成る導電性材料のペーストである導電ペースト４２を充填する（図４（ｆ））。導電ペースト４２としては、錫と銀とビスマスと銅とを含有する合金や、銅、銀等の導電性粉末に未硬化のトリアジン系熱硬化性樹脂やエポキシ樹脂等の熱硬化性樹脂と液状の硬化剤とを混練したものが好ましく、導電性材料を熱硬化して成る貫通導体４を低抵抗化するという観点からは、金属粉末に少なくとも鉛や錫を含む低融点金属を含有させることが好ましい。貫通孔４１への導電ペースト４２の充填は、スクリーン印刷法により行なわれる。その際に、印刷用のマスクとして、貫通孔に対応する孔を有するメタルマスクを用いたり、図４（ｅ）の工程で被覆した保護フィルムをそのまま用いたりすることができる。   Next, the through-hole 41 formed in the insulating sheet 40 is filled with a conductive paste 42, which is a conductive material paste made of conductive powder and uncured thermosetting resin (FIG. 4 (f)). . As the conductive paste 42, an alloy containing tin, silver, bismuth, and copper, or a conductive powder such as copper or silver, a thermosetting resin such as an uncured triazine-based thermosetting resin or an epoxy resin, and a liquid What knead | mixed the hardening | curing agent is preferable, and it is preferable to make a metal powder contain the low melting metal containing at least lead and tin from a viewpoint of reducing the through-conductor 4 formed by thermosetting a conductive material. . Filling the through holes 41 with the conductive paste 42 is performed by a screen printing method. At that time, a metal mask having holes corresponding to the through holes can be used as a mask for printing, or the protective film coated in the step of FIG. 4E can be used as it is.

次に、絶縁シート４０から不図示の保護フィルムを剥離した後、転写フィルム３０上に形成した導体層３と貫通孔４１内の導電ペースト４２とが接触するようにして、熱プレスを用いることにより絶縁シート４０の表面に導体層３を熱圧着して埋入させる（図４（ｇ））。その後、絶縁シート４０から転写フィルム３０を剥離することにより、導体層３を絶縁シート４０に転写する（図４（ｈ））。熱圧着は、熱プレス機を用いて、温度が100〜150°Ｃ、圧力が0.5〜5ＭＰａの条件で数分間加圧することにより行なわれる。   Next, after peeling off a protective film (not shown) from the insulating sheet 40, the conductive layer 3 formed on the transfer film 30 and the conductive paste 42 in the through hole 41 are in contact with each other by using a hot press. The conductor layer 3 is embedded in the surface of the insulating sheet 40 by thermocompression bonding (FIG. 4G). Then, the conductor layer 3 is transcribe | transferred to the insulating sheet 40 by peeling the transfer film 30 from the insulating sheet 40 (FIG.4 (h)). Thermocompression bonding is performed by pressurizing for several minutes using a hot press machine under conditions of a temperature of 100 to 150 ° C. and a pressure of 0.5 to 5 MPa.

このとき、導体層３のうち表面導体層３Ａは、十点平均粗さ（Ｒｚ）が2.0〜4.0μｍのマット面又は粗化されたマット面から成る粗化面である側の主面が絶縁シート４０に埋入され、シャイニー面から成る平滑面である側の主面が表面に露出する。導体層３のうち内部導体層３Ｂは、酸処理により粗化されたシャイニー面から成る粗化面である側の主面が絶縁シート４０に埋入され、マット面から成る粗化面である側の主面が表面に露出する。   At this time, the surface conductor layer 3A of the conductor layer 3 is insulated by the main surface on the side which is a mat surface having a ten-point average roughness (Rz) of 2.0 to 4.0 μm or a roughened mat surface. The main surface, which is embedded in the sheet 40 and is a smooth surface including a shiny surface, is exposed on the surface. Of the conductor layers 3, the inner conductor layer 3 </ b> B is a side that is a roughened surface that is formed by matting the main surface, which is a roughened surface made of a shiny surface roughened by acid treatment, into the insulating sheet 40. The main surface of is exposed on the surface.

なお、熱圧着は加熱に先行して加圧のみを行なう方が良い。加熱を先に行なうと、熱によって転写フィルム３０が伸び、導体層３と導電ペースト４２との正確な位置合わせが困難となる傾向がある。従って、熱圧着は加熱に先行して加圧のみを行なうことが好ましい。   In thermocompression bonding, it is better to perform only pressurization prior to heating. When heating is performed first, the transfer film 30 is stretched by heat, and accurate alignment between the conductor layer 3 and the conductive paste 42 tends to be difficult. Therefore, it is preferable to perform only the pressurization prior to the heating in the thermocompression bonding.

また、絶縁シート４０はロール状の連続体ではなく、１枚ずつカットされて供給されることが望ましい。これは通常、導体層３が貼着された転写フィルム３０がロール状の連続体で供給されるため、絶縁シート４０を動かして細かな位置の調整を行ない、導体層３との位置合わせを行なった方が、位置合わせ機構がコンパクトになるためである。なお、導体層３と絶縁シート４０との位置合わせは画像認識装置により、光学的に行なうことができるが、その他、様々な公知の方法も使用しても良い。   The insulating sheet 40 is preferably supplied by being cut one by one, not a roll-like continuous body. Usually, since the transfer film 30 to which the conductor layer 3 is adhered is supplied as a roll-shaped continuous body, the insulating sheet 40 is moved to finely adjust the position and align with the conductor layer 3. This is because the positioning mechanism becomes compact. In addition, although alignment with the conductor layer 3 and the insulating sheet 40 can be performed optically with an image recognition apparatus, you may also use various well-known methods.

次に、導体層３が転写された絶縁シート４０の複数枚を、各絶縁シート４０に転写された導体層３同士が貫通孔４１に充填された導電ペースト４２で接続されるようにして積層した後、それらを加熱加圧する（図４（ｉ））。それにより、絶縁シート４０及び導電ペースト４２の中の熱硬化性樹脂が熱硬化する。その結果、絶縁シート４０の各々が絶縁層１となるとともに、積層された絶縁シート４０すなわち絶縁層１が一体化して絶縁基板２（図１）を形成する。同時に、導電ペースト４２が導体層３と結合した貫通導体４となる。   Next, a plurality of insulating sheets 40 to which the conductor layers 3 were transferred were laminated so that the conductor layers 3 transferred to the insulating sheets 40 were connected to each other with a conductive paste 42 filled in the through holes 41. Thereafter, they are heated and pressurized (FIG. 4 (i)). Thereby, the thermosetting resin in the insulating sheet 40 and the conductive paste 42 is thermoset. As a result, each of the insulating sheets 40 becomes the insulating layer 1, and the laminated insulating sheets 40, that is, the insulating layers 1 are integrated to form the insulating substrate 2 (FIG. 1). At the same time, the conductive paste 42 becomes the through conductor 4 combined with the conductor layer 3.

すなわち、図４（ｉ）の工程によって、複数の絶縁層１が積層された絶縁基板２の表面及び絶縁層１の間に導体層３が埋設されているとともに、絶縁基板２の表面に埋設された表面導体層３Ａの結晶粒径が絶縁層１の間に埋設された内部導体層３Ｂの結晶粒径よりも小さな配線基板１００が得られる。なお、積層体の加熱処理にあたっては、積層体をフッ素系樹脂等から成る離型性シートで上下から挟みこみ、1〜5ＭＰａの圧力で150〜240°Ｃの温度で熱処理して、絶縁シート４０及び導電ペースト４２中の熱硬化性樹脂を熱硬化させることが好ましい。   That is, the conductor layer 3 is embedded between the surface of the insulating substrate 2 on which the plurality of insulating layers 1 are laminated and the insulating layer 1 and embedded in the surface of the insulating substrate 2 by the process of FIG. Further, the wiring substrate 100 having a smaller crystal grain size of the surface conductor layer 3A than that of the inner conductor layer 3B embedded between the insulating layers 1 is obtained. In the heat treatment of the laminated body, the laminated body is sandwiched from above and below by a release sheet made of a fluorine resin or the like, and heat treated at a pressure of 1 to 5 MPa at a temperature of 150 to 240 ° C. The thermosetting resin in the conductive paste 42 is preferably thermoset.

図４（ｉ）は、内部導体層３Ｂが埋設された絶縁シート４０が１枚である例を示しているが、言うまでもなく、内部導体層３Ｂが埋設された絶縁シート４０は複数枚であってもよい。図１に例示する配線基板１００は、表面導体層３Ａが埋設された絶縁層１を２層有し、それらの間に挟まれるように、内部導体層３Ｂが埋設された絶縁層１を６層有している。従って、配線基板１００を製造するためには、内部導体層３Ｂが埋設された絶縁シート４０を得るための図４（ａ）〜図４（ｈ）の工程が６回反復して実行され、表面導体層３Ａが埋設された絶縁シート４０を得るための図４（ａ）〜図４（ｈ）の工程が２回反復して実行される。   FIG. 4 (i) shows an example in which there is one insulating sheet 40 in which the internal conductor layer 3B is embedded. Needless to say, there are a plurality of insulating sheets 40 in which the internal conductor layer 3B is embedded. Also good. A wiring board 100 illustrated in FIG. 1 has two insulating layers 1 in which a surface conductor layer 3A is embedded, and six insulating layers 1 in which an inner conductor layer 3B is embedded so as to be sandwiched between them. Have. Therefore, in order to manufacture the wiring substrate 100, the process of FIGS. 4A to 4H for obtaining the insulating sheet 40 in which the internal conductor layer 3B is embedded is repeatedly performed six times, The process of FIG. 4A to FIG. 4H for obtaining the insulating sheet 40 in which the conductor layer 3A is embedded is repeated twice.

また、内部導体層３Ｂが埋設された絶縁シート４０を得るための一回ないし複数回の図４（ａ）〜図４（ｈ）の工程と、表面導体層３Ａが埋設された絶縁シート４０を得るための一回ないし複数回の図４（ａ）〜図４（ｈ）の工程とは、互いに順序が任意であり、且つ互いに同時並行に行われても良い。更に、図３及び図４（ａ）〜図４（ｃ）の工程と、図４（ｄ）〜図（ｆ）の工程とは、互いに順序が任意であり、且つ互いに同時並行に行われても良い。   Moreover, the process of FIG. 4 (a)-FIG.4 (h) for obtaining the insulating sheet 40 with which the internal conductor layer 3B was embedded, and the insulating sheet 40 with which the surface conductor layer 3A was embedded are provided. The order of the steps of FIG. 4 (a) to FIG. 4 (h) to be obtained is arbitrary and may be performed in parallel with each other. Further, the steps of FIGS. 3 and 4A to 4C and the steps of FIGS. 4D to 4F are arbitrary in order, and are performed in parallel with each other. Also good.

なお、本発明は上述の実施例に限定されるものではなく、本発明の要旨を逸脱しない範囲であれば、種々の変更が可能であることは言うまでもない。例えば、本発明の配線基板をコア基板として用い、その少なくとも一方の主面にエポキシ樹脂等の熱硬化性樹脂から成る絶縁層と銅めっき膜から成る配線層をビルドアップ法により交互に多層に積層してビルドアップ基板としてもよい。   Needless to say, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the present invention. For example, the wiring board of the present invention is used as a core board, and an insulating layer made of a thermosetting resin such as an epoxy resin and a wiring layer made of a copper plating film are alternately laminated in multiple layers by a build-up method on at least one main surface thereof. And it is good also as a buildup board.

本発明の配線基板の一実施の形態を示す断面図である。It is sectional drawing which shows one Embodiment of the wiring board of this invention. 図１の一部拡大断面図である。It is a partially expanded sectional view of FIG. 図１の配線基板の製造工程図である。FIG. 2 is a manufacturing process diagram of the wiring board of FIG. 1. 図１の配線基板の製造工程図である。FIG. 2 is a manufacturing process diagram of the wiring board of FIG. 1.

符号の説明Explanation of symbols

１・・・・絶縁層（第１、第２絶縁層）
２・・・・絶縁基板
３・・・・導体層
３Ａ・・・・表面導体層（第２導体層）
３Ｂ・・・・内部導体層（第１導体層）
４・・・・貫通導体
２３・・・・銅箔（金属箔）
２３Ａ・・・・銅箔（第２金属箔）
２３Ｂ・・・・銅箔（第１金属箔）
３０・・・・転写フィルム（第１、第２フィルム）
４０・・・・絶縁シート（第１、第２絶縁層） 1. Insulating layer (first and second insulating layers)
2 ... Insulating substrate 3 ... Conductor layer 3A ... Surface conductor layer (second conductor layer)
3B ... ・ Inner conductor layer (first conductor layer)
4 ... Penetration conductor 23 ... Copper foil (metal foil)
23A ... Copper foil (second metal foil)
23B ... Copper foil (first metal foil)
30 ... Transfer film (first and second film)
40... Insulating sheet (first and second insulating layers)

Claims (12)

複数層の導体層を有する多層構造の配線基板であって、
絶縁基板と、
前記絶縁基板の表面に埋設された金属箔から成る表面導体層と、
前記絶縁基板の内部に埋設された金属箔から成る内部導体層と、を備え、
前記表面導体層の結晶粒径が前記内部導体層の結晶粒径よりも小さく、
前記表面導体層は、その埋設された側の主面がマット面又は粗化されたマット面から成る粗化面であるとともに、露出する側の主面がシャイニー面から成る非粗化面又は粗化されたシャイニー面から成る粗化面であり、
前記内部導体層は、一主面がマット面から成る粗化面であり、他主面が粗化されたシャイニー面から成る粗化面であることを特徴とする配線基板。 A multilayer wiring board having a plurality of conductor layers,
An insulating substrate;
A surface conductor layer made of a metal foil embedded in the surface of the insulating substrate;
An inner conductor layer made of a metal foil embedded in the insulating substrate,
The crystal grain size of the surface conductor layer is smaller than the crystal grain size of the inner conductor layer,
The surface conductor layer is a roughened surface whose main surface on the embedded side is a mat surface or a roughened mat surface, and whose main surface on the exposed side is a non-roughened surface or rough surface whose surface is a shiny surface. It is a roughened surface consisting of a shiny surface
The wiring board according to claim 1, wherein the inner conductor layer is a roughened surface having one main surface made of a matte surface and the other main surface made of a roughened shiny surface. 前記表面導体層の埋設された側の前記主面の表面粗さが、前記内部導体層の前記他主面の表面粗さに略同一であることを特徴とする請求項１記載の配線基板。   2. The wiring board according to claim 1, wherein the surface roughness of the main surface on the side where the surface conductor layer is embedded is substantially the same as the surface roughness of the other main surface of the internal conductor layer. 前記表面導体層は、その埋設された側面が粗化面であることを特徴とする請求項１又は２記載の配線基板。   The wiring board according to claim 1, wherein the surface conductor layer has a roughened side surface. 前記表面導体層の前記側面の十点平均粗さ（Ｒｚ）が1.5〜3.5μｍであることを特徴とする請求項３に記載の配線基板。   The wiring board according to claim 3, wherein a ten-point average roughness (Rz) of the side surface of the surface conductor layer is 1.5 to 3.5 μm. 前記内部導体層は、その埋設された側面が粗化面であることを特徴とする請求項１ないし４の何れかに記載の配線基板。   The wiring board according to claim 1, wherein the inner conductor layer has a roughened side surface. 前記表面導体層の結晶粒径が0.2〜1.0μｍであり、前記内部導体層の結晶粒径が0.6〜1.8μｍであることを特徴とする請求項１ないし５の何れかに記載の配線基板。   6. The wiring board according to claim 1, wherein the surface conductor layer has a crystal grain size of 0.2 to 1.0 [mu] m, and the inner conductor layer has a crystal grain size of 0.6 to 1.8 [mu] m. 前記表面導体層は、その埋設された側の前記主面の十点平均粗さ（Ｒｚ）が2.0〜4.0μｍであることを特徴とする請求項１ないし６の何れかに記載の配線基板。   The wiring board according to claim 1, wherein the surface conductor layer has a ten-point average roughness (Rz) of 2.0 to 4.0 μm of the main surface on the embedded side. 前記表面導体層の露出する側の前記主面の十点平均粗さ（Ｒｚ）が1.0〜3.0μｍであることを特徴とする請求項１ないし７の何れかに記載の配線基板。   The wiring board according to claim 1, wherein a ten-point average roughness (Rz) of the main surface on the exposed side of the surface conductor layer is 1.0 to 3.0 μm. 前記内部導体層の前記一主面の十点平均粗さ（Ｒｚ）が1.0〜5.0μｍであることを特徴とする請求項１ないし８の何れかに記載の配線基板。   The wiring board according to claim 1, wherein a ten-point average roughness (Rz) of the one main surface of the inner conductor layer is 1.0 to 5.0 μm. 複数層の導体層を有する多層構造の配線基板を製造する方法であって、
第１金属箔をめっきにより形成する第１工程と、
前記第１金属箔のマット面が接着面となるように前記第１金属箔を第１フィルムに接着させる第２工程と、
前記第１金属箔をパターニングすることにより第１導体層を形成する第３工程と、
前記第２工程と前記第３工程との間、又は前記第３工程の後に、前記第１金属箔のシャイニー面を溶液処理により粗化する第４工程と、
前記第３工程及び前記第４工程の後に、前記第１フィルムを未硬化ないし半硬化の第１絶縁層に圧力を加えつつ積層することにより前記第１導体層を前記第１絶縁層の表面に埋設する第５工程と、
前記第５工程の後に、前記第１フィルムを剥離することにより前記第１導体層を前記第１絶縁層の表面に転写する第６工程と、
前記第１金属箔よりも結晶粒径が小さくなるように第２金属箔をめっきにより形成する第７工程と、
前記第２金属箔のシャイニー面が接着面となるように前記第２金属箔を第２フィルムに接着させる第８工程と、
前記第２金属箔をパターニングすることにより第２導体層を形成する第９工程と、
前記第９工程の後に、前記第２フィルムを未硬化ないし半硬化の第２絶縁層に圧力を加えつつ積層することにより前記第２導体層を前記第２絶縁層の表面に埋設する第１０工程と、
前記第１０工程の後に、前記第２フィルムを剥離することにより前記第２導体層を前記第２絶縁層の表面に転写する第１１工程と、
前記第６工程及び前記第１１工程の後に、前記第１導体層が内部に位置し前記第２導体層が表面に位置するように、前記第１絶縁層と前記第２絶縁層とを積層して硬化させる第１２工程と、を備える配線基板の製造方法。 A method of manufacturing a wiring board having a multilayer structure having a plurality of conductor layers,
A first step of forming a first metal foil by plating;
A second step of adhering the first metal foil to the first film so that the matte surface of the first metal foil becomes an adhesive surface;
A third step of forming a first conductor layer by patterning the first metal foil;
A fourth step of roughening the shiny surface of the first metal foil by solution treatment between the second step and the third step or after the third step;
After the third step and the fourth step, the first conductive layer is laminated on the surface of the first insulating layer by laminating the first film while applying pressure to the uncured or semi-cured first insulating layer. A fifth step of burying;
After the fifth step, a sixth step of transferring the first conductor layer to the surface of the first insulating layer by peeling off the first film;
A seventh step of forming the second metal foil by plating so that the crystal grain size is smaller than that of the first metal foil;
An eighth step of adhering the second metal foil to the second film so that the shiny surface of the second metal foil becomes an adhesive surface;
A ninth step of forming a second conductor layer by patterning the second metal foil;
After the ninth step, the tenth step of embedding the second conductor layer in the surface of the second insulating layer by laminating the second film while applying pressure to the uncured or semi-cured second insulating layer. When,
After the tenth step, an eleventh step of transferring the second conductor layer to the surface of the second insulating layer by peeling off the second film;
After the sixth step and the eleventh step, the first insulating layer and the second insulating layer are laminated so that the first conductor layer is located inside and the second conductor layer is located on the surface. And a twelfth step of curing the wiring substrate. Ｎを１以上の整数として、前記第１工程ないし第６工程を、Ｎ回反復する反復工程を更に備え、
前記第１２工程は、Ｎ＋１回の前記第６工程及び前記第１１工程の後に、全ての前記第１導体層が内部に位置し前記第２導体層が表面に位置するように、Ｎ＋１枚の前記第１絶縁層と前記第２絶縁層とを積層して硬化させる請求項１０記載の配線基板の製造方法。 N is an integer greater than or equal to 1, and further includes an iterative process of repeating the first to sixth processes N times,
In the twelfth step, N + 1 sheets of the first and second conductive layers are positioned on the surface after the N + 1th sixth and eleventh steps so that all the first conductive layers are positioned inside. The method for manufacturing a wiring board according to claim 10, wherein the first insulating layer and the second insulating layer are laminated and cured. 前記第８工程と前記第９工程との間、又は前記第９工程の後に、前記第２金属箔のマット面を溶液処理により更に粗化する第１３工程を更に備える請求項１０又は１１に記載の配線基板の製造方法。   The 13th process which further roughens the mat | matte surface of a said 2nd metal foil by a solution process between the said 8th process and the said 9th process, or after the said 9th process. Wiring board manufacturing method.
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