JP2006261687A - 半導体デバイスの製造方法 - Google Patents
半導体デバイスの製造方法 Download PDFInfo
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- JP2006261687A JP2006261687A JP2006129423A JP2006129423A JP2006261687A JP 2006261687 A JP2006261687 A JP 2006261687A JP 2006129423 A JP2006129423 A JP 2006129423A JP 2006129423 A JP2006129423 A JP 2006129423A JP 2006261687 A JP2006261687 A JP 2006261687A
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
- H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
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Abstract
【解決手段】 絶縁層68,81のエッチングは、1,2−エタンジオール,フッ化水素およびフッ化アンモニアを含むエッチング溶液を用いて行われる。このエッチング溶液は、絶縁層68,81の100〜900オングストロームの範囲でエッチングする。このエッチングは、絶縁層68,81内の移動イオンの少なくと75パーセントを除去し、移動イオンの少なくとも95パーセントを除去しなければならない。このプロセスは、酸フード,酸コンパチブル・スプレー・ツールまたはパドル処理ツールを用いて実施できる。このプロセスは、このプロセスを多くの異なる既存の処理工程に容易に統合できる多くの異なる実施例を含む。同様なプロセスは、レジスト・エッチバック処理工程でも利用できる。
【選択図】 図1
Description
程と、この金属含有層の露出部分をハロゲン化物含有プラズマ・エッチング剤でエッチングして、相互接続部材を形成する工程と、パターニングされた有機マスキング層を、有機マスキング層溶媒ではなくプラズマ・ガスで除去する工程と、第1絶縁層の一部をフッ化物含有溶液でエッチングする工程と、相互接続部材の上に第2絶縁層を形成する工程によって構成される。第1絶縁層の一部をエッチングする段階は、第1絶縁層の少なくとも100オングストロームをエッチングするか、あるいは第1絶縁層から移動イオンの少なくとも75パーセントを除去する。第1絶縁層の一部をエッチングする工程は、露出部分をエッチングする工程の後で、相互接続部材の上に層を形成する前に行われる。
本発明の実施例は、金属エッチング処理工程またはレジスト・エッチバック処理工程中に半導体装置に導入される移動イオン不純物を低減するために用いることができる。移動イオン不純物は、プラズマ金属エッチング工程中およびプラズマ金属エッチング工程のための有機マスキング層溶媒処理中に導入されると考えられる。有機マスキング層溶媒を省き、かつプラズマ金属エッチング工程の後に絶縁層の一部をエッチングすることにより、金属エッチング処理工程中に導入される移動イオン不純物は実質的に低減される。レジスト・エッチバック処理工程では、移動イオンは、有機層および絶縁層が同時にエッチングされるときに導入されることがある。絶縁層の一部はエッチングされ、絶縁層における移動イオン濃度を低減する。本発明は、以下で説明するいくつかの実施例でより理解される。
図1は、半導体装置を形成するために用いられる処理工程を含む。この処理工程は、コンタクトまたは穴(ビア)開口部を形成する工程11と、相互接続層を被着する工程12と、フォトレジスト・マスキング層を形成する工程13と、相互接続層を選択的にエッチングする工程14と、アッシング(有機マスキング層溶媒ではない)によりフォトレジスト・マスキング層を除去する工程15と、基板16を処理する工程16と、絶縁層を被着する工程17とを含む。
glass) ,PSG(phosphosilicate glass) などからなる第1レベル間絶縁層(first int
erlevel insulating layer) 28は、基板20の上にあり、ドレイン・コンタクト開口部291およびゲート・コンタクト開口部292を有する。第1絶縁層28は、約8000オングストローム厚であるが、他の実施例では4000〜8000オングストローム厚でもよい。この時点で示される装置を形成するためには、従来の工程が用いられる。
間絶縁層68が得られる。さまざまな処理要因の組合せを利用して、洗浄された第1レベル間絶縁層68を形成できる。これらの組合せは、機器の安定性、プロセスの安定性、第1レベル間絶縁層28の除去速度の制御、基板表面における除去速度の均等性を考慮して選ばれる。洗浄された第1レベル間絶縁層68を形成するために処理工程を統合することの特定の詳細は、処理工程が統合される機器に依存する。処理工程は、酸フード(acid hood) ,酸コンパチブル・スプレー・ツール(acid-compatible spray tool)またはパドル処理ツール(puddle processing tool)で行うことができる。これらすべての装置は当技術分野で周知であるが、酸コンパチブル・スプレー・ツールおよびパドル処理ツールについて簡単に説明する。酸コンパチブル・スプレー・ツールは、酸を利用できるように修正されている点を除いて、スピン・リンス乾燥機(SRD:spin rinse dryer)に類似している。パドル処理ツールは、基板が薬品の少なくとも1つの「パドル」を介して送られる点を除いて、フォトレジストを基板にコーティングするために用いられるトラックに類似した装置である。一般に、基板はパドル内にあるときに回転される。
相互接続の例で説明したのと同様な移動イオンおよび他の装置信頼性の問題の一部は、レジスト・エッチバック・プロセスでも生じることがある。図10は、レジスト・エッチバック(REB)処理工程の前の半導体基板の一部の断面図を含む。フィールド分離領域101,ソース領域102,ドレイン領域103およびチャネル領域106は、基板100内に少なくとも部分的にある。ゲート誘電層104およびゲート電極105は、チャネル領域106とソースおよびドレイン領域102,103の一部の上にある。
出面に結合して、移動イオンを引きつけ、装置における移動イオン濃度を増加することがあると考えられる。高い移動イオン濃度は、装置の性能および信頼性を低減することが知られている。
Claims (4)
- 半導体基板(20)の上方に第1絶縁層(28,71)を形成する工程と、
前記第1絶縁層(28,71)の上方に金属含有層(41)を被着する工程と、
前記金属含有層の上方にパターニングされた有機マスキング層(421,422)を形成することによって、金属含有層(41)に露出部分を形成する工程と、
前記金属含有層(41)の露出部分を、ハロゲン化物含有プラズマ・エッチング剤でエッチングして、相互接続部材(411,412,75)を形成する工程であって、このエッチング工程の間に前記第1絶縁層に移動イオンが入れられる、相互接続部材の形成工程と、
パターニングされた有機マスキング層(421,422)を、有機マスキング層溶媒ではなくプラズマ・ガスで除去する工程と、
第1絶縁層(28,71)の一部をエッチング溶液でエッチングする工程であって、この工程は、前記露出部分のエッチング工程の後、かつ前記相互接続部材(411,412,75)の上方にいかなる層を形成する前に行われて、前記第1絶縁層(68,81)の少なくとも10nm(100オングストローム)をエッチングし、または前記第1絶縁層から少なくとも75パーセントの移動イオンを除去する、第1絶縁層の一部のエッチング工程と、
前記相互接続部材の上方に第2絶縁層(71,82)を形成する工程とを備える、半導体装置の製造方法。 - 前記エッチング溶液は摂氏20度で少なくとも2センチポイズの粘性を有するキャリア溶媒を含有する、請求項1に記載の半導体装置の製造方法。
- 前記基板を脱イオン水で洗浄する前に、前記基板をアルコールおよびグリコールからなる群から選択された薬品によって洗浄する工程と、
前記基板を脱イオン水で洗浄する工程と、
前記基板を乾燥する工程とをさらに備え、
前記基板を薬品で洗浄する工程、脱イオン水で洗浄する工程、および乾燥する工程は、前記第1絶縁層の一部のエッチング工程と、前記第2絶縁層の形成工程との間に行われる、請求項1に記載の半導体装置の製造方法。 - 前記第1絶縁層の一部のエッチング工程、および前記基板を薬品で洗浄する工程、脱イオン水で洗浄する工程、および乾燥する工程は、酸コンパチブル・スプレー・ツールの内部で同一のサイクルの間に行われる、請求項3に記載の半導体装置の製造方法。
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EP (1) | EP0675535A1 (ja) |
JP (2) | JPH07283320A (ja) |
KR (1) | KR100217450B1 (ja) |
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