JP6989207B2 - キャパシタの製造方法 - Google Patents
キャパシタの製造方法 Download PDFInfo
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- JP6989207B2 JP6989207B2 JP2018093539A JP2018093539A JP6989207B2 JP 6989207 B2 JP6989207 B2 JP 6989207B2 JP 2018093539 A JP2018093539 A JP 2018093539A JP 2018093539 A JP2018093539 A JP 2018093539A JP 6989207 B2 JP6989207 B2 JP 6989207B2
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- dielectric layer
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- 239000003990 capacitor Substances 0.000 title claims description 57
- 238000004519 manufacturing process Methods 0.000 title claims description 34
- 238000000034 method Methods 0.000 claims description 72
- 238000004140 cleaning Methods 0.000 claims description 68
- 239000012530 fluid Substances 0.000 claims description 13
- 238000010030 laminating Methods 0.000 claims description 9
- 238000007598 dipping method Methods 0.000 claims description 4
- 239000002245 particle Substances 0.000 description 58
- 230000002950 deficient Effects 0.000 description 20
- 239000010408 film Substances 0.000 description 17
- 239000000758 substrate Substances 0.000 description 12
- 230000007547 defect Effects 0.000 description 11
- 230000015572 biosynthetic process Effects 0.000 description 10
- 230000015556 catabolic process Effects 0.000 description 10
- 230000007423 decrease Effects 0.000 description 10
- 230000000052 comparative effect Effects 0.000 description 9
- 230000005684 electric field Effects 0.000 description 9
- 239000010931 gold Substances 0.000 description 9
- 238000010586 diagram Methods 0.000 description 7
- 239000002184 metal Substances 0.000 description 6
- 229910052751 metal Inorganic materials 0.000 description 6
- 238000005406 washing Methods 0.000 description 6
- 229910052581 Si3N4 Inorganic materials 0.000 description 5
- 238000005229 chemical vapour deposition Methods 0.000 description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 5
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 4
- 229910052737 gold Inorganic materials 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- 238000003475 lamination Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 2
- 238000009751 slip forming Methods 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 238000004380 ashing Methods 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 239000000428 dust Substances 0.000 description 1
- 238000007654 immersion Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000007736 thin film deposition technique Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
- H01L21/0206—Cleaning during device manufacture during, before or after processing of insulating layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/75—Electrodes comprising two or more layers, e.g. comprising a barrier layer and a metal layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
- H01L23/5223—Capacitor integral with wiring layers
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Integrated Circuits (AREA)
- Cleaning Or Drying Semiconductors (AREA)
- Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
- Ceramic Capacitors (AREA)
Description
本発明の一形態は、下部電極と誘電体と上部電極とが積層されたMIM構造を有するキャパシタの製造方法であって、下部電極の上面に複数回の積層によって誘電体を形成する工程と、誘電体の上面に上部電極を形成する工程と、を有し、誘電体は、下部電極の上面に形成された第1の誘電体層と、第1の誘電体層の上面に形成されて上部電極に接する第2の誘電体層と、を含み、誘電体を形成する工程は、下部電極の上面に少なくとも一層の第1の誘電体層を形成し、第1の誘電体層の上面をジェット洗浄及び二流体洗浄の少なくとも一方により洗浄し、洗浄された第1の誘電体層の上面に第2の誘電体層を形成する。
以下、本発明の実施形態に係るキャパシタの製造方法について、図面を参照して詳細に説明する。なお、本発明はこれらの例示に限定されるものではなく、特許請求の範囲によって示され、特許請求の範囲と均等の意味および範囲内でのすべての変更が含まれることが意図される。また、各図において同一又は相当部分には同一符号を付し、重複する説明を省略する。
Claims (1)
- 下部電極と誘電体と上部電極とが積層されたMIM構造を有するキャパシタの製造方法であって、
前記下部電極の上面に複数回の積層によって前記誘電体を形成する工程と、
前記誘電体の上面に前記上部電極を形成する工程と、を有し、
前記誘電体は、前記下部電極の上面に形成された第1の誘電体層と、前記第1の誘電体層の上面に形成されて前記上部電極に接する第2の誘電体層と、を含み、
前記誘電体を形成する工程は、前記下部電極の上面に少なくとも一層の前記第1の誘電体層を形成し、前記第1の誘電体層の上面をジェット洗浄及び二流体洗浄の少なくとも一方により洗浄し、洗浄された前記第1の誘電体層の上面に前記第2の誘電体層を形成し、
前記上部電極を形成する工程の前に、前記第2の誘電体層の上面を浸漬洗浄方式及びシャワー洗浄方式の少なくともいずれか一方により洗浄する、キャパシタの製造方法。
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2018093539A JP6989207B2 (ja) | 2018-05-15 | 2018-05-15 | キャパシタの製造方法 |
US16/411,668 US11152457B2 (en) | 2018-05-15 | 2019-05-14 | Method of manufacturing capacitor |
CN201910397664.9A CN110491992A (zh) | 2018-05-15 | 2019-05-14 | 电容器的制造方法 |
US17/369,705 US11990504B2 (en) | 2018-05-15 | 2021-07-07 | Capacitor with MIM |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2018093539A JP6989207B2 (ja) | 2018-05-15 | 2018-05-15 | キャパシタの製造方法 |
Publications (2)
Publication Number | Publication Date |
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JP2019201064A JP2019201064A (ja) | 2019-11-21 |
JP6989207B2 true JP6989207B2 (ja) | 2022-01-05 |
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JP2018093539A Active JP6989207B2 (ja) | 2018-05-15 | 2018-05-15 | キャパシタの製造方法 |
Country Status (3)
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US (2) | US11152457B2 (ja) |
JP (1) | JP6989207B2 (ja) |
CN (1) | CN110491992A (ja) |
Family Cites Families (22)
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US5476816A (en) * | 1994-03-28 | 1995-12-19 | Motorola, Inc. | Process for etching an insulating layer after a metal etching step |
JP3323384B2 (ja) * | 1995-12-21 | 2002-09-09 | 大日本スクリーン製造株式会社 | 基板洗浄装置および基板洗浄方法 |
US5968280A (en) * | 1997-11-12 | 1999-10-19 | International Business Machines Corporation | Method for cleaning a surface |
JPH11154734A (ja) * | 1997-11-21 | 1999-06-08 | Advantest Corp | 薄膜コンデンサの形成方法 |
CN1184653C (zh) * | 1999-12-03 | 2005-01-12 | 松下电器产业株式会社 | 固体电解电容器的制作方法及固体电解电容器 |
JP3693875B2 (ja) | 2000-01-26 | 2005-09-14 | Necエレクトロニクス株式会社 | 回路製造方法 |
JP3493605B2 (ja) * | 2000-05-11 | 2004-02-03 | Necトーキン富山株式会社 | 固体電解コンデンサの製造方法 |
JP3989276B2 (ja) * | 2002-04-01 | 2007-10-10 | 株式会社ルネサステクノロジ | 半導体装置の製造方法 |
US6902440B2 (en) * | 2003-10-21 | 2005-06-07 | Freescale Semiconductor, Inc. | Method of forming a low K dielectric in a semiconductor manufacturing process |
CN100490031C (zh) * | 2004-08-31 | 2009-05-20 | 梁颖光 | 单层电容器元件的制备方法 |
JP2006086155A (ja) | 2004-09-14 | 2006-03-30 | Matsushita Electric Ind Co Ltd | 半導体装置及びその製造方法 |
KR100716655B1 (ko) * | 2006-06-29 | 2007-05-09 | 주식회사 하이닉스반도체 | 지르코늄산화막과 탄탈륨산화막이 적층된 유전막 형성 방법및 그를 이용한 캐패시터의 제조 방법 |
JP2008041921A (ja) * | 2006-08-07 | 2008-02-21 | Matsushita Electric Ind Co Ltd | 圧電薄膜素子およびその製造方法、ならびにインクジェットヘッドおよびインクジェット式記録装置 |
US20080076688A1 (en) * | 2006-09-21 | 2008-03-27 | Barnes Jeffrey A | Copper passivating post-chemical mechanical polishing cleaning composition and method of use |
TWI323034B (en) * | 2006-12-25 | 2010-04-01 | Ind Tech Res Inst | Electronic devices with hybrid high-k dielectric and fabrication methods thereof |
JP5194463B2 (ja) * | 2007-01-31 | 2013-05-08 | パナソニック株式会社 | 圧電体薄膜素子の製造方法 |
KR101599724B1 (ko) * | 2009-02-16 | 2016-03-04 | 삼성전자 주식회사 | 반도체 장치 및 그 제조 방법 |
CN103632976B (zh) * | 2012-08-29 | 2016-06-29 | 中芯国际集成电路制造(上海)有限公司 | 晶体管的形成方法 |
JP5928283B2 (ja) | 2012-09-28 | 2016-06-01 | 東京エレクトロン株式会社 | 基板処理装置、基板搬送方法及び記憶媒体 |
JP2016186599A (ja) * | 2015-03-27 | 2016-10-27 | セイコーエプソン株式会社 | 液晶装置の製造方法、液晶装置、及び電子機器 |
KR102621751B1 (ko) * | 2016-06-02 | 2024-01-05 | 삼성전자주식회사 | 반도체 장치 및 그 제조 방법 |
US10679936B2 (en) * | 2017-09-28 | 2020-06-09 | Taiwan Semiconductor Manufacturing Co., Ltd. | MIM structure |
-
2018
- 2018-05-15 JP JP2018093539A patent/JP6989207B2/ja active Active
-
2019
- 2019-05-14 US US16/411,668 patent/US11152457B2/en active Active
- 2019-05-14 CN CN201910397664.9A patent/CN110491992A/zh active Pending
-
2021
- 2021-07-07 US US17/369,705 patent/US11990504B2/en active Active
Also Published As
Publication number | Publication date |
---|---|
JP2019201064A (ja) | 2019-11-21 |
US20210335992A1 (en) | 2021-10-28 |
US20190355805A1 (en) | 2019-11-21 |
US11990504B2 (en) | 2024-05-21 |
CN110491992A (zh) | 2019-11-22 |
US11152457B2 (en) | 2021-10-19 |
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