JP2006229186A - 半導体集積回路およびその製造方法 - Google Patents
半導体集積回路およびその製造方法 Download PDFInfo
- Publication number
- JP2006229186A JP2006229186A JP2005315525A JP2005315525A JP2006229186A JP 2006229186 A JP2006229186 A JP 2006229186A JP 2005315525 A JP2005315525 A JP 2005315525A JP 2005315525 A JP2005315525 A JP 2005315525A JP 2006229186 A JP2006229186 A JP 2006229186A
- Authority
- JP
- Japan
- Prior art keywords
- electrode pad
- integrated circuit
- input
- semiconductor integrated
- output signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 89
- 238000004519 manufacturing process Methods 0.000 title claims description 27
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 37
- 230000001681 protective effect Effects 0.000 claims description 12
- 238000000034 method Methods 0.000 description 27
- 229910052751 metal Inorganic materials 0.000 description 26
- 239000002184 metal Substances 0.000 description 26
- 239000010410 layer Substances 0.000 description 21
- 238000005229 chemical vapour deposition Methods 0.000 description 6
- 239000000523 sample Substances 0.000 description 6
- 239000011229 interlayer Substances 0.000 description 5
- 238000012986 modification Methods 0.000 description 5
- 230000004048 modification Effects 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 239000000758 substrate Substances 0.000 description 4
- 238000005530 etching Methods 0.000 description 3
- 239000004642 Polyimide Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000007687 exposure technique Methods 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 230000006641 stabilisation Effects 0.000 description 1
- 238000011105 stabilization Methods 0.000 description 1
- 230000000087 stabilizing effect Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
- H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
- H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
- H01L2224/02165—Reinforcing structures
- H01L2224/02166—Collar structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05075—Plural internal layers
- H01L2224/0508—Plural internal layers being stacked
- H01L2224/05085—Plural internal layers being stacked with additional elements, e.g. vias arrays, interposed between the stacked layers
- H01L2224/05089—Disposition of the additional element
- H01L2224/05093—Disposition of the additional element of a plurality of vias
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05075—Plural internal layers
- H01L2224/0508—Plural internal layers being stacked
- H01L2224/05085—Plural internal layers being stacked with additional elements, e.g. vias arrays, interposed between the stacked layers
- H01L2224/05089—Disposition of the additional element
- H01L2224/05093—Disposition of the additional element of a plurality of vias
- H01L2224/05096—Uniform arrangement, i.e. array
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/05624—Aluminium [Al] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/0605—Shape
- H01L2224/06051—Bonding areas having different shapes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/118—Masterslice integrated circuits
- H01L27/11898—Input and output buffer/driver structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01004—Beryllium [Be]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01014—Silicon [Si]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01015—Phosphorus [P]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01074—Tungsten [W]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01076—Osmium [Os]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Integrated Circuits (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
【解決手段】集積回路領域1aと、この集積回路領域1aと外部とを電気的に接続するための素子形成領域をそれぞれ有する複数のI/Oセル6とを具備した半導体集積回路1であって、上記各I/Oセル6の素子形成領域上に、入出力信号用電極パッド3、電源用電極パッド4およびGND用電極パッド5を配置したものである。
【選択図】図2
Description
図9は半導体集積回路の一般的な構成を示す図で、(a)は平面図、(b)は(a)のD−D’断面図、(c)は(b)のE部の拡大図である。
すなわち、図9(a)〜(c)において、51は半導体集積回路(半導体チップともいう)、52はPOE構造を有する電極パッドである。58はPSiNなどの第1の保護膜、59はポリイミドなどの第2の保護膜、63は層間絶縁膜、65はシリコン基板である。
例えば、ロジック回路やドライバ回路の上に層間絶縁膜を設け、そしてその上に、入力パッドまたは出力パッドを形成した半導体集積回路が提案されている(例えば、特許文献1参照)。
上記各I/Oセルの素子形成領域上に、入出力信号用電極パッド、電源用電極パッドおよびGND用電極パッドを配置したものである。
上記各I/Oセルの素子形成領域上に、1つ以上の入出力信号用電極パッドと、電源用電極パッドまたはGND用電極パッドのいずれかを配置したものである。
隣接する2つのI/Oセルの素子形成領域に跨って、1つ以上の入出力信号用電極パッドと、電源用電極パッドまたはGND用電極パッドのいずれかを配置したものである。
隣接する2つのI/Oセルの素子形成領域に跨って、1つ以上の入出力信号用電極パッドを配置するとともに、
これら2つのI/Oセル同士に1つ以上の入出力信号用電極パッドが配置されてなるI/Oセルの組を、隣接する2組における4つのI/Oセルの素子形成領域上に跨って電源用電極パッドまたはGND用電極パッドのいずれかを配置したものである。
隣接する2つのI/Oセルの素子形成領域上にそれぞれ跨り且つ当該I/Oセルの長さ方向において内側から外側に向かって順次配置された内側位置および外側位置の2つの入出力信号用電極パッドと、この中間位置の入出力信号用電極パッドの外側の上記I/Oセルの素子形成領域に配置される電源用電極パッドまたはGND用電極パッドとを具備し、
さらに内側位置の入出力信号用電極パッドにおけるI/Oセルでの幅方向の一端側を所定幅でもって中間位置の入出力信号電極パッドまで延設するとともに、中間位置の入出力信号用電極パッドにおけるI/Oセルでの幅方向の他端側を所定幅でもって外側位置の電源用電極パッドまたはGND用電極パッドまで延設したものである。
隣接する2つのI/Oセルの素子形成領域上にそれぞれ跨り且つ当該I/Oセルの長さ方向において内側から外側に向かって順次配置された内側位置および外側位置の2つの入出力信号用電極パッドと、この中間位置の入出力信号用電極パッドの外側の上記I/Oセルの素子形成領域上に配置される電源用電極パッドまたはGND用電極パッドとを具備し、
さらに上記内側位置の入出力信号用電極パッドにおけるI/Oセルでの幅方向の一端側および中間位置の入出力信号用電極パッドにおけるI/Oセルでの幅方向の他端側をそれぞれ所定幅でもって外側位置の電源用電極パッドまたはGND用電極パッドまで延設したものである。
上記I/Oセル領域上に、各入出力用電極パッドに加えて、電源用電極パッドおよび/またはGND用電極パッドを形成する工程を具備した方法である。
入出力信号用電極パッド、電源用電極パッドおよびGND用電極パッドを隣接するI/Oセル領域上に跨って形成する工程を具備した方法である。
電源用電極パッドおよびGND用電極パッドを3つ以上のI/Oセル領域上に跨って形成する工程を具備した方法である。
I/Oセル領域上に内側から外側に向かって、複数の入出力信号用電極パッドを順次形成するとともに、これら入出力信号用電極パッドの外側位置に電源用電極パッドまたはGND用電極パッドを形成する工程を具備し、
且つ上記入出力信号用電極パッドを形成する際に、最も内側に位置する入出力用電極パッドにおけるI/Oセル領域での幅方向における一端側、および中間に位置する入出力信号用電極パッドにおけるI/Oセル領域の幅方向における他端側を、最も外側に位置する電源用またはGND用の電極パッド側に延設するようにした方法である。
以下、本発明の実施の形態に係る半導体集積回路およびその製造方法について、図面を参照しながら説明する。
図1は5層配線構造の半導体集積回路を示しており、また以下の説明において、入出力回路の素子形成領域の外側に設けられていた入出力信号用の電極パッドを入出力回路の素子形成領域上に設けた構造を、素子上パッド構造、略してPOE(Pad On Element)構造ともいう。
すなわち、図1(a)〜(c)において、1は半導体集積回路(半導体チップともいう)、2はPOE構造を有する電極パッドである。8はPSiNなどの第1の保護膜、9はポリイミドなどの第2の保護膜、13は層間絶縁膜、15はシリコン基板である。
図8は本実施の形態における半導体集積回路の製造方法を説明するための断面図で、(a)は入出力回路形成工程を、(b)は積層ビア形成工程を、(c)は電極パッド形成工程を、(d)は保護膜形成工程を、それぞれ説明するためのものである。
次に、図8(b)に示すように、上記パッドメタル11上にワイヤーボンドなどのボンディング工程で生じるクレタリングを抑制するために、ビア12を形成して積層ビア構造を得る。この積層ビア構造は、例えばエッチング法やスパッタ法、メッキ法などの技術を用いて、ビアホールの形成およびビアの埋め込みを行うことにより得られる。
1a 集積回路領域
3 入出力信号用電極パッド
4 電源用電極パッド
5 GND用電極パッド
6 I/0セル
7 最下層メタル
8 第1の保護膜
9 第2の保護膜
10 パッドメタル
11 パッドメタル
12 ビア
13 層間絶縁膜
14 引出し部メタル
15 シリコン基板
18 第1の電源層メタル
Claims (10)
- 集積回路領域と、この集積回路領域と外部とを電気的に接続するための素子形成領域をそれぞれ有する複数のI/Oセルとを具備した半導体集積回路であって、
上記各I/Oセルの素子形成領域上に、入出力信号用電極パッド、電源用電極パッドおよびGND用電極パッドを配置したことを特徴とする半導体集積回路。 - 集積回路領域と、この集積回路領域と外部とを電気的に接続するための素子形成領域をそれぞれ有する複数のI/Oセルとを具備した半導体集積回路であって、
上記各I/Oセルの素子形成領域上に、1つ以上の入出力信号用電極パッドと、電源用電極パッドまたはGND用電極パッドのいずれかを配置したことを特徴とする半導体集積回路。 - 集積回路領域と、この集積回路領域と外部とを電気的に接続するための素子形成領域をそれぞれ有する複数のI/Oセルとを具備した半導体集積回路であって、
隣接する2つのI/Oセルの素子形成領域に跨って、1つ以上の入出力信号用電極パッドと、電源用電極パッドまたはGND用電極パッドのいずれかを配置したことを特徴とする半導体集積回路。 - 集積回路領域と、この集積回路領域と外部とを電気的に接続するための素子形成領域をそれぞれ有する複数のI/Oセルとを具備した半導体集積回路であって、
隣接する2つのI/Oセルの素子形成領域に跨って、1つ以上の入出力信号用電極パッドを配置するとともに、
これら2つのI/Oセル同士に1つ以上の入出力信号用電極パッドが配置されてなるI/Oセルの組を、隣接する2組における4つのI/Oセルの素子形成領域上に跨って電源用電極パッドまたはGND用電極パッドのいずれかを配置したことを特徴とする半導体集積回路。 - 集積回路領域と、この集積回路領域と外部とを電気的に接続するための素子形成領域をそれぞれ有するとともに所定幅で且つ所定長さの複数のI/Oセルとを具備した半導体集積回路であって、
隣接する2つのI/Oセルの素子形成領域上にそれぞれ跨り且つ当該I/Oセルの長さ方向において内側から外側に向かって順次配置された内側位置および外側位置の2つの入出力信号用電極パッドと、この中間位置の入出力信号用電極パッドの外側の上記I/Oセルの素子形成領域に配置される電源用電極パッドまたはGND用電極パッドとを具備し、
さらに内側位置の入出力信号用電極パッドにおけるI/Oセルでの幅方向の一端側を所定幅でもって中間位置の入出力信号電極パッドまで延設するとともに、中間位置の入出力信号用電極パッドにおけるI/Oセルでの幅方向の他端側を所定幅でもって外側位置の電源用電極パッドまたはGND用電極パッドまで延設したことを特徴とする半導体集積回路。 - 集積回路領域と、この集積回路領域と外部とを電気的に接続するための素子形成領域をそれぞれ有するとともに所定幅で且つ所定長さの複数のI/Oセルとを具備した半導体集積回路であって、
隣接する2つのI/Oセルの素子形成領域上にそれぞれ跨り且つ当該I/Oセルの長さ方向において内側から外側に向かって順次配置された内側位置および外側位置の2つの入出力信号用電極パッドと、この中間位置の入出力信号用電極パッドの外側の上記I/Oセルの素子形成領域上に配置される電源用電極パッドまたはGND用電極パッドとを具備し、
さらに上記内側位置の入出力信号用電極パッドにおけるI/Oセルでの幅方向の一端側および中間位置の入出力信号用電極パッドにおけるI/Oセルでの幅方向の他端側をそれぞれ所定幅でもって外側位置の電源用電極パッドまたはGND用電極パッドまで延設したことを特徴とする半導体集積回路。 - 集積回路領域およびI/Oセル領域を形成する工程と、所定位置にビアを形成する工程と、上記ビア上に入出力信号用電極パッドを形成する工程と、上記集積回路領域上に保護膜を形成する工程とを具備する半導体集積回路の製造方法において、
上記I/Oセル領域上に、各入出力用電極パッドに加えて、電源用電極パッドおよび/またはGND用電極パッドを形成する工程を具備したことを特徴とする半導体集積回路の製造方法。 - 請求項7に記載の半導体集積回路の製造方法において、
入出力信号用電極パッド、電源用電極パッドおよびGND用電極パッドを隣接するI/Oセル領域上に跨って形成する工程を具備したことを特徴とする半導体集積回路の製造方法。 - 請求項8に記載の半導体集積回路の製造方法において、
電源用電極パッドおよびGND用電極パッドを3つ以上のI/Oセル領域上に跨って形成する工程を具備したことを特徴とする半導体集積回路の製造方法。 - 請求項8または9に記載の半導体集積回路の製造方法において、
I/Oセル領域上に内側から外側に向かって、複数の入出力信号用電極パッドを順次形成するとともに、これら入出力信号用電極パッドの外側位置に電源用電極パッドまたはGND用電極パッドを形成する工程を具備し、
且つ上記入出力信号用電極パッドを形成する際に、最も内側に位置する入出力用電極パッドにおけるI/Oセル領域での幅方向における一端側、および中間に位置する入出力信号用電極パッドにおけるI/Oセル領域の幅方向における他端側を最も外側に位置する電源用またはGND用の電極パッド側に延設するようにしたことを特徴とする半導体集積回路の製造方法。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005315525A JP2006229186A (ja) | 2005-01-18 | 2005-10-31 | 半導体集積回路およびその製造方法 |
TW095100935A TWI264789B (en) | 2005-01-18 | 2006-01-10 | Semiconductor integrated circuit and its manufacturing method |
US11/333,297 US7501710B2 (en) | 2005-01-18 | 2006-01-18 | Semiconductor integrated circuit and method of manufacturing the same |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005009719 | 2005-01-18 | ||
JP2005315525A JP2006229186A (ja) | 2005-01-18 | 2005-10-31 | 半導体集積回路およびその製造方法 |
Publications (1)
Publication Number | Publication Date |
---|---|
JP2006229186A true JP2006229186A (ja) | 2006-08-31 |
Family
ID=36682971
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2005315525A Pending JP2006229186A (ja) | 2005-01-18 | 2005-10-31 | 半導体集積回路およびその製造方法 |
Country Status (3)
Country | Link |
---|---|
US (1) | US7501710B2 (ja) |
JP (1) | JP2006229186A (ja) |
TW (1) | TWI264789B (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2011066459A (ja) * | 2010-12-28 | 2011-03-31 | Panasonic Corp | 半導体装置 |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4671814B2 (ja) | 2005-09-02 | 2011-04-20 | パナソニック株式会社 | 半導体装置 |
JP5065674B2 (ja) * | 2006-12-28 | 2012-11-07 | ルネサスエレクトロニクス株式会社 | 半導体集積回路装置の製造方法 |
US8549257B2 (en) | 2011-01-10 | 2013-10-01 | Arm Limited | Area efficient arrangement of interface devices within an integrated circuit |
JP5727288B2 (ja) | 2011-04-28 | 2015-06-03 | ルネサスエレクトロニクス株式会社 | 半導体装置、半導体装置の設計方法、半導体装置設計装置、及びプログラム |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2000252363A (ja) * | 1999-03-01 | 2000-09-14 | Kawasaki Steel Corp | 半導体集積回路 |
JP2002016069A (ja) * | 2000-06-29 | 2002-01-18 | Matsushita Electric Ind Co Ltd | 半導体装置およびその製造方法 |
WO2004093188A1 (en) * | 2003-04-09 | 2004-10-28 | Freescale Semiconductor, Inc. | Integrated circuit die i/o cells |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2749241B2 (ja) | 1993-02-16 | 1998-05-13 | ローム株式会社 | 半導体集積回路 |
US6242814B1 (en) * | 1998-07-31 | 2001-06-05 | Lsi Logic Corporation | Universal I/O pad structure for in-line or staggered wire bonding or arrayed flip-chip assembly |
JP4071914B2 (ja) * | 2000-02-25 | 2008-04-02 | 沖電気工業株式会社 | 半導体素子及びこれを用いた半導体装置 |
JP2002299452A (ja) * | 2001-03-30 | 2002-10-11 | Fujitsu Ltd | 半導体集積回路及び電源レイアウト設計方法 |
EP1321984A3 (en) | 2001-08-24 | 2004-01-14 | STMicroelectronics Limited | Semiconductor input/output circuit arrangement |
US6870273B2 (en) * | 2002-04-29 | 2005-03-22 | Pmc-Sierra, Inc. | High speed I/O pad and pad/cell interconnection for flip chips |
US6836026B1 (en) * | 2003-01-14 | 2004-12-28 | Lsi Logic Corporation | Integrated circuit design for both input output limited and core limited integrated circuits |
US7203916B2 (en) * | 2003-06-24 | 2007-04-10 | International Business Machines Corporation | System, method and program product for positioning I/O pads on a chip |
JP2005093575A (ja) * | 2003-09-16 | 2005-04-07 | Nec Electronics Corp | 半導体集積回路装置と配線レイアウト方法 |
-
2005
- 2005-10-31 JP JP2005315525A patent/JP2006229186A/ja active Pending
-
2006
- 2006-01-10 TW TW095100935A patent/TWI264789B/zh not_active IP Right Cessation
- 2006-01-18 US US11/333,297 patent/US7501710B2/en not_active Expired - Fee Related
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2000252363A (ja) * | 1999-03-01 | 2000-09-14 | Kawasaki Steel Corp | 半導体集積回路 |
JP2002016069A (ja) * | 2000-06-29 | 2002-01-18 | Matsushita Electric Ind Co Ltd | 半導体装置およびその製造方法 |
WO2004093188A1 (en) * | 2003-04-09 | 2004-10-28 | Freescale Semiconductor, Inc. | Integrated circuit die i/o cells |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2011066459A (ja) * | 2010-12-28 | 2011-03-31 | Panasonic Corp | 半導体装置 |
Also Published As
Publication number | Publication date |
---|---|
US20060157740A1 (en) | 2006-07-20 |
TWI264789B (en) | 2006-10-21 |
TW200627569A (en) | 2006-08-01 |
US7501710B2 (en) | 2009-03-10 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP5342154B2 (ja) | 半導体装置の製造方法 | |
US20100032196A1 (en) | Multilayer wiring board, semiconductor package and method of manufacturing the same | |
JP2007115922A (ja) | 半導体装置 | |
JP2006229186A (ja) | 半導体集積回路およびその製造方法 | |
JP3886513B2 (ja) | フィルム基板およびその製造方法 | |
JP4293563B2 (ja) | 半導体装置及び半導体パッケージ | |
JP2006303073A (ja) | 半導体装置及びその製造方法 | |
JP2010003953A (ja) | 半導体集積回路 | |
JP2009218264A (ja) | 半導体装置 | |
JP4343124B2 (ja) | 半導体装置 | |
JP2009176833A (ja) | 半導体装置とその製造方法 | |
JP4627632B2 (ja) | 半導体装置 | |
JP5168872B2 (ja) | 半導体集積回路 | |
JP6006527B2 (ja) | 半導体装置 | |
JP2008277595A (ja) | 半導体装置およびその製造方法 | |
JP2008078646A (ja) | パッケージ用印刷回路基板及びその製造方法 | |
JP2008066440A (ja) | 半導体装置およびその製造方法 | |
JP2009060000A (ja) | 半導体装置 | |
JP6001917B2 (ja) | 半導体装置 | |
JP6006528B2 (ja) | 半導体装置 | |
JP2013026291A (ja) | 半導体装置 | |
JP5113509B2 (ja) | 半導体装置 | |
JP4232576B2 (ja) | 半導体装置 | |
TWI557861B (zh) | 線路載板及其製造方法 | |
JP2005252095A (ja) | 半導体集積回路装置 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
RD04 | Notification of resignation of power of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7424 Effective date: 20080430 |
|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20080804 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20110825 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20110830 |
|
A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 20111227 |