JP2006191153A - 半導体装置及びその製造方法 - Google Patents
半導体装置及びその製造方法 Download PDFInfo
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Abstract
【解決手段】 本発明の半導体装置は、半導体チップ上に形成されたパッド2と、前記パッド2上に形成された電極接続部7と、前記パッド2を露出するように前記半導体チップの裏面に形成された開口部14と、前記開口部14の側壁に形成された第1の絶縁膜15と、前記第1の絶縁膜15を有した前記開口部内に形成された金属膜(Cu17)とを具備することを特徴とするものである。
【選択図】 図6
Description
Claims (23)
- 半導体基板の表面側に形成された金属パッドと、
前記金属パッドの一方の主面と電気的に接続され、前記半導体基板の表面側に形成された電極接続部と、
前記半導体基板の裏面から前記金属パッドの他方の主面に至る開口部と、
前記開口部内の側壁に形成された第1の絶縁膜と、
前記開口部内に形成された金属膜とを具備することを特徴とする半導体装置。 - 前記半導体基板の裏面に前記金属膜と電気的に接続された導電端子が形成されていることを特徴とする請求項1に記載の半導体装置。
- 前記金属膜に接続された配線パターンが前記半導体基板の裏面に形成され、前記配線パターン上に前記導電端子が形成されていることを特徴とする請求項2に記載の半導体装置。
- 前記電極接続部は、Ni,Au,Cuから成る積層体もしくはNi,Au,Cu,Auから成る積層体であることを特徴とする請求項1乃至請求項3のいずれかに記載の半導体装置。
- 前記電極接続部上に開口部を有する第2の絶縁膜が前記半導体基板の表面上に形成されていることを特徴とする請求項1乃至請求項4のいずれかに記載の半導体装置。
- 前記第2の絶縁膜は、ポリイミドまたはエポキシ樹脂を含むことを特徴とする請求項5に記載の半導体装置。
- 前記電極接続部と前記金属パッドとの電気的な接続を介在する配線が、前記半導体基板の表面上に形成されていることを特徴とする請求項1乃至請求項6のいずれかに記載の半導体装置。
- 前記請求項1乃至請求項7のいずれか1項に記載の半導体装置と他の半導体装置が積層された積層型の半導体装置であって、相互間の電気的な接続が前記電極接続部を介して行われていることを特徴とする積層型の半導体装置。
- 前記請求項1乃至請求項7のいずれか1項に記載された半導体装置を少なくとも2個積層させた積層型の半導体装置であって、前記少なくとも2個積層された半導体装置のうち一方の半導体装置の前記電極接続部と、もう一方の半導体装置の前記導電端子とが接続されていることを特徴とする積層型の半導体装置。
- 金属パッドが形成された半導体基板と当該半導体基板を支持する支持体とを接着体を用いて貼り合わせる工程と、
前記半導体基板の裏面から開口を形成する工程と、
前記開口の側壁部に絶縁膜を形成した後に、当該開口内に金属膜を形成する工程と、
前記半導体基板の裏面から所定深さ位置までダイシングする工程と、
前記半導体基板と前記支持体とを分離する工程とを有することを特徴とする半導体装置の製造方法。 - 前記金属膜上に電極を形成する工程を有することを特徴とする請求項10に記載の半導体装置の製造方法。
- 前記半導体基板と前記支持体とを分離する工程は、前記接着体を溶液を用いて溶かす工程であることを特徴とする請求項10または請求項11のいずれかに記載の半導体装置の製造方法。
- 前記半導体基板と前記支持体とを分離する工程は、前記接着体としての有機膜をアセトン溶液で溶かす工程であることを特徴とする請求項10乃至請求項12のいずれかに記載の半導体装置の製造方法。
- 前記半導体基板と前記支持体とを分離する工程は、前記接着体としての有機膜を熱により軟化させる工程であることを特徴とする請求項10または請求項11のいずれかに記載の半導体装置の製造方法。
- 前記半導体基板と前記支持体とを分離する工程は、前記接着体としてUVテープを用いる際には、前記支持体として透明ガラスを用いてUV照射する工程であることを特徴とする請求項10または請求項11のいずれかに記載の半導体装置の製造方法。
- 前記金属膜上に電極を形成する工程が、当該金属膜上に配線パターンを形成し、当該配線パターン上に電極を形成する工程であることを特徴とする請求項11に記載の半導体装置の製造方法。
- 前記半導体基板の裏面から開口を形成する工程の前に、その裏面を研磨することを特徴とする請求項10乃至請求項16のいずれかに記載の半導体装置の製造方法。
- 前記金属パッド上に電極接続部を形成する工程を有することを特徴とする請求項10乃至請求項17のいずれかに記載の半導体装置の製造方法。
- 前記支持体として、Si基板、酸化膜、ガラス基板、セラミック基板を用いることを特徴とする請求項10乃至請求項18のいずれかに記載の半導体装置の製造方法。
- 前記金属パッド上に電極接続部を形成する工程は、前記パッド上にNi、Au、Cuから成る積層体もしくはNi、Au、Cu、Auから成る積層体を形成することを特徴とする請求項18に記載の半導体装置の製造方法。
- 前記金属パッド上に電極接続部を形成する工程は、前記パッドに配線パターンを接続し、前記配線パターン上に前記電極接続部を形成することを特徴とする請求項18乃至請求項20のいずれかに記載の半導体装置の製造方法。
- 請求項10乃至請求項21のいずれか1項に記載の半導体装置と他の半導体装置とを積層する工程を有することを特徴とする積層型の半導体装置の製造方法。
- 請求項10乃至請求項21のいずれか1項に記載の半導体装置と他の半導体装置とを積層する工程は、一方の半導体装置の前記電極接続部と、もう一方の半導体装置の前記導電端子とを接続することを特徴とする積層型の半導体装置の製造方法。
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JP2010199220A (ja) * | 2009-02-24 | 2010-09-09 | Sorbus Memory Inc | 積層チップ |
JP2010245571A (ja) * | 2010-07-23 | 2010-10-28 | Oki Semiconductor Co Ltd | 半導体装置の製造方法 |
JP2012256679A (ja) * | 2011-06-08 | 2012-12-27 | Elpida Memory Inc | 半導体装置及びその製造方法 |
JP2014507065A (ja) * | 2010-12-22 | 2014-03-20 | アプライド マテリアルズ インコーポレイテッド | シリコンウエハのシリコン貫通ビアの製造 |
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JP2010199220A (ja) * | 2009-02-24 | 2010-09-09 | Sorbus Memory Inc | 積層チップ |
JP2010245571A (ja) * | 2010-07-23 | 2010-10-28 | Oki Semiconductor Co Ltd | 半導体装置の製造方法 |
JP2014507065A (ja) * | 2010-12-22 | 2014-03-20 | アプライド マテリアルズ インコーポレイテッド | シリコンウエハのシリコン貫通ビアの製造 |
JP2012256679A (ja) * | 2011-06-08 | 2012-12-27 | Elpida Memory Inc | 半導体装置及びその製造方法 |
US9515037B2 (en) | 2011-06-08 | 2016-12-06 | Longitude Semiconductor S.A.R.L. | Semiconductor device having through silicon vias and manufacturing method thereof |
EP2533280A3 (en) * | 2011-06-08 | 2017-08-23 | PS4 Luxco S.a.r.l. | Semiconductor device |
US11211363B2 (en) | 2011-06-08 | 2021-12-28 | Longitude Licensing Limited | Semiconductor device having through silicon vias and manufacturing method thereof |
US11817427B2 (en) | 2011-06-08 | 2023-11-14 | Longitude Licensing Limited | Semiconductor device having through silicon vias and manufacturing method thereof |
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