JP2006073888A - 半導体装置及びその製造方法 - Google Patents
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Abstract
【解決手段】 集積回路4が形成され、集積回路4に電気的に接続された電極6を有する半導体基板2と、半導体基板2の電極6が形成された面に、電極6を避けて形成されてなる樹脂層8と、樹脂層8上において、上方に突出してなる凸部12を有するように形成され、電極6に電気的に接続されてなる配線10と、配線10の凸部12上に形成されてなるはんだ20と、を含み、凸部12の上面部は、はんだ20と凸部12の材料とによって溶食されている。
【選択図】 図1
Description
前記半導体基板の前記電極が形成された面に、前記電極を避けて形成されてなる樹脂層と、
前記樹脂層上において、上方に突出してなる凸部を有するように形成され、前記電極に電気的に接続されてなる配線と、
前記配線の前記凸部上に形成されてなるはんだと、
を含み、
前記凸部の上面部は、前記はんだと前記凸部の材料とによって溶食されている。本発明によれば、配線のランドの凸部の膜厚を、配線のランドの凸部以外の膜厚よりも厚くしたので、溶食された部分に応力が集中しても配線の断線を著しく低減することができ、電気的な接続の信頼性を高めた半導体装置を提供することができる。
(2)この半導体装置において、
前記配線の一部を覆うように形成されたソルダレジスト層をさらに有していてもよい。
(3)この半導体装置において、
前記ソルダレジスト層は、前記凸部の縁部に載っていなくてもよい。
(4)本発明に係る半導体装置の製造方法は、集積回路を有する半導体基板の前記集積回路に電気的に接続された電極が形成された面に、前記電極を避けて樹脂層を形成すること、
前記樹脂層上に上方に突出してなる凸部を有し、前記電極に電気的に接続される配線を形成すること、
前記配線の少なくとも一部を覆い、前記凸部の縁部に載らないようにソルダレジスト層を形成すること、及び、その後、
前記凸部上に、前記樹脂層にて支持されるようにはんだを形成すること、
を含む。本発明によれば、配線のランドの凸部の膜厚を、配線のランドの凸部以外の膜厚よりも厚くしたので、溶食された部分に応力が集中しても配線の断線を著しく低減することができ、電気的な接続の信頼性を高めた半導体装置の製造方法を提供することができる。
Claims (4)
- 集積回路が形成され、前記集積回路に電気的に接続された電極を有する半導体基板と、
前記半導体基板の前記電極が形成された面に、前記電極を避けて形成されてなる樹脂層と、
前記樹脂層上において、上方に突出してなる凸部を有するように形成され、前記電極に電気的に接続されてなる配線と、
前記配線の前記凸部上に形成されてなるはんだと、
を含み、
前記凸部の上面部は、前記はんだと前記凸部の材料とによって溶食されていることを特徴とする半導体装置。 - 請求項1記載の半導体装置において、
前記配線の一部を覆うように形成されたソルダレジスト層をさらに有する半導体装置。 - 請求項2記載の半導体装置において、
前記ソルダレジスト層は、前記凸部の縁部に載っていない半導体装置。 - 集積回路を有する半導体基板の前記集積回路に電気的に接続された電極が形成された面に、前記電極を避けて樹脂層を形成すること、
前記樹脂層上に上方に突出してなる凸部を有し、前記電極に電気的に接続される配線を形成すること、
前記配線の少なくとも一部を覆い、前記凸部の縁部に載らないようにソルダレジスト層を形成すること、及び、その後、
前記凸部上に、前記樹脂層にて支持されるようにはんだを形成すること、
を含む半導体装置の製造方法。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004257331A JP3972211B2 (ja) | 2004-09-03 | 2004-09-03 | 半導体装置及びその製造方法 |
US11/197,338 US7365429B2 (en) | 2004-09-03 | 2005-08-04 | Semiconductor device and method for manufacturing the same |
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Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004257331A JP3972211B2 (ja) | 2004-09-03 | 2004-09-03 | 半導体装置及びその製造方法 |
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Publication Number | Publication Date |
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JP2006073888A true JP2006073888A (ja) | 2006-03-16 |
JP3972211B2 JP3972211B2 (ja) | 2007-09-05 |
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JP (1) | JP3972211B2 (ja) |
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US20080075095A1 (en) * | 2006-09-21 | 2008-03-27 | Sbc Knowledge Ventures, L.P. | Method and system for network communication |
FR2969899B1 (fr) * | 2010-12-23 | 2012-12-21 | Valeo Sys Controle Moteur Sas | Circuit imprime a substrat metallique isole |
CN103545222B (zh) * | 2013-10-24 | 2017-04-26 | 中国电子科技集团公司第四十一研究所 | 一种高可靠性软介质电路的加工制作方法 |
CN105513978B (zh) * | 2014-09-25 | 2018-03-20 | 欣兴电子股份有限公司 | 导电配线的制作方法 |
JP6778585B2 (ja) * | 2016-11-02 | 2020-11-04 | 日東電工株式会社 | 配線回路基板およびその製造方法 |
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TW448524B (en) * | 1997-01-17 | 2001-08-01 | Seiko Epson Corp | Electronic component, semiconductor device, manufacturing method therefor, circuit board and electronic equipment |
JP4024958B2 (ja) | 1999-03-15 | 2007-12-19 | 株式会社ルネサステクノロジ | 半導体装置および半導体実装構造体 |
JP3957928B2 (ja) | 1999-09-07 | 2007-08-15 | 松下電器産業株式会社 | 半導体装置およびその製造方法 |
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JP2004140115A (ja) | 2002-10-16 | 2004-05-13 | Seiko Epson Corp | 半導体装置及びその製造方法、回路基板並びに電子機器 |
JP2004140116A (ja) | 2002-10-16 | 2004-05-13 | Seiko Epson Corp | 半導体装置及びその製造方法、回路基板並びに電子機器 |
JP2004304151A (ja) * | 2003-03-20 | 2004-10-28 | Seiko Epson Corp | 半導体ウエハ、半導体装置及びその製造方法、回路基板並びに電子機器 |
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US7365429B2 (en) | 2008-04-29 |
JP3972211B2 (ja) | 2007-09-05 |
US20060049518A1 (en) | 2006-03-09 |
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