JP2006000978A5 - - Google Patents

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JP2006000978A5
JP2006000978A5 JP2004180404A JP2004180404A JP2006000978A5 JP 2006000978 A5 JP2006000978 A5 JP 2006000978A5 JP 2004180404 A JP2004180404 A JP 2004180404A JP 2004180404 A JP2004180404 A JP 2004180404A JP 2006000978 A5 JP2006000978 A5 JP 2006000978A5
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silicon substrate
dry etching
dimensional shape
processing method
substrate processing
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JP2004180404A
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JP2006000978A (en
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Priority to JP2004180404A priority Critical patent/JP2006000978A/en
Priority claimed from JP2004180404A external-priority patent/JP2006000978A/en
Publication of JP2006000978A publication Critical patent/JP2006000978A/en
Publication of JP2006000978A5 publication Critical patent/JP2006000978A5/ja
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Claims (14)

シリコン基板上に設けたレジスト樹脂を電子ビーム描画及び現像によって三次元形状に形成し、該三次元形状に形成されたレジスト樹脂をマスクとして前記シリコン基板をドライエッチングすることを特徴とするシリコン基板加工方法。 Silicon substrate processing characterized in that a resist resin provided on a silicon substrate is formed in a three-dimensional shape by electron beam drawing and development, and the silicon substrate is dry-etched using the resist resin formed in the three-dimensional shape as a mask Method. シリコン基板上に設けたレジスト樹脂を電子ビーム描画及び現像によって三次元形状に形成し、該三次元形状に形成されたレジスト樹脂をマスクとして該三次元形状に形成されたレジスト樹脂が全てなくなるまで前記シリコン基板をドライエッチングにより加工することで、前記三次元形状をシリコン基板に転写することを特徴とするシリコン基板加工方法。 The resist resin provided on the silicon substrate is formed into a three-dimensional shape by electron beam drawing and development, and the resist resin formed in the three-dimensional shape is completely removed using the resist resin formed in the three-dimensional shape as a mask A silicon substrate processing method , wherein the three-dimensional shape is transferred to a silicon substrate by processing the silicon substrate by dry etching . 前記ドライエッチングにおいてF系ガスまたはF系ガスと酸素の混合ガスを用い、
前記レジストマスクがなくなってから前記ドライエッチングを更に行うことで前記シリコン基板の表面をフッ素化する請求項に記載のシリコン基板加工方法。
In the dry etching, F-based gas or a mixed gas of F-based gas and oxygen is used,
The silicon substrate processing method according to claim 2 , wherein the surface of the silicon substrate is fluorinated by further performing the dry etching after the resist mask disappears.
異方性ドライエッチングにより前記ドライエッチングを行い、前記シリコン基板に形成される三次元形状のパターン高さの微調整は前記レジストマスクと前記シリコン基板との選択比を制御することで行われる請求項1乃至のいずれか1項に記載のシリコン基板加工方法。 The dry etching is performed by anisotropic dry etching, and the fine adjustment of the pattern height of the three-dimensional shape formed on the silicon substrate is performed by controlling the selection ratio between the resist mask and the silicon substrate. 4. The silicon substrate processing method according to any one of 1 to 3 . 前記ドライエッチングをプラズマエッチングで行う際のプラズマ中の電子温度は6〜15eVの範囲内であり、プラズマ密度は108〜1011cm-3の範囲内であり、ガス封入圧力は1Pa未満である請求項1乃至のいずれか1項に記載のシリコン基板加工方法。 When performing the dry etching by plasma etching, the electron temperature in the plasma is in the range of 6 to 15 eV, the plasma density is in the range of 10 8 to 10 11 cm −3 , and the gas charging pressure is less than 1 Pa. The silicon substrate processing method of any one of Claims 1 thru | or 4 . 前記ドライエッチングは誘導結合プラズマ(ICP)を用い、前記選択比の最終的な微調整は、前記シリコン基板に印加する高周波電圧またはバイアス電圧のみを調整することで行う請求項に記載のシリコン基板加工方法。 The silicon substrate according to claim 4 , wherein the dry etching uses inductively coupled plasma (ICP), and final fine adjustment of the selection ratio is performed by adjusting only a high-frequency voltage or a bias voltage applied to the silicon substrate. Processing method. 前記シリコン基板に形成される三次元形状の側壁保護のために前記ドライエッチングのときHBrとO2を添加する請求項乃至のいずれか1項に記載のシリコン基板加工方法。 Silicon substrate machining method according to any one of claims 3 to 6, adding HBr and O 2 when the dry etching for the sidewall protection of the three-dimensional shape formed on the silicon substrate. 側壁保護効果を有する成膜プロセスと前記ドライエッチングとを交互に行う請求項乃至のいずれか1項に記載のシリコン基板加工方法。 Silicon substrate machining method according to any one of claims 3 to 6 perform the said dry etching and deposition process having a side wall protection effect alternately. 前記ドライエッチングで寸法及び特徴が異なる形状を同一のシリコン基板上に同時に加工する請求項乃至のいずれか1項に記載のシリコン基板加工方法。 The silicon substrate processing method according to any one of claims 3 to 8 dimensions and features by dry etching to simultaneously process different shapes on the same silicon substrate. 請求項1乃至のいずれか1項に記載のシリコン基板加工方法により加工されたシリコン基板から構成された光学素子用金型母型。 A mold die for an optical element comprising a silicon substrate processed by the silicon substrate processing method according to any one of claims 1 to 9 . 請求項1乃至のいずれか1項に記載のシリコン基板加工方法により加工されたシリコン基板から構成された光学素子用金型。 A metal mold for an optical element comprising a silicon substrate processed by the silicon substrate processing method according to any one of claims 1 to 9 . 請求項1に記載の光学素子用金型母型を用いて加工された光学素子用金型。 Processed optical element mold by using an optical element die mold according to claim 1 0. 請求項1または1に記載の金型を用いて加工された光学素子。 Processed optical element using a mold according to claim 1 1 or 1 2. 請求項1または1に記載の金型を用いて加工された光通信波長帯域用エシェロン構造型の回折格子。 Claim 1 1 or 1 processed optical communication wavelength band for Echelon structure type diffraction grating with a second mold according to.
JP2004180404A 2004-06-18 2004-06-18 Silicon substrate processing method, die for optical element, mother die of die for optical element, optical element, and diffraction grating Pending JP2006000978A (en)

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JP2004180404A JP2006000978A (en) 2004-06-18 2004-06-18 Silicon substrate processing method, die for optical element, mother die of die for optical element, optical element, and diffraction grating

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JP2004180404A JP2006000978A (en) 2004-06-18 2004-06-18 Silicon substrate processing method, die for optical element, mother die of die for optical element, optical element, and diffraction grating

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JP2006000978A JP2006000978A (en) 2006-01-05
JP2006000978A5 true JP2006000978A5 (en) 2007-07-12

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Publication number Priority date Publication date Assignee Title
JP5353101B2 (en) * 2008-07-29 2013-11-27 大日本印刷株式会社 Microstructure formation method
JP5468325B2 (en) * 2009-07-27 2014-04-09 株式会社アルバック Device manufacturing method
JP2014135435A (en) * 2013-01-11 2014-07-24 Toshiba Corp Semiconductor device manufacturing method
JP6646888B2 (en) * 2015-09-09 2020-02-14 大日本印刷株式会社 Convex structure, concave structure, and method of manufacturing convex structure

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JPS62161532A (en) * 1986-01-13 1987-07-17 Omron Tateisi Electronics Co Manufacture of plastic lens and so on
JPH01180503A (en) * 1988-01-13 1989-07-18 Omron Tateisi Electron Co Manufacture of stamper for manufacturing optical element
JP3666905B2 (en) * 1994-08-01 2005-06-29 リコー光学株式会社 Optical device and manufacturing method thereof
JPH09230121A (en) * 1996-02-27 1997-09-05 Olympus Optical Co Ltd Production of diffraction grating plate
US6127278A (en) * 1997-06-02 2000-10-03 Applied Materials, Inc. Etch process for forming high aspect ratio trenched in silicon
JP2001284319A (en) * 2000-03-30 2001-10-12 Seiko Epson Corp Dry etching process and method of manufacturing semiconductor including the same
JP2002043296A (en) * 2000-07-28 2002-02-08 Matsushita Electric Ind Co Ltd Method and device for dry etching
US6743727B2 (en) * 2001-06-05 2004-06-01 International Business Machines Corporation Method of etching high aspect ratio openings
JP2004107765A (en) * 2002-09-20 2004-04-08 Japan Science & Technology Corp Method for treating silicon surface and metal surface

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